mirror of https://github.com/acidanthera/audk.git
MdeModulePkg/SdMmcPciHcDxe: Add retries for sync commands
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=1140 To increase the resiliency driver will now attempt to retry the commands that failed due to the CRC error up to 5 times. This should address the problems with the commands that fail due to random condition on links. This should also help the boards on which CMD13 is particularly unstable after switching the link frequency. Cc: Hao A Wu <hao.a.wu@intel.com> Cc: Marcin Wojtas <mw@semihalf.com> Cc: Zhichao Gao <zhichao.gao@intel.com> Cc: Liming Gao <liming.gao@intel.com> Signed-off-by: Mateusz Albecki <mateusz.albecki@intel.com> Reviewed-by: Hao A Wu <hao.a.wu@intel.com>
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@ -7,7 +7,7 @@
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It would expose EFI_SD_MMC_PASS_THRU_PROTOCOL for upper layer use.
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Copyright (c) 2018-2019, NVIDIA CORPORATION. All rights reserved.
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Copyright (c) 2015 - 2019, Intel Corporation. All rights reserved.<BR>
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Copyright (c) 2015 - 2020, Intel Corporation. All rights reserved.<BR>
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SPDX-License-Identifier: BSD-2-Clause-Patent
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**/
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@ -974,6 +974,58 @@ SdMmcPciHcDriverBindingStop (
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return Status;
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}
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/**
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Execute TRB synchronously.
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@param[in] Private Pointer to driver private data.
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@param[in] Trb Pointer to TRB to execute.
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@retval EFI_SUCCESS TRB executed successfully.
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@retval Other TRB failed.
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**/
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EFI_STATUS
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SdMmcPassThruExecSyncTrb (
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IN SD_MMC_HC_PRIVATE_DATA *Private,
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IN SD_MMC_HC_TRB *Trb
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)
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{
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EFI_STATUS Status;
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EFI_TPL OldTpl;
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//
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// Wait async I/O list is empty before execute sync I/O operation.
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//
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while (TRUE) {
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OldTpl = gBS->RaiseTPL (TPL_NOTIFY);
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if (IsListEmpty (&Private->Queue)) {
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gBS->RestoreTPL (OldTpl);
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break;
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}
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gBS->RestoreTPL (OldTpl);
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}
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while (Trb->Retries) {
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Status = SdMmcWaitTrbEnv (Private, Trb);
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if (EFI_ERROR (Status)) {
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return Status;
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}
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Status = SdMmcExecTrb (Private, Trb);
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if (EFI_ERROR (Status)) {
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return Status;
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}
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Status = SdMmcWaitTrbResult (Private, Trb);
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if (Status == EFI_CRC_ERROR) {
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Trb->Retries--;
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} else {
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return Status;
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}
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}
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return Status;
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}
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/**
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Sends SD command to an SD card that is attached to the SD controller.
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@ -1023,7 +1075,6 @@ SdMmcPassThruPassThru (
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EFI_STATUS Status;
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SD_MMC_HC_PRIVATE_DATA *Private;
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SD_MMC_HC_TRB *Trb;
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EFI_TPL OldTpl;
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if ((This == NULL) || (Packet == NULL)) {
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return EFI_INVALID_PARAMETER;
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@ -1066,34 +1117,8 @@ SdMmcPassThruPassThru (
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return EFI_SUCCESS;
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}
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//
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// Wait async I/O list is empty before execute sync I/O operation.
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//
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while (TRUE) {
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OldTpl = gBS->RaiseTPL (TPL_NOTIFY);
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if (IsListEmpty (&Private->Queue)) {
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gBS->RestoreTPL (OldTpl);
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break;
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}
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gBS->RestoreTPL (OldTpl);
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}
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Status = SdMmcPassThruExecSyncTrb (Private, Trb);
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Status = SdMmcWaitTrbEnv (Private, Trb);
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if (EFI_ERROR (Status)) {
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goto Done;
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}
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Status = SdMmcExecTrb (Private, Trb);
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if (EFI_ERROR (Status)) {
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goto Done;
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}
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Status = SdMmcWaitTrbResult (Private, Trb);
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if (EFI_ERROR (Status)) {
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goto Done;
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}
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Done:
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SdMmcFreeTrb (Trb);
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return Status;
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@ -3,7 +3,7 @@
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Provides some data structure definitions used by the SD/MMC host controller driver.
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Copyright (c) 2018-2019, NVIDIA CORPORATION. All rights reserved.
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Copyright (c) 2015, Intel Corporation. All rights reserved.<BR>
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Copyright (c) 2015 - 2020, Intel Corporation. All rights reserved.<BR>
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SPDX-License-Identifier: BSD-2-Clause-Patent
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**/
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@ -130,6 +130,8 @@ typedef struct {
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#define SD_MMC_HC_TRB_SIG SIGNATURE_32 ('T', 'R', 'B', 'T')
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#define SD_MMC_TRB_RETRIES 5
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//
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// TRB (Transfer Request Block) contains information for the cmd request.
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//
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@ -152,6 +154,7 @@ typedef struct {
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EFI_EVENT Event;
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BOOLEAN Started;
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UINT64 Timeout;
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UINT32 Retries;
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SD_MMC_HC_ADMA_32_DESC_LINE *Adma32Desc;
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SD_MMC_HC_ADMA_64_V3_DESC_LINE *Adma64V3Desc;
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@ -1683,6 +1683,7 @@ SdMmcCreateTrb (
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Trb->Event = Event;
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Trb->Started = FALSE;
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Trb->Timeout = Packet->Timeout;
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Trb->Retries = SD_MMC_TRB_RETRIES;
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Trb->Private = Private;
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if ((Packet->InTransferLength != 0) && (Packet->InDataBuffer != NULL)) {
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