mirror of https://github.com/acidanthera/audk.git
MdePkg/BaseSynchronizationLib GCC: fix InternalSyncCompareExchange16()
The CMPXCHG instruction has the following operands: - AX (implicit, CompareValue): input and output - destination operand (*Value): input and output - source operand (ExchangeValue): input The IA32 version of InternalSyncCompareExchange16() correctly marks CompareValue as input/output, but it marks (*Value) only as input. The X64 version of InternalSyncCompareExchange16() attempts to mark both CompareValue and (*Value) as input/output, but it doesn't use the appropriate constraints for either operand. Fix these issues. Furthermore, prefer the short "+" constraint for I/O operands over the <output-operand-number> constraint that can be applied to the input instances of I/O operands. Cc: Liming Gao <liming.gao@intel.com> Cc: Michael D Kinney <michael.d.kinney@intel.com> Ref: https://bugzilla.tianocore.org/show_bug.cgi?id=1208 Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Laszlo Ersek <lersek@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Acked-by: Michael D Kinney <michael.d.kinney@intel.com> Reviewed-by: Liming Gao <liming.gao@intel.com>
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@ -115,11 +115,10 @@ InternalSyncCompareExchange16 (
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{
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__asm__ __volatile__ (
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"lock \n\t"
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"cmpxchgw %1, %2 \n\t"
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: "=a" (CompareValue) // %0
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: "q" (ExchangeValue), // %1
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"m" (*Value), // %2
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"0" (CompareValue) // %3
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"cmpxchgw %2, %1 \n\t"
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: "+a" (CompareValue), // %0
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"+m" (*Value) // %1
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: "q" (ExchangeValue) // %2
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: "memory",
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"cc"
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);
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@ -115,12 +115,10 @@ InternalSyncCompareExchange16 (
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{
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__asm__ __volatile__ (
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"lock \n\t"
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"cmpxchgw %3, %1 \n\t"
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: "=a" (CompareValue), // %0
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"=m" (*Value) // %1
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: "a" (CompareValue), // %2
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"r" (ExchangeValue), // %3
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"m" (*Value) // %4
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"cmpxchgw %2, %1 \n\t"
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: "+a" (CompareValue), // %0
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"+m" (*Value) // %1
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: "r" (ExchangeValue) // %2
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: "memory",
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"cc"
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);
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