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ArmPkg/ArmGicV3Dxe: configure all interrupts as non-secure Group-1 

Reassign all interrupts to non-secure Group-1 if the GIC has its DS
(Disable Security) bit set. In this case, it is safe to assume that we
own the GIC, and that no other firmware has performed any configuration
yet, which means it is up to us to reconfigure the interrupts so they
can be taken by the non-secure firmware.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
This commit is contained in:
Ard Biesheuvel 2016-06-22 16:23:57 +02:00
parent bf57a42a0e
commit c7fefb6906
2 changed files with 19 additions and 2 deletions
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16
ArmPkg/Drivers/ArmGic/GicV3/ArmGicV3Dxe.c
View File

@ -297,6 +297,22 @@ GicV3DxeInitialize (
MpId = ArmReadMpidr ();
CpuTarget = MpId & (ARM_CORE_AFF0 | ARM_CORE_AFF1 | ARM_CORE_AFF2 | ARM_CORE_AFF3);
if ((MmioRead32 (mGicDistributorBase + ARM_GIC_ICDDCR) & ARM_GIC_ICDDCR_DS) != 0) {
//
// If the Disable Security (DS) control bit is set, we are dealing with a
// GIC that has only one security state. In this case, let's assume we are
// executing in non-secure state (which is appropriate for DXE modules)
// and that no other firmware has performed any configuration on the GIC.
// This means we need to reconfigure all interrupts to non-secure Group 1
// first.
//
MmioWrite32 (mGicRedistributorsBase + ARM_GICR_CTLR_FRAME_SIZE + ARM_GIC_ICDISR, 0xffffffff);
for (Index = 32; Index < mGicNumInterrupts; Index += 32) {
MmioWrite32 (mGicDistributorBase + ARM_GIC_ICDISR + Index / 8, 0xffffffff);
}
}
// Route the SPIs to the primary CPU. SPIs start at the INTID 32
for (Index = 0; Index < (mGicNumInterrupts - 32); Index++) {
MmioWrite32 (mGicDistributorBase + ARM_GICD_IROUTER + (Index * 8), CpuTarget | ARM_GICD_IROUTER_IRM);

5
ArmPkg/Include/Library/ArmGicLib.h
View File

@ -47,8 +47,9 @@
// GICv3 specific registers
#define ARM_GICD_IROUTER 0x6100 // Interrupt Routing Registers
// the Affinity Routing Enable (ARE) bit in GICD_CTLR
#define ARM_GIC_ICDDCR_ARE (1 << 4)
// GICD_CTLR bits
#define ARM_GIC_ICDDCR_ARE (1 << 4) // Affinity Routing Enable (ARE)
#define ARM_GIC_ICDDCR_DS (1 << 6) // Disable Security (DS)
//
// GIC Redistributor