mirror of https://github.com/acidanthera/audk.git
Roll back the previous change in MdePkg BaseLib Ia32 Thunk16.S and EcpPkg GlueLib BaseLib Ia32 Thunk16.S, and still use the hard code offset in them to avoid GCC compiler create the unexpected instruction.
Signed-off-by: lgao4 Reviewed-by: rsun3 git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@12898 6f19259b-4bc3-4df7-8a09-765794883524
This commit is contained in:
lgao4
parent
855790a56f
commit
c8641de387
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@ -24,27 +24,6 @@
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.globl ASM_PFX(m16Start), ASM_PFX(m16Size), ASM_PFX(mThunk16Attr), ASM_PFX(m16Gdt), ASM_PFX(m16GdtrBase), ASM_PFX(mTransition)
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.globl ASM_PFX(InternalAsmThunk16)
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# define the structure of IA32_REGS
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.set _EDI, 0 #size 4
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.set _ESI, 4 #size 4
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.set _EBP, 8 #size 4
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.set _ESP, 12 #size 4
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.set _EBX, 16 #size 4
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.set _EDX, 20 #size 4
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.set _ECX, 24 #size 4
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.set _EAX, 28 #size 4
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.set _DS, 32 #size 2
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.set _ES, 34 #size 2
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.set _FS, 36 #size 2
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.set _GS, 38 #size 2
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.set _EFLAGS, 40 #size 4
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.set _EIP, 44 #size 4
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.set _CS, 48 #size 2
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.set _SS, 50 #size 2
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.set IA32_REGS_SIZE, 52
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.text
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ASM_PFX(m16Start):
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SavedGdt: .space 6
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@ -78,17 +57,15 @@ ASM_PFX(ThunkAttr): .space 4
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2:
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xorw %ax, %ax # xor eax, eax
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movl %ss, %eax # mov ax, ss
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.byte 0x67
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lea IA32_REGS_SIZE(%esp), %bp
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.byte 0x66
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mov %ebp, (_ESP - IA32_REGS_SIZE)(%esi)
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mov (_EIP - IA32_REGS_SIZE)(%esi), %ebx
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.byte 0x67, 0x66, 0x8d, 0x6c, 0x24, 0x34, 0x66
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mov %ebp, 0xffffffd8(%esi)
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mov 0xfffffff8(%esi), %ebx
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shlw $4, %ax # shl eax, 4
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addw %ax, %bp # add ebp, eax
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.byte 0x66, 0xb8 # mov eax, imm32
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SavedCr4: .space 4
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movl %eax, %cr4
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lgdtw %cs:(SavedGdt - L_Base1)(%edi)
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lgdtw %cs:0xfffffff2(%edi)
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.byte 0x66, 0xb8 # mov eax, imm32
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SavedCr0: .space 4
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movl %eax, %cr0
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@ -123,15 +100,15 @@ ASM_PFX(ToUserCode):
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L_Base:
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popw %bp # ebp <- offset L_Base
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.byte 0x67; # address size override
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push (IA32_REGS_SIZE + 2)(%esp)
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lea (L_RealMode - L_Base)(%esi), %eax
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push 54(%esp)
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lea 0xc(%esi), %eax
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push %eax
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lret
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L_RealMode:
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mov %edx, %cs:(SavedSs - L_Base)(%esi)
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mov %bx, %cs:(SavedEsp - L_Base)(%esi)
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lidtw %cs:(_16Idtr - L_Base)(%esi)
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mov %edx, %cs:0xffffffc5(%esi)
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mov %bx, %cs:0xffffffcb(%esi)
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lidtw %cs:0xffffffd7(%esi)
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popaw # popad actually
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pop %ds
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pop %es
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@ -172,41 +149,41 @@ ASM_PFX(InternalAsmThunk16):
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push %fs
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push %gs
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movl 36(%esp), %esi # esi <- RegSet
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movzwl _SS(%esi), %edx
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mov _ESP(%esi), %edi
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add $(-(IA32_REGS_SIZE + 4)), %edi
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movzwl 0x32(%esi), %edx
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mov 0xc(%esi), %edi
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add $0xffffffc8, %edi
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movl %edi, %ebx # ebx <- stack offset
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imul $0x10, %edx, %eax
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push $(IA32_REGS_SIZE / 4)
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push $0xd
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addl %eax, %edi # edi <- linear address of 16-bit stack
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pop %ecx
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rep
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movsl # copy RegSet
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movl 40(%esp), %eax # eax <- address of transition code
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movl %edx, %esi # esi <- 16-bit stack segment
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lea (SavedCr0 - ASM_PFX(m16Start))(%eax), %edx
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lea 0x61(%eax), %edx
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movl %eax, %ecx
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andl $0xf, %ecx
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shll $12, %eax
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lea (ASM_PFX(BackFromUserCode) - ASM_PFX(m16Start))(%ecx), %ecx
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lea 0x6(%ecx), %ecx
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movw %cx, %ax
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stosl # [edi] <- return address of user code
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sgdtl (SavedGdt - SavedCr0)(%edx)
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sgdtl 0xffffff9f(%edx)
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sidtl 0x24(%esp)
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movl %cr0, %eax
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movl %eax, (%edx) # save CR0 in SavedCr0
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andl $0x7ffffffe, %eax # clear PE, PG bits
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movl %cr4, %ebp
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mov %ebp, (SavedCr4 - SavedCr0)(%edx)
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mov %ebp, 0xfffffff1(%edx)
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andl $0x300, %ebp # clear all but PCE and OSFXSR bits
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pushl $0x10
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pop %ecx # ecx <- selector for data segments
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lgdtl (_16Gdtr - SavedCr0)(%edx)
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lgdtl 0x20(%edx)
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pushfl
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lcall *(_EntryPoint - SavedCr0)(%edx)
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lcall *0x14(%edx)
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popfl
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lidtl 0x24(%esp)
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lea -IA32_REGS_SIZE(%ebp), %eax
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lea 0xffffffcc(%ebp), %eax
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pop %gs
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pop %fs
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pop %es
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@ -24,27 +24,6 @@
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ASM_GLOBAL ASM_PFX(m16Start), ASM_PFX(m16Size), ASM_PFX(mThunk16Attr), ASM_PFX(m16Gdt), ASM_PFX(m16GdtrBase), ASM_PFX(mTransition)
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ASM_GLOBAL ASM_PFX(InternalAsmThunk16)
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# define the structure of IA32_REGS
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.set _EDI, 0 #size 4
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.set _ESI, 4 #size 4
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.set _EBP, 8 #size 4
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.set _ESP, 12 #size 4
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.set _EBX, 16 #size 4
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.set _EDX, 20 #size 4
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.set _ECX, 24 #size 4
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.set _EAX, 28 #size 4
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.set _DS, 32 #size 2
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.set _ES, 34 #size 2
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.set _FS, 36 #size 2
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.set _GS, 38 #size 2
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.set _EFLAGS, 40 #size 4
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.set _EIP, 44 #size 4
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.set _CS, 48 #size 2
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.set _SS, 50 #size 2
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.set IA32_REGS_SIZE, 52
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.text
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ASM_PFX(m16Start):
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SavedGdt: .space 6
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@ -78,17 +57,15 @@ ASM_PFX(ThunkAttr): .space 4
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2:
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xorw %ax, %ax # xor eax, eax
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movl %ss, %eax # mov ax, ss
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.byte 0x67
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lea IA32_REGS_SIZE(%esp), %bp
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.byte 0x66
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mov %ebp, (_ESP - IA32_REGS_SIZE)(%esi)
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mov (_EIP - IA32_REGS_SIZE)(%esi), %ebx
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.byte 0x67, 0x66, 0x8d, 0x6c, 0x24, 0x34, 0x66
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mov %ebp, 0xffffffd8(%esi)
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mov 0xfffffff8(%esi), %ebx
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shlw $4, %ax # shl eax, 4
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addw %ax, %bp # add ebp, eax
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.byte 0x66, 0xb8 # mov eax, imm32
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SavedCr4: .space 4
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movl %eax, %cr4
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lgdtw %cs:(SavedGdt - L_Base1)(%edi)
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lgdtw %cs:0xfffffff2(%edi)
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.byte 0x66, 0xb8 # mov eax, imm32
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SavedCr0: .space 4
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movl %eax, %cr0
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@ -123,15 +100,15 @@ ASM_PFX(ToUserCode):
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L_Base:
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popw %bp # ebp <- offset L_Base
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.byte 0x67; # address size override
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push (IA32_REGS_SIZE + 2)(%esp)
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lea (L_RealMode - L_Base)(%esi), %eax
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push 54(%esp)
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lea 0xc(%esi), %eax
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push %eax
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lret
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L_RealMode:
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mov %edx, %cs:(SavedSs - L_Base)(%esi)
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mov %bx, %cs:(SavedEsp - L_Base)(%esi)
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lidtw %cs:(_16Idtr - L_Base)(%esi)
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mov %edx, %cs:0xffffffc5(%esi)
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mov %bx, %cs:0xffffffcb(%esi)
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lidtw %cs:0xffffffd7(%esi)
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popaw # popad actually
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pop %ds
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pop %es
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@ -172,41 +149,41 @@ ASM_PFX(InternalAsmThunk16):
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push %fs
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push %gs
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movl 36(%esp), %esi # esi <- RegSet
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movzwl _SS(%esi), %edx
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mov _ESP(%esi), %edi
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add $(-(IA32_REGS_SIZE + 4)), %edi
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movzwl 0x32(%esi), %edx
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mov 0xc(%esi), %edi
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add $0xffffffc8, %edi
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movl %edi, %ebx # ebx <- stack offset
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imul $0x10, %edx, %eax
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push $(IA32_REGS_SIZE / 4)
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push $0xd
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addl %eax, %edi # edi <- linear address of 16-bit stack
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pop %ecx
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rep
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movsl # copy RegSet
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movl 40(%esp), %eax # eax <- address of transition code
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movl %edx, %esi # esi <- 16-bit stack segment
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lea (SavedCr0 - ASM_PFX(m16Start))(%eax), %edx
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lea 0x61(%eax), %edx
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movl %eax, %ecx
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andl $0xf, %ecx
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shll $12, %eax
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lea (ASM_PFX(BackFromUserCode) - ASM_PFX(m16Start))(%ecx), %ecx
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lea 0x6(%ecx), %ecx
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movw %cx, %ax
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stosl # [edi] <- return address of user code
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sgdtl (SavedGdt - SavedCr0)(%edx)
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sgdtl 0xffffff9f(%edx)
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sidtl 0x24(%esp)
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movl %cr0, %eax
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movl %eax, (%edx) # save CR0 in SavedCr0
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andl $0x7ffffffe, %eax # clear PE, PG bits
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movl %cr4, %ebp
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mov %ebp, (SavedCr4 - SavedCr0)(%edx)
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mov %ebp, 0xfffffff1(%edx)
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andl $0x300, %ebp # clear all but PCE and OSFXSR bits
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pushl $0x10
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pop %ecx # ecx <- selector for data segments
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lgdtl (_16Gdtr - SavedCr0)(%edx)
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lgdtl 0x20(%edx)
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pushfl
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lcall *(_EntryPoint - SavedCr0)(%edx)
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lcall *0x14(%edx)
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popfl
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lidtl 0x24(%esp)
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lea -IA32_REGS_SIZE(%ebp), %eax
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lea 0xffffffcc(%ebp), %eax
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pop %gs
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pop %fs
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pop %es
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