mirror of https://github.com/acidanthera/audk.git
MdePkg/BaseMemoryLibOptDxe: add accelerated AARCH64 routines
This adds AARCH64 support to BaseMemoryLibOptDxe, based on the cortex-strings library. All string routines are accelerated except ScanMem16, ScanMem32, ScanMem64 and IsZeroBuffer, which can wait for another day. (Very few occurrences exist in the codebase) Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Liming Gao <liming.gao@intel.com>
This commit is contained in:
Ard Biesheuvel
parent
a37f660599
commit
c86cd1e175
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//
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// Copyright (c) 2013, Linaro Limited
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// All rights reserved.
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//
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// Redistribution and use in source and binary forms, with or without
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// modification, are permitted provided that the following conditions are met:
|
||||
// * Redistributions of source code must retain the above copyright
|
||||
// notice, this list of conditions and the following disclaimer.
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||||
// * Redistributions in binary form must reproduce the above copyright
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||||
// notice, this list of conditions and the following disclaimer in the
|
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// documentation and/or other materials provided with the distribution.
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||||
// * Neither the name of the Linaro nor the
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// names of its contributors may be used to endorse or promote products
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||||
// derived from this software without specific prior written permission.
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||||
//
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// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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// HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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||||
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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//
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// Assumptions:
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//
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// ARMv8-a, AArch64
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//
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// Parameters and result.
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#define src1 x0
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#define src2 x1
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#define limit x2
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#define result x0
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// Internal variables.
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#define data1 x3
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#define data1w w3
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#define data2 x4
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#define data2w w4
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#define diff x6
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#define endloop x7
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#define tmp1 x8
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#define tmp2 x9
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#define pos x11
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#define limit_wd x12
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#define mask x13
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.p2align 6
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ASM_GLOBAL ASM_PFX(InternalMemCompareMem)
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ASM_PFX(InternalMemCompareMem):
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eor tmp1, src1, src2
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tst tmp1, #7
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b.ne .Lmisaligned8
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ands tmp1, src1, #7
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b.ne .Lmutual_align
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add limit_wd, limit, #7
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lsr limit_wd, limit_wd, #3
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// Start of performance-critical section -- one 64B cache line.
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.Lloop_aligned:
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ldr data1, [src1], #8
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ldr data2, [src2], #8
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.Lstart_realigned:
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subs limit_wd, limit_wd, #1
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eor diff, data1, data2 // Non-zero if differences found.
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csinv endloop, diff, xzr, ne // Last Dword or differences.
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cbz endloop, .Lloop_aligned
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// End of performance-critical section -- one 64B cache line.
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// Not reached the limit, must have found a diff.
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cbnz limit_wd, .Lnot_limit
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// Limit % 8 == 0 => all bytes significant.
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ands limit, limit, #7
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b.eq .Lnot_limit
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lsl limit, limit, #3 // Bits -> bytes.
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mov mask, #~0
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lsl mask, mask, limit
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bic data1, data1, mask
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bic data2, data2, mask
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orr diff, diff, mask
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.Lnot_limit:
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rev diff, diff
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rev data1, data1
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rev data2, data2
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// The MS-non-zero bit of DIFF marks either the first bit
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// that is different, or the end of the significant data.
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// Shifting left now will bring the critical information into the
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// top bits.
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clz pos, diff
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lsl data1, data1, pos
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lsl data2, data2, pos
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// But we need to zero-extend (char is unsigned) the value and then
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// perform a signed 32-bit subtraction.
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lsr data1, data1, #56
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sub result, data1, data2, lsr #56
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ret
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.Lmutual_align:
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// Sources are mutually aligned, but are not currently at an
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// alignment boundary. Round down the addresses and then mask off
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// the bytes that precede the start point.
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bic src1, src1, #7
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bic src2, src2, #7
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add limit, limit, tmp1 // Adjust the limit for the extra.
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lsl tmp1, tmp1, #3 // Bytes beyond alignment -> bits.
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ldr data1, [src1], #8
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neg tmp1, tmp1 // Bits to alignment -64.
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ldr data2, [src2], #8
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mov tmp2, #~0
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// Little-endian. Early bytes are at LSB.
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lsr tmp2, tmp2, tmp1 // Shift (tmp1 & 63).
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add limit_wd, limit, #7
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orr data1, data1, tmp2
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orr data2, data2, tmp2
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lsr limit_wd, limit_wd, #3
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b .Lstart_realigned
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.p2align 6
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.Lmisaligned8:
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sub limit, limit, #1
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1:
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// Perhaps we can do better than this.
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ldrb data1w, [src1], #1
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ldrb data2w, [src2], #1
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subs limit, limit, #1
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ccmp data1w, data2w, #0, cs // NZCV = 0b0000.
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b.eq 1b
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sub result, data1, data2
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ret
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@ -0,0 +1,284 @@
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//
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// Copyright (c) 2012 - 2016, Linaro Limited
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// All rights reserved.
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//
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// Redistribution and use in source and binary forms, with or without
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// modification, are permitted provided that the following conditions are met:
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// * Redistributions of source code must retain the above copyright
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// notice, this list of conditions and the following disclaimer.
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// * Redistributions in binary form must reproduce the above copyright
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// notice, this list of conditions and the following disclaimer in the
|
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// documentation and/or other materials provided with the distribution.
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// * Neither the name of the Linaro nor the
|
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// names of its contributors may be used to endorse or promote products
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// derived from this software without specific prior written permission.
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//
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// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
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// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
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// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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// HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
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// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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//
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//
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// Copyright (c) 2015 ARM Ltd
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// All rights reserved.
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//
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// Redistribution and use in source and binary forms, with or without
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// modification, are permitted provided that the following conditions
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// are met:
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// 1. Redistributions of source code must retain the above copyright
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// notice, this list of conditions and the following disclaimer.
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// 2. Redistributions in binary form must reproduce the above copyright
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// notice, this list of conditions and the following disclaimer in the
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// documentation and/or other materials provided with the distribution.
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// 3. The name of the company may not be used to endorse or promote
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// products derived from this software without specific prior written
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// permission.
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//
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// THIS SOFTWARE IS PROVIDED BY ARM LTD ``AS IS'' AND ANY EXPRESS OR IMPLIED
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// WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
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// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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// IN NO EVENT SHALL ARM LTD BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED
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// TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
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// PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
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// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
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// NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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// SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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//
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// Assumptions:
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//
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// ARMv8-a, AArch64, unaligned accesses.
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//
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//
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#define dstin x0
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#define src x1
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#define count x2
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#define dst x3
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#define srcend x4
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#define dstend x5
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#define A_l x6
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#define A_lw w6
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#define A_h x7
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#define A_hw w7
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#define B_l x8
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#define B_lw w8
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#define B_h x9
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#define C_l x10
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#define C_h x11
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#define D_l x12
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#define D_h x13
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#define E_l x14
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#define E_h x15
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#define F_l srcend
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#define F_h dst
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#define tmp1 x9
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#define tmp2 x3
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#define L(l) .L ## l
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// Copies are split into 3 main cases: small copies of up to 16 bytes,
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// medium copies of 17..96 bytes which are fully unrolled. Large copies
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// of more than 96 bytes align the destination and use an unrolled loop
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// processing 64 bytes per iteration.
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// Small and medium copies read all data before writing, allowing any
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// kind of overlap, and memmove tailcalls memcpy for these cases as
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// well as non-overlapping copies.
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__memcpy:
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prfm PLDL1KEEP, [src]
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add srcend, src, count
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add dstend, dstin, count
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cmp count, 16
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b.ls L(copy16)
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cmp count, 96
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b.hi L(copy_long)
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// Medium copies: 17..96 bytes.
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sub tmp1, count, 1
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ldp A_l, A_h, [src]
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tbnz tmp1, 6, L(copy96)
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ldp D_l, D_h, [srcend, -16]
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tbz tmp1, 5, 1f
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ldp B_l, B_h, [src, 16]
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ldp C_l, C_h, [srcend, -32]
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stp B_l, B_h, [dstin, 16]
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stp C_l, C_h, [dstend, -32]
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1:
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stp A_l, A_h, [dstin]
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stp D_l, D_h, [dstend, -16]
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ret
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.p2align 4
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// Small copies: 0..16 bytes.
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L(copy16):
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cmp count, 8
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b.lo 1f
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ldr A_l, [src]
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ldr A_h, [srcend, -8]
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str A_l, [dstin]
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str A_h, [dstend, -8]
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ret
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.p2align 4
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1:
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tbz count, 2, 1f
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ldr A_lw, [src]
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ldr A_hw, [srcend, -4]
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str A_lw, [dstin]
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str A_hw, [dstend, -4]
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ret
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// Copy 0..3 bytes. Use a branchless sequence that copies the same
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// byte 3 times if count==1, or the 2nd byte twice if count==2.
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1:
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cbz count, 2f
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lsr tmp1, count, 1
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ldrb A_lw, [src]
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ldrb A_hw, [srcend, -1]
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ldrb B_lw, [src, tmp1]
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strb A_lw, [dstin]
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strb B_lw, [dstin, tmp1]
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strb A_hw, [dstend, -1]
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2: ret
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.p2align 4
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// Copy 64..96 bytes. Copy 64 bytes from the start and
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// 32 bytes from the end.
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L(copy96):
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ldp B_l, B_h, [src, 16]
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ldp C_l, C_h, [src, 32]
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ldp D_l, D_h, [src, 48]
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ldp E_l, E_h, [srcend, -32]
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ldp F_l, F_h, [srcend, -16]
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stp A_l, A_h, [dstin]
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stp B_l, B_h, [dstin, 16]
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stp C_l, C_h, [dstin, 32]
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stp D_l, D_h, [dstin, 48]
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stp E_l, E_h, [dstend, -32]
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stp F_l, F_h, [dstend, -16]
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ret
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// Align DST to 16 byte alignment so that we don't cross cache line
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// boundaries on both loads and stores. There are at least 96 bytes
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// to copy, so copy 16 bytes unaligned and then align. The loop
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// copies 64 bytes per iteration and prefetches one iteration ahead.
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.p2align 4
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L(copy_long):
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and tmp1, dstin, 15
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bic dst, dstin, 15
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ldp D_l, D_h, [src]
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sub src, src, tmp1
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add count, count, tmp1 // Count is now 16 too large.
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ldp A_l, A_h, [src, 16]
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stp D_l, D_h, [dstin]
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ldp B_l, B_h, [src, 32]
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ldp C_l, C_h, [src, 48]
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ldp D_l, D_h, [src, 64]!
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subs count, count, 128 + 16 // Test and readjust count.
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b.ls 2f
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1:
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stp A_l, A_h, [dst, 16]
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ldp A_l, A_h, [src, 16]
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stp B_l, B_h, [dst, 32]
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ldp B_l, B_h, [src, 32]
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stp C_l, C_h, [dst, 48]
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ldp C_l, C_h, [src, 48]
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stp D_l, D_h, [dst, 64]!
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ldp D_l, D_h, [src, 64]!
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subs count, count, 64
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b.hi 1b
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// Write the last full set of 64 bytes. The remainder is at most 64
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// bytes, so it is safe to always copy 64 bytes from the end even if
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// there is just 1 byte left.
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2:
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ldp E_l, E_h, [srcend, -64]
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stp A_l, A_h, [dst, 16]
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ldp A_l, A_h, [srcend, -48]
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stp B_l, B_h, [dst, 32]
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ldp B_l, B_h, [srcend, -32]
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stp C_l, C_h, [dst, 48]
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ldp C_l, C_h, [srcend, -16]
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stp D_l, D_h, [dst, 64]
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stp E_l, E_h, [dstend, -64]
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stp A_l, A_h, [dstend, -48]
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stp B_l, B_h, [dstend, -32]
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stp C_l, C_h, [dstend, -16]
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ret
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//
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// All memmoves up to 96 bytes are done by memcpy as it supports overlaps.
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// Larger backwards copies are also handled by memcpy. The only remaining
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// case is forward large copies. The destination is aligned, and an
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// unrolled loop processes 64 bytes per iteration.
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//
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ASM_GLOBAL ASM_PFX(InternalMemCopyMem)
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ASM_PFX(InternalMemCopyMem):
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sub tmp2, dstin, src
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cmp count, 96
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ccmp tmp2, count, 2, hi
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b.hs __memcpy
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cbz tmp2, 3f
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add dstend, dstin, count
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add srcend, src, count
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// Align dstend to 16 byte alignment so that we don't cross cache line
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// boundaries on both loads and stores. There are at least 96 bytes
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// to copy, so copy 16 bytes unaligned and then align. The loop
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// copies 64 bytes per iteration and prefetches one iteration ahead.
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and tmp2, dstend, 15
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ldp D_l, D_h, [srcend, -16]
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sub srcend, srcend, tmp2
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sub count, count, tmp2
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ldp A_l, A_h, [srcend, -16]
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stp D_l, D_h, [dstend, -16]
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ldp B_l, B_h, [srcend, -32]
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ldp C_l, C_h, [srcend, -48]
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ldp D_l, D_h, [srcend, -64]!
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sub dstend, dstend, tmp2
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subs count, count, 128
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b.ls 2f
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nop
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1:
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stp A_l, A_h, [dstend, -16]
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ldp A_l, A_h, [srcend, -16]
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stp B_l, B_h, [dstend, -32]
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ldp B_l, B_h, [srcend, -32]
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stp C_l, C_h, [dstend, -48]
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ldp C_l, C_h, [srcend, -48]
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stp D_l, D_h, [dstend, -64]!
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ldp D_l, D_h, [srcend, -64]!
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subs count, count, 64
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b.hi 1b
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// Write the last full set of 64 bytes. The remainder is at most 64
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// bytes, so it is safe to always copy 64 bytes from the start even if
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// there is just 1 byte left.
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2:
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ldp E_l, E_h, [src, 48]
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stp A_l, A_h, [dstend, -16]
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ldp A_l, A_h, [src, 32]
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stp B_l, B_h, [dstend, -32]
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ldp B_l, B_h, [src, 16]
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stp C_l, C_h, [dstend, -48]
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ldp C_l, C_h, [src]
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stp D_l, D_h, [dstend, -64]
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stp E_l, E_h, [dstin, 48]
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stp A_l, A_h, [dstin, 32]
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stp B_l, B_h, [dstin, 16]
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stp C_l, C_h, [dstin]
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3: ret
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@ -0,0 +1,161 @@
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//
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// Copyright (c) 2014, ARM Limited
|
||||
// All rights Reserved.
|
||||
//
|
||||
// Redistribution and use in source and binary forms, with or without
|
||||
// modification, are permitted provided that the following conditions are met:
|
||||
// * Redistributions of source code must retain the above copyright
|
||||
// notice, this list of conditions and the following disclaimer.
|
||||
// * Redistributions in binary form must reproduce the above copyright
|
||||
// notice, this list of conditions and the following disclaimer in the
|
||||
// documentation and/or other materials provided with the distribution.
|
||||
// * Neither the name of the company nor the names of its contributors
|
||||
// may be used to endorse or promote products derived from this
|
||||
// software without specific prior written permission.
|
||||
//
|
||||
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
// HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
//
|
||||
|
||||
// Assumptions:
|
||||
//
|
||||
// ARMv8-a, AArch64
|
||||
// Neon Available.
|
||||
//
|
||||
|
||||
// Arguments and results.
|
||||
#define srcin x0
|
||||
#define cntin x1
|
||||
#define chrin w2
|
||||
|
||||
#define result x0
|
||||
|
||||
#define src x3
|
||||
#define tmp x4
|
||||
#define wtmp2 w5
|
||||
#define synd x6
|
||||
#define soff x9
|
||||
#define cntrem x10
|
||||
|
||||
#define vrepchr v0
|
||||
#define vdata1 v1
|
||||
#define vdata2 v2
|
||||
#define vhas_chr1 v3
|
||||
#define vhas_chr2 v4
|
||||
#define vrepmask v5
|
||||
#define vend v6
|
||||
|
||||
//
|
||||
// Core algorithm:
|
||||
//
|
||||
// For each 32-byte chunk we calculate a 64-bit syndrome value, with two bits
|
||||
// per byte. For each tuple, bit 0 is set if the relevant byte matched the
|
||||
// requested character and bit 1 is not used (faster than using a 32bit
|
||||
// syndrome). Since the bits in the syndrome reflect exactly the order in which
|
||||
// things occur in the original string, counting trailing zeros allows to
|
||||
// identify exactly which byte has matched.
|
||||
//
|
||||
|
||||
ASM_GLOBAL ASM_PFX(InternalMemScanMem8)
|
||||
ASM_PFX(InternalMemScanMem8):
|
||||
// Do not dereference srcin if no bytes to compare.
|
||||
cbz cntin, .Lzero_length
|
||||
//
|
||||
// Magic constant 0x40100401 allows us to identify which lane matches
|
||||
// the requested byte.
|
||||
//
|
||||
mov wtmp2, #0x0401
|
||||
movk wtmp2, #0x4010, lsl #16
|
||||
dup vrepchr.16b, chrin
|
||||
// Work with aligned 32-byte chunks
|
||||
bic src, srcin, #31
|
||||
dup vrepmask.4s, wtmp2
|
||||
ands soff, srcin, #31
|
||||
and cntrem, cntin, #31
|
||||
b.eq .Lloop
|
||||
|
||||
//
|
||||
// Input string is not 32-byte aligned. We calculate the syndrome
|
||||
// value for the aligned 32 bytes block containing the first bytes
|
||||
// and mask the irrelevant part.
|
||||
//
|
||||
|
||||
ld1 {vdata1.16b, vdata2.16b}, [src], #32
|
||||
sub tmp, soff, #32
|
||||
adds cntin, cntin, tmp
|
||||
cmeq vhas_chr1.16b, vdata1.16b, vrepchr.16b
|
||||
cmeq vhas_chr2.16b, vdata2.16b, vrepchr.16b
|
||||
and vhas_chr1.16b, vhas_chr1.16b, vrepmask.16b
|
||||
and vhas_chr2.16b, vhas_chr2.16b, vrepmask.16b
|
||||
addp vend.16b, vhas_chr1.16b, vhas_chr2.16b // 256->128
|
||||
addp vend.16b, vend.16b, vend.16b // 128->64
|
||||
mov synd, vend.d[0]
|
||||
// Clear the soff*2 lower bits
|
||||
lsl tmp, soff, #1
|
||||
lsr synd, synd, tmp
|
||||
lsl synd, synd, tmp
|
||||
// The first block can also be the last
|
||||
b.ls .Lmasklast
|
||||
// Have we found something already?
|
||||
cbnz synd, .Ltail
|
||||
|
||||
.Lloop:
|
||||
ld1 {vdata1.16b, vdata2.16b}, [src], #32
|
||||
subs cntin, cntin, #32
|
||||
cmeq vhas_chr1.16b, vdata1.16b, vrepchr.16b
|
||||
cmeq vhas_chr2.16b, vdata2.16b, vrepchr.16b
|
||||
// If we're out of data we finish regardless of the result
|
||||
b.ls .Lend
|
||||
// Use a fast check for the termination condition
|
||||
orr vend.16b, vhas_chr1.16b, vhas_chr2.16b
|
||||
addp vend.2d, vend.2d, vend.2d
|
||||
mov synd, vend.d[0]
|
||||
// We're not out of data, loop if we haven't found the character
|
||||
cbz synd, .Lloop
|
||||
|
||||
.Lend:
|
||||
// Termination condition found, let's calculate the syndrome value
|
||||
and vhas_chr1.16b, vhas_chr1.16b, vrepmask.16b
|
||||
and vhas_chr2.16b, vhas_chr2.16b, vrepmask.16b
|
||||
addp vend.16b, vhas_chr1.16b, vhas_chr2.16b // 256->128
|
||||
addp vend.16b, vend.16b, vend.16b // 128->64
|
||||
mov synd, vend.d[0]
|
||||
// Only do the clear for the last possible block
|
||||
b.hi .Ltail
|
||||
|
||||
.Lmasklast:
|
||||
// Clear the (32 - ((cntrem + soff) % 32)) * 2 upper bits
|
||||
add tmp, cntrem, soff
|
||||
and tmp, tmp, #31
|
||||
sub tmp, tmp, #32
|
||||
neg tmp, tmp, lsl #1
|
||||
lsl synd, synd, tmp
|
||||
lsr synd, synd, tmp
|
||||
|
||||
.Ltail:
|
||||
// Count the trailing zeros using bit reversing
|
||||
rbit synd, synd
|
||||
// Compensate the last post-increment
|
||||
sub src, src, #32
|
||||
// Check that we have found a character
|
||||
cmp synd, #0
|
||||
// And count the leading zeros
|
||||
clz synd, synd
|
||||
// Compute the potential result
|
||||
add result, src, synd, lsr #1
|
||||
// Select result or NULL
|
||||
csel result, xzr, result, eq
|
||||
ret
|
||||
|
||||
.Lzero_length:
|
||||
mov result, #0
|
||||
ret
|
||||
|
|
@ -0,0 +1,244 @@
|
|||
//
|
||||
// Copyright (c) 2012 - 2016, Linaro Limited
|
||||
// All rights reserved.
|
||||
//
|
||||
// Redistribution and use in source and binary forms, with or without
|
||||
// modification, are permitted provided that the following conditions are met:
|
||||
// * Redistributions of source code must retain the above copyright
|
||||
// notice, this list of conditions and the following disclaimer.
|
||||
// * Redistributions in binary form must reproduce the above copyright
|
||||
// notice, this list of conditions and the following disclaimer in the
|
||||
// documentation and/or other materials provided with the distribution.
|
||||
// * Neither the name of the Linaro nor the
|
||||
// names of its contributors may be used to endorse or promote products
|
||||
// derived from this software without specific prior written permission.
|
||||
//
|
||||
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
// HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
//
|
||||
|
||||
//
|
||||
// Copyright (c) 2015 ARM Ltd
|
||||
// All rights reserved.
|
||||
//
|
||||
// Redistribution and use in source and binary forms, with or without
|
||||
// modification, are permitted provided that the following conditions
|
||||
// are met:
|
||||
// 1. Redistributions of source code must retain the above copyright
|
||||
// notice, this list of conditions and the following disclaimer.
|
||||
// 2. Redistributions in binary form must reproduce the above copyright
|
||||
// notice, this list of conditions and the following disclaimer in the
|
||||
// documentation and/or other materials provided with the distribution.
|
||||
// 3. The name of the company may not be used to endorse or promote
|
||||
// products derived from this software without specific prior written
|
||||
// permission.
|
||||
//
|
||||
// THIS SOFTWARE IS PROVIDED BY ARM LTD ``AS IS'' AND ANY EXPRESS OR IMPLIED
|
||||
// WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
|
||||
// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
|
||||
// IN NO EVENT SHALL ARM LTD BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED
|
||||
// TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
|
||||
// PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
|
||||
// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
|
||||
// NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
|
||||
// SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
//
|
||||
|
||||
// Assumptions:
|
||||
//
|
||||
// ARMv8-a, AArch64, unaligned accesses
|
||||
//
|
||||
//
|
||||
|
||||
#define dstin x0
|
||||
#define count x1
|
||||
#define val x2
|
||||
#define valw w2
|
||||
#define dst x3
|
||||
#define dstend x4
|
||||
#define tmp1 x5
|
||||
#define tmp1w w5
|
||||
#define tmp2 x6
|
||||
#define tmp2w w6
|
||||
#define zva_len x7
|
||||
#define zva_lenw w7
|
||||
|
||||
#define L(l) .L ## l
|
||||
|
||||
ASM_GLOBAL ASM_PFX(InternalMemSetMem16)
|
||||
ASM_PFX(InternalMemSetMem16):
|
||||
dup v0.8H, valw
|
||||
b 0f
|
||||
|
||||
ASM_GLOBAL ASM_PFX(InternalMemSetMem32)
|
||||
ASM_PFX(InternalMemSetMem32):
|
||||
dup v0.4S, valw
|
||||
b 0f
|
||||
|
||||
ASM_GLOBAL ASM_PFX(InternalMemSetMem64)
|
||||
ASM_PFX(InternalMemSetMem64):
|
||||
dup v0.2D, val
|
||||
b 0f
|
||||
|
||||
ASM_GLOBAL ASM_PFX(InternalMemZeroMem)
|
||||
ASM_PFX(InternalMemZeroMem):
|
||||
movi v0.16B, #0
|
||||
b 0f
|
||||
|
||||
ASM_GLOBAL ASM_PFX(InternalMemSetMem)
|
||||
ASM_PFX(InternalMemSetMem):
|
||||
dup v0.16B, valw
|
||||
0: add dstend, dstin, count
|
||||
mov val, v0.D[0]
|
||||
|
||||
cmp count, 96
|
||||
b.hi L(set_long)
|
||||
cmp count, 16
|
||||
b.hs L(set_medium)
|
||||
|
||||
// Set 0..15 bytes.
|
||||
tbz count, 3, 1f
|
||||
str val, [dstin]
|
||||
str val, [dstend, -8]
|
||||
ret
|
||||
nop
|
||||
1: tbz count, 2, 2f
|
||||
str valw, [dstin]
|
||||
str valw, [dstend, -4]
|
||||
ret
|
||||
2: cbz count, 3f
|
||||
strb valw, [dstin]
|
||||
tbz count, 1, 3f
|
||||
strh valw, [dstend, -2]
|
||||
3: ret
|
||||
|
||||
// Set 17..96 bytes.
|
||||
L(set_medium):
|
||||
str q0, [dstin]
|
||||
tbnz count, 6, L(set96)
|
||||
str q0, [dstend, -16]
|
||||
tbz count, 5, 1f
|
||||
str q0, [dstin, 16]
|
||||
str q0, [dstend, -32]
|
||||
1: ret
|
||||
|
||||
.p2align 4
|
||||
// Set 64..96 bytes. Write 64 bytes from the start and
|
||||
// 32 bytes from the end.
|
||||
L(set96):
|
||||
str q0, [dstin, 16]
|
||||
stp q0, q0, [dstin, 32]
|
||||
stp q0, q0, [dstend, -32]
|
||||
ret
|
||||
|
||||
.p2align 3
|
||||
nop
|
||||
L(set_long):
|
||||
bic dst, dstin, 15
|
||||
str q0, [dstin]
|
||||
cmp count, 256
|
||||
ccmp val, 0, 0, cs
|
||||
b.eq L(try_zva)
|
||||
L(no_zva):
|
||||
sub count, dstend, dst // Count is 16 too large.
|
||||
add dst, dst, 16
|
||||
sub count, count, 64 + 16 // Adjust count and bias for loop.
|
||||
1: stp q0, q0, [dst], 64
|
||||
stp q0, q0, [dst, -32]
|
||||
L(tail64):
|
||||
subs count, count, 64
|
||||
b.hi 1b
|
||||
2: stp q0, q0, [dstend, -64]
|
||||
stp q0, q0, [dstend, -32]
|
||||
ret
|
||||
|
||||
.p2align 3
|
||||
L(try_zva):
|
||||
mrs tmp1, dczid_el0
|
||||
tbnz tmp1w, 4, L(no_zva)
|
||||
and tmp1w, tmp1w, 15
|
||||
cmp tmp1w, 4 // ZVA size is 64 bytes.
|
||||
b.ne L(zva_128)
|
||||
|
||||
// Write the first and last 64 byte aligned block using stp rather
|
||||
// than using DC ZVA. This is faster on some cores.
|
||||
L(zva_64):
|
||||
str q0, [dst, 16]
|
||||
stp q0, q0, [dst, 32]
|
||||
bic dst, dst, 63
|
||||
stp q0, q0, [dst, 64]
|
||||
stp q0, q0, [dst, 96]
|
||||
sub count, dstend, dst // Count is now 128 too large.
|
||||
sub count, count, 128+64+64 // Adjust count and bias for loop.
|
||||
add dst, dst, 128
|
||||
nop
|
||||
1: dc zva, dst
|
||||
add dst, dst, 64
|
||||
subs count, count, 64
|
||||
b.hi 1b
|
||||
stp q0, q0, [dst, 0]
|
||||
stp q0, q0, [dst, 32]
|
||||
stp q0, q0, [dstend, -64]
|
||||
stp q0, q0, [dstend, -32]
|
||||
ret
|
||||
|
||||
.p2align 3
|
||||
L(zva_128):
|
||||
cmp tmp1w, 5 // ZVA size is 128 bytes.
|
||||
b.ne L(zva_other)
|
||||
|
||||
str q0, [dst, 16]
|
||||
stp q0, q0, [dst, 32]
|
||||
stp q0, q0, [dst, 64]
|
||||
stp q0, q0, [dst, 96]
|
||||
bic dst, dst, 127
|
||||
sub count, dstend, dst // Count is now 128 too large.
|
||||
sub count, count, 128+128 // Adjust count and bias for loop.
|
||||
add dst, dst, 128
|
||||
1: dc zva, dst
|
||||
add dst, dst, 128
|
||||
subs count, count, 128
|
||||
b.hi 1b
|
||||
stp q0, q0, [dstend, -128]
|
||||
stp q0, q0, [dstend, -96]
|
||||
stp q0, q0, [dstend, -64]
|
||||
stp q0, q0, [dstend, -32]
|
||||
ret
|
||||
|
||||
L(zva_other):
|
||||
mov tmp2w, 4
|
||||
lsl zva_lenw, tmp2w, tmp1w
|
||||
add tmp1, zva_len, 64 // Max alignment bytes written.
|
||||
cmp count, tmp1
|
||||
blo L(no_zva)
|
||||
|
||||
sub tmp2, zva_len, 1
|
||||
add tmp1, dst, zva_len
|
||||
add dst, dst, 16
|
||||
subs count, tmp1, dst // Actual alignment bytes to write.
|
||||
bic tmp1, tmp1, tmp2 // Aligned dc zva start address.
|
||||
beq 2f
|
||||
1: stp q0, q0, [dst], 64
|
||||
stp q0, q0, [dst, -32]
|
||||
subs count, count, 64
|
||||
b.hi 1b
|
||||
2: mov dst, tmp1
|
||||
sub count, dstend, tmp1 // Remaining bytes to write.
|
||||
subs count, count, zva_len
|
||||
b.lo 4f
|
||||
3: dc zva, dst
|
||||
add dst, dst, zva_len
|
||||
subs count, count, zva_len
|
||||
b.hs 3b
|
||||
4: add count, count, zva_len
|
||||
b L(tail64)
|
||||
|
|
@ -27,7 +27,7 @@
|
|||
|
||||
|
||||
#
|
||||
# VALID_ARCHITECTURES = IA32 X64 ARM
|
||||
# VALID_ARCHITECTURES = IA32 X64 ARM AARCH64
|
||||
#
|
||||
|
||||
[Sources]
|
||||
|
|
@ -127,6 +127,13 @@
|
|||
Arm/CopyMem.asm |RVCT
|
||||
Arm/CompareMem.asm |RVCT
|
||||
|
||||
[Sources.AARCH64]
|
||||
AArch64/ScanMem.S
|
||||
AArch64/SetMem.S
|
||||
AArch64/CopyMem.S
|
||||
AArch64/CompareMem.S
|
||||
|
||||
[Sources.ARM, Sources.AARCH64]
|
||||
Arm/ScanMemGeneric.c
|
||||
|
||||
[Sources]
|
||||
|
|
|
|||
Loading…
Reference in New Issue