mirror of https://github.com/acidanthera/audk.git
Save and disable CPU interrupt before programming MTRR settings, and restore the CPU interrupt after programming MTRR setting.
signed-off-by: Kinney, Michael D <michael.d.kinney@intel.com> reviewed-by: Bjorge, Erik C <erik.c.bjorge@intel.com> reviewed-by: Jeff Fan <jeff.fan@intel.com> git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@13749 6f19259b-4bc3-4df7-8a09-765794883524
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vanjeff
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c878cee473
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@ -20,6 +20,14 @@
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#include <Library/BaseMemoryLib.h>
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#include <Library/DebugLib.h>
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//
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// Context to save and restore when MTRRs are programmed
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//
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typedef struct {
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UINTN Cr4;
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BOOLEAN InterruptState;
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} MTRR_CONTEXT;
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//
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// This table defines the offset, base and length of the fixed MTRRs
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//
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@ -166,16 +174,19 @@ MtrrGetDefaultMemoryType (
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This function will do some preparation for programming MTRRs:
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disable cache, invalid cache and disable MTRR caching functionality
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@return CR4 value before changing.
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@param[out] Pointer to context to save
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**/
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UINTN
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VOID
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PreMtrrChange (
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VOID
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OUT MTRR_CONTEXT *MtrrContext
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)
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{
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UINTN Value;
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//
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// Disable interrupts and save current interrupt state
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//
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MtrrContext->InterruptState = SaveAndDisableInterrupts();
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//
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// Enter no fill cache mode, CD=1(Bit30), NW=0 (Bit29)
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//
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@ -184,8 +195,8 @@ PreMtrrChange (
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//
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// Save original CR4 value and clear PGE flag (Bit 7)
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//
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Value = AsmReadCr4 ();
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AsmWriteCr4 (Value & (~BIT7));
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MtrrContext->Cr4 = AsmReadCr4 ();
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AsmWriteCr4 (MtrrContext->Cr4 & (~BIT7));
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//
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// Flush all TLBs
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@ -196,11 +207,6 @@ PreMtrrChange (
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// Disable Mtrrs
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//
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AsmMsrBitFieldWrite64 (MTRR_LIB_IA32_MTRR_DEF_TYPE, 10, 11, 0);
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//
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// Return original CR4 value
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//
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return Value;
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}
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/**
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@ -209,12 +215,12 @@ PreMtrrChange (
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This function will do some clean up after programming MTRRs:
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Flush all TLBs, re-enable caching, restore CR4.
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@param Cr4 CR4 value to restore
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@param[in] Pointer to context to restore
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**/
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VOID
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PostMtrrChangeEnableCache (
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IN UINTN Cr4
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IN MTRR_CONTEXT *MtrrContext
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)
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{
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//
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@ -230,7 +236,12 @@ PostMtrrChangeEnableCache (
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//
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// Restore original CR4 value
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//
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AsmWriteCr4 (Cr4);
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AsmWriteCr4 (MtrrContext->Cr4);
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//
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// Restore original interrupt state
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//
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SetInterruptState (MtrrContext->InterruptState);
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}
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/**
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@ -239,12 +250,12 @@ PostMtrrChangeEnableCache (
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This function will do some clean up after programming MTRRs:
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enable MTRR caching functionality, and enable cache
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@param Cr4 CR4 value to restore
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@param[in] Pointer to context to restore
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**/
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VOID
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PostMtrrChange (
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IN UINTN Cr4
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IN MTRR_CONTEXT *MtrrContext
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)
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{
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//
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@ -252,7 +263,7 @@ PostMtrrChange (
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//
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AsmMsrBitFieldWrite64 (MTRR_LIB_IA32_MTRR_DEF_TYPE, 10, 11, 3);
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PostMtrrChangeEnableCache (Cr4);
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PostMtrrChangeEnableCache (MtrrContext);
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}
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@ -704,11 +715,11 @@ InvalidateMtrr (
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IN VARIABLE_MTRR *VariableMtrr
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)
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{
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UINTN Index;
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UINTN Cr4;
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UINTN VariableMtrrCount;
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UINTN Index;
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UINTN VariableMtrrCount;
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MTRR_CONTEXT MtrrContext;
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Cr4 = PreMtrrChange ();
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PreMtrrChange (&MtrrContext);
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Index = 0;
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VariableMtrrCount = GetVariableMtrrCount ();
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while (Index < VariableMtrrCount) {
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@ -719,7 +730,7 @@ InvalidateMtrr (
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}
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Index ++;
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}
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PostMtrrChange (Cr4);
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PostMtrrChange (&MtrrContext);
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}
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@ -744,10 +755,10 @@ ProgramVariableMtrr (
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IN UINT64 MtrrValidAddressMask
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)
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{
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UINT64 TempQword;
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UINTN Cr4;
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UINT64 TempQword;
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MTRR_CONTEXT MtrrContext;
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Cr4 = PreMtrrChange ();
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PreMtrrChange (&MtrrContext);
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//
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// MTRR Physical Base
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@ -764,7 +775,7 @@ ProgramVariableMtrr (
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(TempQword & MtrrValidAddressMask) | MTRR_LIB_CACHE_MTRR_ENABLED
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);
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PostMtrrChange (Cr4);
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PostMtrrChange (&MtrrContext);
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}
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@ -953,10 +964,10 @@ MtrrSetMemoryAttribute (
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UINT32 UsedMtrr;
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UINT64 MtrrValidBitsMask;
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UINT64 MtrrValidAddressMask;
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UINTN Cr4;
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BOOLEAN OverwriteExistingMtrr;
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UINT32 FirmwareVariableMtrrCount;
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UINT32 VariableMtrrEnd;
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MTRR_CONTEXT MtrrContext;
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DEBUG((DEBUG_CACHE, "MtrrSetMemoryAttribute() %a:%016lx-%016lx\n", mMtrrMemoryCacheTypeShortName[Attribute], BaseAddress, Length));
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@ -995,9 +1006,9 @@ MtrrSetMemoryAttribute (
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//
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Status = RETURN_SUCCESS;
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while ((BaseAddress < BASE_1MB) && (Length > 0) && Status == RETURN_SUCCESS) {
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Cr4 = PreMtrrChange ();
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PreMtrrChange (&MtrrContext);
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Status = ProgramFixedMtrr (MemoryType, &BaseAddress, &Length);
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PostMtrrChange (Cr4);
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PostMtrrChange (&MtrrContext);
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if (RETURN_ERROR (Status)) {
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goto Done;
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}
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@ -1353,15 +1364,15 @@ MtrrSetVariableMtrr (
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IN MTRR_VARIABLE_SETTINGS *VariableSettings
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)
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{
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UINTN Cr4;
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MTRR_CONTEXT MtrrContext;
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if (!IsMtrrSupported ()) {
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return VariableSettings;
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}
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Cr4 = PreMtrrChange ();
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PreMtrrChange (&MtrrContext);
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MtrrSetVariableMtrrWorker (VariableSettings);
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PostMtrrChange (Cr4);
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PostMtrrChange (&MtrrContext);
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return VariableSettings;
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}
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@ -1430,15 +1441,15 @@ MtrrSetFixedMtrr (
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IN MTRR_FIXED_SETTINGS *FixedSettings
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)
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{
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UINTN Cr4;
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MTRR_CONTEXT MtrrContext;
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if (!IsMtrrSupported ()) {
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return FixedSettings;
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}
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Cr4 = PreMtrrChange ();
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PreMtrrChange (&MtrrContext);
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MtrrSetFixedMtrrWorker (FixedSettings);
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PostMtrrChange (Cr4);
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PostMtrrChange (&MtrrContext);
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return FixedSettings;
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}
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@ -1495,13 +1506,13 @@ MtrrSetAllMtrrs (
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IN MTRR_SETTINGS *MtrrSetting
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)
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{
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UINTN Cr4;
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MTRR_CONTEXT MtrrContext;
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if (!IsMtrrSupported ()) {
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return MtrrSetting;
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}
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Cr4 = PreMtrrChange ();
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PreMtrrChange (&MtrrContext);
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//
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// Set fixed MTRRs
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@ -1518,7 +1529,7 @@ MtrrSetAllMtrrs (
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//
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AsmWriteMsr64 (MTRR_LIB_IA32_MTRR_DEF_TYPE, MtrrSetting->MtrrDefType);
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PostMtrrChangeEnableCache (Cr4);
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PostMtrrChangeEnableCache (&MtrrContext);
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return MtrrSetting;
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}
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