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UefiCpuPkg CpuDxe: Enhance get mtrr mask logic.

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In order to not use the deprecated macro, refine
get mtrr mask value logic.

Cc: Jeff Fan <jeff.fan@intel.com>
Cc: Ruiyu Ni <ruiyu.ni@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Eric Dong <eric.dong@intel.com>
Reviewed-by: Ruiyu Ni <ruiyu.ni@intel.com>
This commit is contained in:
Eric Dong 2017-08-02 18:29:09 +08:00
parent 055fa1c666
commit c894f83fe3
1 changed files with 6 additions and 7 deletions
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13
UefiCpuPkg/CpuDxe/CpuDxe.c
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@ -25,8 +25,8 @@
BOOLEAN InterruptState = FALSE; BOOLEAN InterruptState = FALSE;
EFI_HANDLE mCpuHandle = NULL; EFI_HANDLE mCpuHandle = NULL;
BOOLEAN mIsFlushingGCD; BOOLEAN mIsFlushingGCD;
UINT64 mValidMtrrAddressMask = MTRR_LIB_CACHE_VALID_ADDRESS; UINT64 mValidMtrrAddressMask;
UINT64 mValidMtrrBitsMask = MTRR_LIB_MSR_VALID_MASK; UINT64 mValidMtrrBitsMask;
UINT64 mTimerPeriod = 0; UINT64 mTimerPeriod = 0;
FIXED_MTRR mFixedMtrrTable[] = { FIXED_MTRR mFixedMtrrTable[] = {
@ -510,13 +510,12 @@ InitializeMtrrMask (
AsmCpuid (0x80000008, &RegEax, NULL, NULL, NULL); AsmCpuid (0x80000008, &RegEax, NULL, NULL, NULL);
PhysicalAddressBits = (UINT8) RegEax; PhysicalAddressBits = (UINT8) RegEax;
mValidMtrrBitsMask = LShiftU64 (1, PhysicalAddressBits) - 1;
mValidMtrrAddressMask = mValidMtrrBitsMask & 0xfffffffffffff000ULL;
} else { } else {
mValidMtrrBitsMask = MTRR_LIB_MSR_VALID_MASK; PhysicalAddressBits = 36;
mValidMtrrAddressMask = MTRR_LIB_CACHE_VALID_ADDRESS;
} }
mValidMtrrBitsMask = LShiftU64 (1, PhysicalAddressBits) - 1;
mValidMtrrAddressMask = mValidMtrrBitsMask & 0xfffffffffffff000ULL;
} }
/** /**