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MdeModulePkg BaseSerialPortLib16550: Correct MemoryLimit and MemoryBase offset. 

Their offset in PCI-to-PCI Bridge Configuration Space.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Liming Gao <liming.gao@intel.com>
Reviewed-by: Michael Kinney <michael.d.kinney@intel.com>
Reviewed-by: Guo Dong <guo.dong@intel.com>

git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@16402 6f19259b-4bc3-4df7-8a09-765794883524
This commit is contained in:
Liming Gao 2014-11-19 02:30:21 +00:00 committed by lgao4
parent 18a7dbbc02
commit c9e0bba385
1 changed files with 6 additions and 6 deletions
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12
MdeModulePkg/Library/BaseSerialPortLib16550/BaseSerialPortLib16550.c
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@ -244,8 +244,8 @@ GetSerialRegisterBase (
// Retrieve and verify the I/O or MMIO decode window in the PCI to PCI Bridge // Retrieve and verify the I/O or MMIO decode window in the PCI to PCI Bridge
// //
if (PcdGetBool (PcdSerialUseMmio)) { if (PcdGetBool (PcdSerialUseMmio)) {
MemoryLimit = PciRead16 (PciLibAddress + OFFSET_OF (PCI_BRIDGE_CONTROL_REGISTER, MemoryLimit)) & 0xfff0; MemoryLimit = PciRead16 (PciLibAddress + OFFSET_OF (PCI_TYPE01, Bridge.MemoryLimit)) & 0xfff0;
MemoryBase = PciRead16 (PciLibAddress + OFFSET_OF (PCI_BRIDGE_CONTROL_REGISTER, MemoryBase)) & 0xfff0; MemoryBase = PciRead16 (PciLibAddress + OFFSET_OF (PCI_TYPE01, Bridge.MemoryBase)) & 0xfff0;
// //
// If PCI Bridge MMIO window is disabled, then return 0 // If PCI Bridge MMIO window is disabled, then return 0
@ -263,17 +263,17 @@ GetSerialRegisterBase (
ParentMemoryBase = MemoryBase; ParentMemoryBase = MemoryBase;
ParentMemoryLimit = MemoryLimit; ParentMemoryLimit = MemoryLimit;
} else { } else {
IoLimit = PciRead8 (PciLibAddress + OFFSET_OF (PCI_BRIDGE_CONTROL_REGISTER, IoLimit)); IoLimit = PciRead8 (PciLibAddress + OFFSET_OF (PCI_TYPE01, Bridge.IoLimit));
if ((IoLimit & PCI_BRIDGE_32_BIT_IO_SPACE ) == 0) { if ((IoLimit & PCI_BRIDGE_32_BIT_IO_SPACE ) == 0) {
IoLimit = IoLimit >> 4; IoLimit = IoLimit >> 4;
} else { } else {
IoLimit = (PciRead16 (PciLibAddress + OFFSET_OF (PCI_BRIDGE_CONTROL_REGISTER, IoLimitUpper16)) << 4) | (IoLimit >> 4); IoLimit = (PciRead16 (PciLibAddress + OFFSET_OF (PCI_TYPE01, Bridge.IoLimitUpper16)) << 4) | (IoLimit >> 4);
} }
IoBase = PciRead8 (PciLibAddress + OFFSET_OF (PCI_BRIDGE_CONTROL_REGISTER, IoBase)); IoBase = PciRead8 (PciLibAddress + OFFSET_OF (PCI_TYPE01, Bridge.IoBase));
if ((IoBase & PCI_BRIDGE_32_BIT_IO_SPACE ) == 0) { if ((IoBase & PCI_BRIDGE_32_BIT_IO_SPACE ) == 0) {
IoBase = IoBase >> 4; IoBase = IoBase >> 4;
} else { } else {
IoBase = (PciRead16 (PciLibAddress + OFFSET_OF (PCI_BRIDGE_CONTROL_REGISTER, IoBaseUpper16)) << 4) | (IoBase >> 4); IoBase = (PciRead16 (PciLibAddress + OFFSET_OF (PCI_TYPE01, Bridge.IoBaseUpper16)) << 4) | (IoBase >> 4);
} }
// //