mirror of https://github.com/acidanthera/audk.git
ArmPkg/CompilerIntrinsicsLib: provide atomics intrinsics
Gary reports the GCC 10 will emit calls to atomics intrinsics routines unless -mno-outline-atomics is specified. This means GCC-10 introduces new intrinsics, and even though it would be possible to work around this by specifying the command line option, this would require a new GCC10 toolchain profile to be created, which we prefer to avoid. So instead, add the new intrinsics to our library so they are provided when necessary. Signed-off-by: Ard Biesheuvel <ard.biesheuvel@arm.com> Tested-by: Gary Lin <glin@suse.com> Acked-by: Laszlo Ersek <lersek@redhat.com> Reviewed-by: Leif Lindholm <leif@nuviainc.com> Reviewed-by: Philippe Mathieu-Daude <philmd@redhat.com>
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Ard Biesheuvel
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#------------------------------------------------------------------------------
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#
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# Copyright (c) 2020, Arm, Limited. All rights reserved.<BR>
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#
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# SPDX-License-Identifier: BSD-2-Clause-Patent
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#
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#------------------------------------------------------------------------------
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/*
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* Provide the GCC intrinsics that are required when using GCC 9 or
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* later with the -moutline-atomics options (which became the default
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* in GCC 10)
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*/
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.arch armv8-a
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.macro reg_alias, pfx, sz
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r0_\sz .req \pfx\()0
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r1_\sz .req \pfx\()1
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tmp0_\sz .req \pfx\()16
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tmp1_\sz .req \pfx\()17
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.endm
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/*
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* Define register aliases of the right type for each size
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* (xN for 8 bytes, wN for everything smaller)
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*/
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reg_alias w, 1
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reg_alias w, 2
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reg_alias w, 4
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reg_alias x, 8
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.macro fn_start, name:req
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.section .text.\name
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.globl \name
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.type \name, %function
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\name\():
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.endm
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.macro fn_end, name:req
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.size \name, . - \name
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.endm
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/*
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* Emit an atomic helper for \model with operands of size \sz, using
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* the operation specified by \insn (which is the LSE name), and which
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* can be implemented using the generic load-locked/store-conditional
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* (LL/SC) sequence below, using the arithmetic operation given by
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* \opc.
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*/
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.macro emit_ld_sz, sz:req, insn:req, opc:req, model:req, s, a, l
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fn_start __aarch64_\insn\()\sz\()\model
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mov tmp0_\sz, r0_\sz
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0: ld\a\()xr\s r0_\sz, [x1]
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.ifnc \insn, swp
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\opc tmp1_\sz, r0_\sz, tmp0_\sz
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st\l\()xr\s w15, tmp1_\sz, [x1]
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.else
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st\l\()xr\s w15, tmp0_\sz, [x1]
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.endif
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cbnz w15, 0b
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ret
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fn_end __aarch64_\insn\()\sz\()\model
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.endm
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/*
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* Emit atomic helpers for \model for operand sizes in the
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* set {1, 2, 4, 8}, for the instruction pattern given by
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* \insn. (This is the LSE name, but this implementation uses
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* the generic LL/SC sequence using \opc as the arithmetic
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* operation on the target.)
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*/
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.macro emit_ld, insn:req, opc:req, model:req, a, l
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emit_ld_sz 1, \insn, \opc, \model, b, \a, \l
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emit_ld_sz 2, \insn, \opc, \model, h, \a, \l
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emit_ld_sz 4, \insn, \opc, \model, , \a, \l
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emit_ld_sz 8, \insn, \opc, \model, , \a, \l
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.endm
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/*
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* Emit the compare and swap helper for \model and size \sz
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* using LL/SC instructions.
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*/
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.macro emit_cas_sz, sz:req, model:req, uxt:req, s, a, l
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fn_start __aarch64_cas\sz\()\model
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\uxt tmp0_\sz, r0_\sz
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0: ld\a\()xr\s r0_\sz, [x2]
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cmp r0_\sz, tmp0_\sz
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bne 1f
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st\l\()xr\s w15, r1_\sz, [x2]
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cbnz w15, 0b
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1: ret
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fn_end __aarch64_cas\sz\()\model
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.endm
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/*
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* Emit compare-and-swap helpers for \model for operand sizes in the
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* set {1, 2, 4, 8, 16}.
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*/
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.macro emit_cas, model:req, a, l
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emit_cas_sz 1, \model, uxtb, b, \a, \l
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emit_cas_sz 2, \model, uxth, h, \a, \l
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emit_cas_sz 4, \model, mov , , \a, \l
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emit_cas_sz 8, \model, mov , , \a, \l
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/*
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* We cannot use the parameterized sequence for 16 byte CAS, so we
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* need to define it explicitly.
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*/
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fn_start __aarch64_cas16\model
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mov x16, x0
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mov x17, x1
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0: ld\a\()xp x0, x1, [x4]
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cmp x0, x16
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ccmp x1, x17, #0, eq
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bne 1f
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st\l\()xp w15, x16, x17, [x4]
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cbnz w15, 0b
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1: ret
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fn_end __aarch64_cas16\model
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.endm
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/*
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* Emit the set of GCC outline atomic helper functions for
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* the memory ordering model given by \model:
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* - relax unordered loads and stores
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* - acq load-acquire, unordered store
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* - rel unordered load, store-release
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* - acq_rel load-acquire, store-release
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*/
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.macro emit_model, model:req, a, l
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emit_ld ldadd, add, \model, \a, \l
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emit_ld ldclr, bic, \model, \a, \l
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emit_ld ldeor, eor, \model, \a, \l
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emit_ld ldset, orr, \model, \a, \l
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emit_ld swp, mov, \model, \a, \l
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emit_cas \model, \a, \l
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.endm
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emit_model _relax
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emit_model _acq, a
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emit_model _rel,, l
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emit_model _acq_rel, a, l
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@ -79,6 +79,9 @@
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Arm/ldivmod.asm | MSFT
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Arm/llsr.asm | MSFT
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[Sources.AARCH64]
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AArch64/Atomics.S | GCC
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[Packages]
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MdePkg/MdePkg.dec
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ArmPkg/ArmPkg.dec
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