mirror of https://github.com/acidanthera/audk.git
Update PcAtChipsetPkg PciRootBridgeIo to consume IoLib&PciLib.
git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@10591 6f19259b-4bc3-4df7-8a09-765794883524
This commit is contained in:
rsun3
parent
46f0e2a9ee
commit
cac2ab9556
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@ -39,6 +39,8 @@
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MemoryAllocationLib|MdePkg/Library/UefiMemoryAllocationLib/UefiMemoryAllocationLib.inf
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UefiBootServicesTableLib|MdePkg/Library/UefiBootServicesTableLib/UefiBootServicesTableLib.inf
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DxeServicesTableLib|MdePkg/Library/DxeServicesTableLib/DxeServicesTableLib.inf
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PciLib|MdePkg/Library/BasePciLibCf8/BasePciLibCf8.inf
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PciCf8Lib|MdePkg/Library/BasePciCf8Lib/BasePciCf8Lib.inf
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[Components]
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PcAtChipsetPkg/8254TimerDxe/8254Timer.inf
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@ -47,4 +49,4 @@
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PcAtChipsetPkg/KbcResetDxe/Reset.inf
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PcAtChipsetPkg/Library/SerialIoLib/SerialIoLib.inf
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PcAtChipsetPkg/PcatRealTimeClockRuntimeDxe/PcatRealTimeClockRuntimeDxe.inf
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PcAtChipsetPkg/PciHostBridgeDxe/PciHostBridgeDxe.inf
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PcAtChipsetPkg/PciHostBridgeDxe/PciHostBridgeDxe.inf
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@ -51,7 +51,7 @@ EFI_PCI_ROOT_BRIDGE_DEVICE_PATH mEfiPciRootBridgeDevicePath[1][1] = {
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};
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PCI_ROOT_BRIDGE_RESOURCE_APPETURE mResAppeture[1][1] = {
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{0, 0, 0, 0xffffffff, 0, 1 << 16}
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{0, 0xff, 0x80000000, 0xffffffff, 0, 0xffff}
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};
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EFI_HANDLE mDriverImageHandle;
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@ -1,7 +1,7 @@
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/** @file
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The Header file of the Pci Host Bridge Driver
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Copyright (c) 2008 - 2009, Intel Corporation. All rights reserved.<BR>
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Copyright (c) 2008 - 2010, Intel Corporation. All rights reserved.<BR>
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This program and the accompanying materials are
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licensed and made available under the terms and conditions of the BSD License
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which accompanies this distribution. The full text of the license may be found at
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@ -22,7 +22,6 @@
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#include <Protocol/PciHostBridgeResourceAllocation.h>
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#include <Protocol/PciRootBridgeIo.h>
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#include <Protocol/CpuIo2.h>
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#include <Protocol/Metronome.h>
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#include <Protocol/DevicePath.h>
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@ -35,6 +34,8 @@
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#include <Library/UefiBootServicesTableLib.h>
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#include <Library/DxeServicesTableLib.h>
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#include <Library/DevicePathLib.h>
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#include <Library/IoLib.h>
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#include <Library/PciLib.h>
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//
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// Hard code the host bridge number in the platform.
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@ -42,6 +43,16 @@
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//
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#define HOST_BRIDGE_NUMBER 1
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#define MAX_PCI_DEVICE_NUMBER 31
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#define MAX_PCI_FUNCTION_NUMBER 7
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#define MAX_PCI_REG_ADDRESS 0xFF
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typedef enum {
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IoOperation,
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MemOperation,
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PciOperation
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} OPERATION_TYPE;
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#define PCI_HOST_BRIDGE_SIGNATURE SIGNATURE_32('e', 'h', 's', 't')
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typedef struct {
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UINTN Signature;
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@ -219,7 +230,6 @@ typedef struct {
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UINT64 MemLimit;
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UINT64 IoLimit;
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EFI_LOCK PciLock;
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UINTN PciAddress;
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UINTN PciData;
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@ -35,7 +35,9 @@
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BaseLib
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DebugLib
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DevicePathLib
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IoLib
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PciLib
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[Sources]
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PciHostBridge.c
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PciRootBridgeIo.c
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@ -44,9 +46,9 @@
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[Protocols]
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gEfiPciHostBridgeResourceAllocationProtocolGuid
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gEfiPciRootBridgeIoProtocolGuid
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gEfiCpuIo2ProtocolGuid
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gEfiMetronomeArchProtocolGuid
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gEfiDevicePathProtocolGuid
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[depex]
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gEfiCpuIo2ProtocolGuid AND gEfiMetronomeArchProtocolGuid
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gEfiMetronomeArchProtocolGuid
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@ -572,42 +572,46 @@ RootBridgeIoConfiguration (
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OUT VOID **Resources
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);
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//
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// Sub Function Prototypes
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//
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/**
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Internal help function for read and write PCI configuration space.
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@param[in] This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
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@param[in] Write Switch value for Read or Write.
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@param[in] Width Signifies the width of the memory operations.
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@param[in] UserAddress The address within the PCI configuration space for the PCI controller.
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@param[in] Count The number of PCI configuration operations to perform. Bytes
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moved is Width size * Count, starting at Address.
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@param[out] UserBuffer For read operations, the destination buffer to store the results. For
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write operations, the source buffer to write data from.
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@retval EFI_SUCCESS The data was read from or written to the PCI root bridge.
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@retval EFI_INVALID_PARAMETER Width is invalid for this PCI root bridge.
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@retval EFI_INVALID_PARAMETER Buffer is NULL.
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@retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.
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**/
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EFI_STATUS
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RootBridgeIoPciRW (
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IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,
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IN BOOLEAN Write,
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IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width,
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IN UINT64 UserAddress,
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IN UINTN Count,
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IN OUT VOID *UserBuffer
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);
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//
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// Memory Controller Pci Root Bridge Io Module Variables
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//
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EFI_METRONOME_ARCH_PROTOCOL *mMetronome;
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EFI_CPU_IO2_PROTOCOL *mCpuIo;
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//
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// Lookup table for increment values based on transfer widths
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//
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UINT8 mInStride[] = {
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1, // EfiPciWidthUint8
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2, // EfiPciWidthUint16
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4, // EfiPciWidthUint32
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8, // EfiPciWidthUint64
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0, // EfiPciWidthFifoUint8
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0, // EfiPciWidthFifoUint16
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0, // EfiPciWidthFifoUint32
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0, // EfiPciWidthFifoUint64
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1, // EfiPciWidthFillUint8
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2, // EfiPciWidthFillUint16
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4, // EfiPciWidthFillUint32
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8 // EfiPciWidthFillUint64
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};
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//
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// Lookup table for increment values based on transfer widths
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//
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UINT8 mOutStride[] = {
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1, // EfiPciWidthUint8
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2, // EfiPciWidthUint16
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4, // EfiPciWidthUint32
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8, // EfiPciWidthUint64
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1, // EfiPciWidthFifoUint8
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2, // EfiPciWidthFifoUint16
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4, // EfiPciWidthFifoUint32
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8, // EfiPciWidthFifoUint64
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0, // EfiPciWidthFillUint8
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0, // EfiPciWidthFillUint16
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0, // EfiPciWidthFillUint32
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0 // EfiPciWidthFillUint64
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};
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/**
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@ -665,8 +669,6 @@ RootBridgeConstructor (
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PrivateData->ResAllocNode[Index].Status = ResNone;
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}
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EfiInitializeLock (&PrivateData->PciLock, TPL_HIGH_LEVEL);
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PrivateData->PciAddress = 0xCF8;
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PrivateData->PciData = 0xCFC;
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@ -706,15 +708,391 @@ RootBridgeConstructor (
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Protocol->SegmentNumber = 0;
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Status = gBS->LocateProtocol (&gEfiCpuIo2ProtocolGuid, NULL, (VOID **)&mCpuIo);
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ASSERT_EFI_ERROR (Status);
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Status = gBS->LocateProtocol (&gEfiMetronomeArchProtocolGuid, NULL, (VOID **)&mMetronome);
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ASSERT_EFI_ERROR (Status);
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return EFI_SUCCESS;
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}
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/**
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Check parameters for IO,MMIO,PCI read/write services of PCI Root Bridge IO.
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The I/O operations are carried out exactly as requested. The caller is responsible
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for satisfying any alignment and I/O width restrictions that a PI System on a
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platform might require. For example on some platforms, width requests of
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EfiCpuIoWidthUint64 do not work. Misaligned buffers, on the other hand, will
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be handled by the driver.
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@param[in] This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
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@param[in] OperationType I/O operation type: IO/MMIO/PCI.
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@param[in] Width Signifies the width of the I/O or Memory operation.
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@param[in] Address The base address of the I/O operation.
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@param[in] Count The number of I/O operations to perform. The number of
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bytes moved is Width size * Count, starting at Address.
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@param[in] Buffer For read operations, the destination buffer to store the results.
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For write operations, the source buffer from which to write data.
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@retval EFI_SUCCESS The parameters for this request pass the checks.
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@retval EFI_INVALID_PARAMETER Width is invalid for this PI system.
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@retval EFI_INVALID_PARAMETER Buffer is NULL.
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@retval EFI_UNSUPPORTED The Buffer is not aligned for the given Width.
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@retval EFI_UNSUPPORTED The address range specified by Address, Width,
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and Count is not valid for this PI system.
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**/
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EFI_STATUS
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RootBridgeIoCheckParameter (
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IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,
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IN OPERATION_TYPE OperationType,
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IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width,
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IN UINT64 Address,
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IN UINTN Count,
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IN VOID *Buffer
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)
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{
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PCI_ROOT_BRIDGE_INSTANCE *PrivateData;
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EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_PCI_ADDRESS *PciRbAddr;
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UINT64 MaxCount;
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UINT64 Base;
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UINT64 Limit;
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//
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// Check to see if Buffer is NULL
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//
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if (Buffer == NULL) {
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return EFI_INVALID_PARAMETER;
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}
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//
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// Check to see if Width is in the valid range
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//
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if (Width < EfiPciWidthUint8 || Width >= EfiPciWidthMaximum) {
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return EFI_INVALID_PARAMETER;
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}
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//
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// For FIFO type, the target address won't increase during the access,
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// so treat Count as 1
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//
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if (Width >= EfiPciWidthFifoUint8 && Width <= EfiPciWidthFifoUint64) {
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Count = 1;
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}
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//
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// Check to see if Width is in the valid range for I/O Port operations
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//
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Width = (EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH) (Width & 0x03);
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if ((OperationType != MemOperation) && (Width == EfiPciWidthUint64)) {
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ASSERT (FALSE);
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return EFI_INVALID_PARAMETER;
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}
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//
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// Check to see if Address is aligned
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//
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if ((Address & (UINT64)(mInStride[Width] - 1)) != 0) {
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return EFI_UNSUPPORTED;
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}
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PrivateData = DRIVER_INSTANCE_FROM_PCI_ROOT_BRIDGE_IO_THIS (This);
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//
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// Check to see if any address associated with this transfer exceeds the maximum
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// allowed address. The maximum address implied by the parameters passed in is
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// Address + Size * Count. If the following condition is met, then the transfer
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// is not supported.
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//
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// Address + Size * Count > Limit + 1
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//
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// Since Limit can be the maximum integer value supported by the CPU and Count
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// can also be the maximum integer value supported by the CPU, this range
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// check must be adjusted to avoid all oveflow conditions.
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//
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// The following form of the range check is equivalent but assumes that
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// Limit is of the form (2^n - 1).
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//
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if (OperationType == IoOperation) {
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Base = PrivateData->IoBase;
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Limit = PrivateData->IoLimit;
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} else if (OperationType == MemOperation) {
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Base = PrivateData->MemBase;
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Limit = PrivateData->MemLimit;
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} else {
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PciRbAddr = (EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_PCI_ADDRESS*) &Address;
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if (PciRbAddr->Bus < PrivateData->BusBase || PciRbAddr->Bus > PrivateData->BusLimit) {
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return EFI_INVALID_PARAMETER;
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}
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if (PciRbAddr->Device > MAX_PCI_DEVICE_NUMBER || PciRbAddr->Function > MAX_PCI_FUNCTION_NUMBER) {
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return EFI_INVALID_PARAMETER;
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}
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if (PciRbAddr->ExtendedRegister != 0) {
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Address = PciRbAddr->ExtendedRegister;
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} else {
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Address = PciRbAddr->Register;
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}
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Base = 0;
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Limit = MAX_PCI_REG_ADDRESS;
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}
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if (Address < Base) {
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return EFI_INVALID_PARAMETER;
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}
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if (Count == 0) {
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if (Address > Limit) {
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return EFI_UNSUPPORTED;
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}
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} else {
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MaxCount = RShiftU64 (Limit, Width);
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if (MaxCount < (Count - 1)) {
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return EFI_UNSUPPORTED;
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}
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if (Address > LShiftU64 (MaxCount - Count + 1, Width)) {
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return EFI_UNSUPPORTED;
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}
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}
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return EFI_SUCCESS;
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}
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/**
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Internal help function for read and write memory space.
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@param[in] This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
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@param[in] Write Switch value for Read or Write.
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@param[in] Width Signifies the width of the memory operations.
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@param[in] UserAddress The address within the PCI configuration space for the PCI controller.
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@param[in] Count The number of PCI configuration operations to perform. Bytes
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moved is Width size * Count, starting at Address.
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@param[out] UserBuffer For read operations, the destination buffer to store the results. For
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write operations, the source buffer to write data from.
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@retval EFI_SUCCESS The data was read from or written to the PCI root bridge.
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@retval EFI_INVALID_PARAMETER Width is invalid for this PCI root bridge.
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@retval EFI_INVALID_PARAMETER Buffer is NULL.
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@retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.
|
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**/
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EFI_STATUS
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RootBridgeIoMemRW (
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IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,
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IN BOOLEAN Write,
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IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width,
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IN UINT64 Address,
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IN UINTN Count,
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IN OUT VOID *Buffer
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)
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{
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EFI_STATUS Status;
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UINT8 InStride;
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UINT8 OutStride;
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EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH OperationWidth;
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UINT8 *Uint8Buffer;
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Status = RootBridgeIoCheckParameter (This, MemOperation, Width, Address, Count, Buffer);
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if (EFI_ERROR (Status)) {
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return Status;
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}
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InStride = mInStride[Width];
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OutStride = mOutStride[Width];
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OperationWidth = (EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH) (Width & 0x03);
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for (Uint8Buffer = Buffer; Count > 0; Address += InStride, Uint8Buffer += OutStride, Count--) {
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if (Write) {
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switch (OperationWidth) {
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case EfiPciWidthUint8:
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MmioWrite8 ((UINTN)Address, *Uint8Buffer);
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break;
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case EfiPciWidthUint16:
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MmioWrite16 ((UINTN)Address, *((UINT16 *)Uint8Buffer));
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break;
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case EfiPciWidthUint32:
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MmioWrite32 ((UINTN)Address, *((UINT32 *)Uint8Buffer));
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break;
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case EfiPciWidthUint64:
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MmioWrite64 ((UINTN)Address, *((UINT64 *)Uint8Buffer));
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break;
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}
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} else {
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switch (OperationWidth) {
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case EfiPciWidthUint8:
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*Uint8Buffer = MmioRead8 ((UINTN)Address);
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break;
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case EfiPciWidthUint16:
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*((UINT16 *)Uint8Buffer) = MmioRead16 ((UINTN)Address);
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break;
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case EfiPciWidthUint32:
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*((UINT32 *)Uint8Buffer) = MmioRead32 ((UINTN)Address);
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break;
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case EfiPciWidthUint64:
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*((UINT64 *)Uint8Buffer) = MmioRead64 ((UINTN)Address);
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break;
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}
|
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}
|
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}
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return EFI_SUCCESS;
|
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}
|
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|
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/**
|
||||
Internal help function for read and write IO space.
|
||||
|
||||
@param[in] This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
|
||||
@param[in] Write Switch value for Read or Write.
|
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@param[in] Width Signifies the width of the memory operations.
|
||||
@param[in] UserAddress The address within the PCI configuration space for the PCI controller.
|
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@param[in] Count The number of PCI configuration operations to perform. Bytes
|
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moved is Width size * Count, starting at Address.
|
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@param[out] UserBuffer For read operations, the destination buffer to store the results. For
|
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write operations, the source buffer to write data from.
|
||||
|
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@retval EFI_SUCCESS The data was read from or written to the PCI root bridge.
|
||||
@retval EFI_INVALID_PARAMETER Width is invalid for this PCI root bridge.
|
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@retval EFI_INVALID_PARAMETER Buffer is NULL.
|
||||
@retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.
|
||||
|
||||
**/
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EFI_STATUS
|
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RootBridgeIoIoRW (
|
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IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,
|
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IN BOOLEAN Write,
|
||||
IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width,
|
||||
IN UINT64 Address,
|
||||
IN UINTN Count,
|
||||
IN OUT VOID *Buffer
|
||||
)
|
||||
{
|
||||
EFI_STATUS Status;
|
||||
UINT8 InStride;
|
||||
UINT8 OutStride;
|
||||
EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH OperationWidth;
|
||||
UINT8 *Uint8Buffer;
|
||||
|
||||
Status = RootBridgeIoCheckParameter (This, IoOperation, Width, Address, Count, Buffer);
|
||||
if (EFI_ERROR (Status)) {
|
||||
return Status;
|
||||
}
|
||||
|
||||
InStride = mInStride[Width];
|
||||
OutStride = mOutStride[Width];
|
||||
OperationWidth = (EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH) (Width & 0x03);
|
||||
for (Uint8Buffer = Buffer; Count > 0; Address += InStride, Uint8Buffer += OutStride, Count--) {
|
||||
if (Write) {
|
||||
switch (OperationWidth) {
|
||||
case EfiPciWidthUint8:
|
||||
IoWrite8 ((UINTN)Address, *Uint8Buffer);
|
||||
break;
|
||||
case EfiPciWidthUint16:
|
||||
IoWrite16 ((UINTN)Address, *((UINT16 *)Uint8Buffer));
|
||||
break;
|
||||
case EfiPciWidthUint32:
|
||||
IoWrite32 ((UINTN)Address, *((UINT32 *)Uint8Buffer));
|
||||
break;
|
||||
}
|
||||
} else {
|
||||
switch (OperationWidth) {
|
||||
case EfiPciWidthUint8:
|
||||
*Uint8Buffer = IoRead8 ((UINTN)Address);
|
||||
break;
|
||||
case EfiPciWidthUint16:
|
||||
*((UINT16 *)Uint8Buffer) = IoRead16 ((UINTN)Address);
|
||||
break;
|
||||
case EfiPciWidthUint32:
|
||||
*((UINT32 *)Uint8Buffer) = IoRead32 ((UINTN)Address);
|
||||
break;
|
||||
}
|
||||
}
|
||||
}
|
||||
return EFI_SUCCESS;
|
||||
}
|
||||
|
||||
/**
|
||||
Internal help function for read and write PCI configuration space.
|
||||
|
||||
@param[in] This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
|
||||
@param[in] Write Switch value for Read or Write.
|
||||
@param[in] Width Signifies the width of the memory operations.
|
||||
@param[in] UserAddress The address within the PCI configuration space for the PCI controller.
|
||||
@param[in] Count The number of PCI configuration operations to perform. Bytes
|
||||
moved is Width size * Count, starting at Address.
|
||||
@param[out] UserBuffer For read operations, the destination buffer to store the results. For
|
||||
write operations, the source buffer to write data from.
|
||||
|
||||
@retval EFI_SUCCESS The data was read from or written to the PCI root bridge.
|
||||
@retval EFI_INVALID_PARAMETER Width is invalid for this PCI root bridge.
|
||||
@retval EFI_INVALID_PARAMETER Buffer is NULL.
|
||||
@retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.
|
||||
|
||||
**/
|
||||
EFI_STATUS
|
||||
RootBridgeIoPciRW (
|
||||
IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,
|
||||
IN BOOLEAN Write,
|
||||
IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width,
|
||||
IN UINT64 Address,
|
||||
IN UINTN Count,
|
||||
IN OUT VOID *Buffer
|
||||
)
|
||||
{
|
||||
EFI_STATUS Status;
|
||||
UINT8 InStride;
|
||||
UINT8 OutStride;
|
||||
EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH OperationWidth;
|
||||
UINT8 *Uint8Buffer;
|
||||
EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_PCI_ADDRESS *PciRbAddr;
|
||||
UINTN PcieRegAddr;
|
||||
|
||||
Status = RootBridgeIoCheckParameter (This, PciOperation, Width, Address, Count, Buffer);
|
||||
if (EFI_ERROR (Status)) {
|
||||
return Status;
|
||||
}
|
||||
|
||||
PciRbAddr = (EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_PCI_ADDRESS*) &Address;
|
||||
|
||||
PcieRegAddr = (UINTN) PCI_LIB_ADDRESS (
|
||||
PciRbAddr->Bus,
|
||||
PciRbAddr->Device,
|
||||
PciRbAddr->Function,
|
||||
(PciRbAddr->ExtendedRegister != 0) ? \
|
||||
PciRbAddr->ExtendedRegister :
|
||||
PciRbAddr->Register
|
||||
);
|
||||
|
||||
InStride = mInStride[Width];
|
||||
OutStride = mOutStride[Width];
|
||||
OperationWidth = (EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH) (Width & 0x03);
|
||||
for (Uint8Buffer = Buffer; Count > 0; PcieRegAddr += InStride, Uint8Buffer += OutStride, Count--) {
|
||||
if (Write) {
|
||||
switch (OperationWidth) {
|
||||
case EfiPciWidthUint8:
|
||||
PciWrite8 (PcieRegAddr, *Uint8Buffer);
|
||||
break;
|
||||
case EfiPciWidthUint16:
|
||||
PciWrite16 (PcieRegAddr, *((UINT16 *)Uint8Buffer));
|
||||
break;
|
||||
case EfiPciWidthUint32:
|
||||
PciWrite32 (PcieRegAddr, *((UINT32 *)Uint8Buffer));
|
||||
break;
|
||||
}
|
||||
} else {
|
||||
switch (OperationWidth) {
|
||||
case EfiPciWidthUint8:
|
||||
*Uint8Buffer = PciRead8 (PcieRegAddr);
|
||||
break;
|
||||
case EfiPciWidthUint16:
|
||||
*((UINT16 *)Uint8Buffer) = PciRead16 (PcieRegAddr);
|
||||
break;
|
||||
case EfiPciWidthUint32:
|
||||
*((UINT32 *)Uint8Buffer) = PciRead32 (PcieRegAddr);
|
||||
break;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
return EFI_SUCCESS;
|
||||
}
|
||||
|
||||
/**
|
||||
Polls an address in memory mapped I/O space until an exit condition is met, or
|
||||
a timeout occurs.
|
||||
|
|
@ -952,42 +1330,7 @@ RootBridgeIoMemRead (
|
|||
IN OUT VOID *Buffer
|
||||
)
|
||||
{
|
||||
PCI_ROOT_BRIDGE_INSTANCE *PrivateData;
|
||||
EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH OldWidth;
|
||||
UINTN OldCount;
|
||||
|
||||
if (Buffer == NULL) {
|
||||
return EFI_INVALID_PARAMETER;
|
||||
}
|
||||
|
||||
if (Width < 0 || Width >= EfiPciWidthMaximum) {
|
||||
return EFI_INVALID_PARAMETER;
|
||||
}
|
||||
|
||||
PrivateData = DRIVER_INSTANCE_FROM_PCI_ROOT_BRIDGE_IO_THIS(This);
|
||||
|
||||
//
|
||||
// Check memory access limit
|
||||
//
|
||||
if (Address < PrivateData->MemBase) {
|
||||
return EFI_INVALID_PARAMETER;
|
||||
}
|
||||
|
||||
OldWidth = Width;
|
||||
OldCount = Count;
|
||||
|
||||
if (Width >= EfiPciWidthFifoUint8 && Width <= EfiPciWidthFifoUint64) {
|
||||
Count = 1;
|
||||
}
|
||||
|
||||
Width = (EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH)(Width & 0x03);
|
||||
|
||||
if (Address + (((UINTN)1 << Width) * Count) - 1 > PrivateData->MemLimit) {
|
||||
return EFI_INVALID_PARAMETER;
|
||||
}
|
||||
|
||||
return mCpuIo->Mem.Read (mCpuIo, (EFI_CPU_IO_PROTOCOL_WIDTH) OldWidth,
|
||||
Address, OldCount, Buffer);
|
||||
return RootBridgeIoMemRW (This, FALSE, Width, Address, Count, Buffer);
|
||||
}
|
||||
|
||||
/**
|
||||
|
|
@ -1022,41 +1365,7 @@ RootBridgeIoMemWrite (
|
|||
IN OUT VOID *Buffer
|
||||
)
|
||||
{
|
||||
PCI_ROOT_BRIDGE_INSTANCE *PrivateData;
|
||||
EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH OldWidth;
|
||||
UINTN OldCount;
|
||||
|
||||
if (Buffer == NULL) {
|
||||
return EFI_INVALID_PARAMETER;
|
||||
}
|
||||
|
||||
if (Width < 0 || Width >= EfiPciWidthMaximum) {
|
||||
return EFI_INVALID_PARAMETER;
|
||||
}
|
||||
|
||||
PrivateData = DRIVER_INSTANCE_FROM_PCI_ROOT_BRIDGE_IO_THIS(This);
|
||||
|
||||
//
|
||||
// Check memory access limit
|
||||
//
|
||||
if (Address < PrivateData->MemBase) {
|
||||
return EFI_INVALID_PARAMETER;
|
||||
}
|
||||
|
||||
OldWidth = Width;
|
||||
OldCount = Count;
|
||||
if (Width >= EfiPciWidthFifoUint8 && Width <= EfiPciWidthFifoUint64) {
|
||||
Count = 1;
|
||||
}
|
||||
|
||||
Width = (EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH)(Width & 0x03);
|
||||
|
||||
if (Address + (((UINTN)1 << Width) * Count) - 1 > PrivateData->MemLimit) {
|
||||
return EFI_INVALID_PARAMETER;
|
||||
}
|
||||
|
||||
return mCpuIo->Mem.Write (mCpuIo, (EFI_CPU_IO_PROTOCOL_WIDTH) OldWidth,
|
||||
Address, OldCount, Buffer);
|
||||
return RootBridgeIoMemRW (This, TRUE, Width, Address, Count, Buffer);
|
||||
}
|
||||
|
||||
/**
|
||||
|
|
@ -1087,52 +1396,7 @@ RootBridgeIoIoRead (
|
|||
IN OUT VOID *Buffer
|
||||
)
|
||||
{
|
||||
|
||||
|
||||
UINTN AlignMask;
|
||||
PCI_ROOT_BRIDGE_INSTANCE *PrivateData;
|
||||
EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH OldWidth;
|
||||
UINTN OldCount;
|
||||
|
||||
if (Buffer == NULL) {
|
||||
return EFI_INVALID_PARAMETER;
|
||||
}
|
||||
|
||||
if (Width < 0 || Width >= EfiPciWidthMaximum) {
|
||||
return EFI_INVALID_PARAMETER;
|
||||
}
|
||||
|
||||
PrivateData = DRIVER_INSTANCE_FROM_PCI_ROOT_BRIDGE_IO_THIS(This);
|
||||
|
||||
//AlignMask = (1 << Width) - 1;
|
||||
AlignMask = (1 << (Width & 0x03)) - 1;
|
||||
|
||||
//
|
||||
// check Io access limit
|
||||
//
|
||||
if (Address < PrivateData->IoBase) {
|
||||
return EFI_INVALID_PARAMETER;
|
||||
}
|
||||
|
||||
OldWidth = Width;
|
||||
OldCount = Count;
|
||||
if (Width >= EfiPciWidthFifoUint8 && Width <= EfiPciWidthFifoUint64) {
|
||||
Count = 1;
|
||||
}
|
||||
|
||||
Width = (EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH)(Width & 0x03);
|
||||
|
||||
if (Address + (((UINTN)1 << Width) * Count) - 1 >= PrivateData->IoLimit) {
|
||||
return EFI_INVALID_PARAMETER;
|
||||
}
|
||||
|
||||
if (Address & AlignMask) {
|
||||
return EFI_INVALID_PARAMETER;
|
||||
}
|
||||
|
||||
return mCpuIo->Io.Read (mCpuIo, (EFI_CPU_IO_PROTOCOL_WIDTH) OldWidth,
|
||||
Address, OldCount, Buffer);
|
||||
|
||||
return RootBridgeIoIoRW (This, FALSE, Width, Address, Count, Buffer);
|
||||
}
|
||||
|
||||
/**
|
||||
|
|
@ -1163,50 +1427,7 @@ RootBridgeIoIoWrite (
|
|||
IN OUT VOID *Buffer
|
||||
)
|
||||
{
|
||||
UINTN AlignMask;
|
||||
PCI_ROOT_BRIDGE_INSTANCE *PrivateData;
|
||||
EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH OldWidth;
|
||||
UINTN OldCount;
|
||||
|
||||
if (Buffer == NULL) {
|
||||
return EFI_INVALID_PARAMETER;
|
||||
}
|
||||
|
||||
if (Width < 0 || Width >= EfiPciWidthMaximum) {
|
||||
return EFI_INVALID_PARAMETER;
|
||||
}
|
||||
|
||||
PrivateData = DRIVER_INSTANCE_FROM_PCI_ROOT_BRIDGE_IO_THIS(This);
|
||||
|
||||
//AlignMask = (1 << Width) - 1;
|
||||
AlignMask = (1 << (Width & 0x03)) - 1;
|
||||
|
||||
//
|
||||
// Check Io access limit
|
||||
//
|
||||
if (Address < PrivateData->IoBase) {
|
||||
return EFI_INVALID_PARAMETER;
|
||||
}
|
||||
|
||||
OldWidth = Width;
|
||||
OldCount = Count;
|
||||
if (Width >= EfiPciWidthFifoUint8 && Width <= EfiPciWidthFifoUint64) {
|
||||
Count = 1;
|
||||
}
|
||||
|
||||
Width = (EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH)(Width & 0x03);
|
||||
|
||||
if (Address + (((UINTN)1 << Width) * Count) - 1 >= PrivateData->IoLimit) {
|
||||
return EFI_INVALID_PARAMETER;
|
||||
}
|
||||
|
||||
if (Address & AlignMask) {
|
||||
return EFI_INVALID_PARAMETER;
|
||||
}
|
||||
|
||||
return mCpuIo->Io.Write (mCpuIo, (EFI_CPU_IO_PROTOCOL_WIDTH) OldWidth,
|
||||
Address, OldCount, Buffer);
|
||||
|
||||
return RootBridgeIoIoRW (This, TRUE, Width, Address, Count, Buffer);
|
||||
}
|
||||
|
||||
/**
|
||||
|
|
@ -1331,17 +1552,6 @@ RootBridgeIoPciRead (
|
|||
IN OUT VOID *Buffer
|
||||
)
|
||||
{
|
||||
|
||||
if (Buffer == NULL) {
|
||||
return EFI_INVALID_PARAMETER;
|
||||
}
|
||||
|
||||
if (Width < 0 || Width >= EfiPciWidthMaximum) {
|
||||
return EFI_INVALID_PARAMETER;
|
||||
}
|
||||
//
|
||||
// Read Pci configuration space
|
||||
//
|
||||
return RootBridgeIoPciRW (This, FALSE, Width, Address, Count, Buffer);
|
||||
}
|
||||
|
||||
|
|
@ -1378,17 +1588,6 @@ RootBridgeIoPciWrite (
|
|||
IN OUT VOID *Buffer
|
||||
)
|
||||
{
|
||||
|
||||
if (Buffer == NULL) {
|
||||
return EFI_INVALID_PARAMETER;
|
||||
}
|
||||
|
||||
if (Width < 0 || Width >= EfiPciWidthMaximum) {
|
||||
return EFI_INVALID_PARAMETER;
|
||||
}
|
||||
//
|
||||
// Write Pci configuration space
|
||||
//
|
||||
return RootBridgeIoPciRW (This, TRUE, Width, Address, Count, Buffer);
|
||||
}
|
||||
|
||||
|
|
@ -1879,111 +2078,3 @@ RootBridgeIoConfiguration (
|
|||
return EFI_SUCCESS;
|
||||
}
|
||||
|
||||
//
|
||||
// Internal function
|
||||
//
|
||||
/**
|
||||
Internal help function for read and write PCI configuration space.
|
||||
|
||||
@param[in] This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
|
||||
@param[in] Write Switch value for Read or Write.
|
||||
@param[in] Width Signifies the width of the memory operations.
|
||||
@param[in] UserAddress The address within the PCI configuration space for the PCI controller.
|
||||
@param[in] Count The number of PCI configuration operations to perform. Bytes
|
||||
moved is Width size * Count, starting at Address.
|
||||
@param[out] UserBuffer For read operations, the destination buffer to store the results. For
|
||||
write operations, the source buffer to write data from.
|
||||
|
||||
@retval EFI_SUCCESS The data was read from or written to the PCI root bridge.
|
||||
@retval EFI_INVALID_PARAMETER Width is invalid for this PCI root bridge.
|
||||
@retval EFI_INVALID_PARAMETER Buffer is NULL.
|
||||
@retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.
|
||||
|
||||
**/
|
||||
EFI_STATUS
|
||||
RootBridgeIoPciRW (
|
||||
IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,
|
||||
IN BOOLEAN Write,
|
||||
IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width,
|
||||
IN UINT64 UserAddress,
|
||||
IN UINTN Count,
|
||||
IN OUT VOID *UserBuffer
|
||||
)
|
||||
{
|
||||
PCI_CONFIG_ACCESS_CF8 Pci;
|
||||
PCI_CONFIG_ACCESS_CF8 PciAligned;
|
||||
UINT32 InStride;
|
||||
UINT32 OutStride;
|
||||
UINTN PciData;
|
||||
UINTN PciDataStride;
|
||||
PCI_ROOT_BRIDGE_INSTANCE *PrivateData;
|
||||
EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_PCI_ADDRESS PciAddress;
|
||||
|
||||
if (Width < 0 || Width >= EfiPciWidthMaximum) {
|
||||
return EFI_INVALID_PARAMETER;
|
||||
}
|
||||
|
||||
if ((Width & 0x03) >= EfiPciWidthUint64) {
|
||||
return EFI_INVALID_PARAMETER;
|
||||
}
|
||||
|
||||
PrivateData = DRIVER_INSTANCE_FROM_PCI_ROOT_BRIDGE_IO_THIS(This);
|
||||
|
||||
InStride = 1 << (Width & 0x03);
|
||||
OutStride = InStride;
|
||||
if (Width >= EfiCpuIoWidthFifoUint8 && Width <= EfiCpuIoWidthFifoUint64) {
|
||||
InStride = 0;
|
||||
}
|
||||
|
||||
if (Width >= EfiCpuIoWidthFillUint8 && Width <= EfiCpuIoWidthFillUint64) {
|
||||
OutStride = 0;
|
||||
}
|
||||
|
||||
CopyMem (&PciAddress, &UserAddress, sizeof(UINT64));
|
||||
|
||||
if (PciAddress.ExtendedRegister > 0xFF) {
|
||||
return EFI_UNSUPPORTED;
|
||||
}
|
||||
|
||||
if (PciAddress.ExtendedRegister != 0) {
|
||||
Pci.Bits.Reg = PciAddress.ExtendedRegister & 0xFF;
|
||||
} else {
|
||||
Pci.Bits.Reg = PciAddress.Register;
|
||||
}
|
||||
|
||||
Pci.Bits.Func = PciAddress.Function;
|
||||
Pci.Bits.Dev = PciAddress.Device;
|
||||
Pci.Bits.Bus = PciAddress.Bus;
|
||||
Pci.Bits.Reserved = 0;
|
||||
Pci.Bits.Enable = 1;
|
||||
|
||||
//
|
||||
// PCI Config access are all 32-bit alligned, but by accessing the
|
||||
// CONFIG_DATA_REGISTER (0xcfc) with different widths more cycle types
|
||||
// are possible on PCI.
|
||||
//
|
||||
// To read a byte of PCI config space you load 0xcf8 and
|
||||
// read 0xcfc, 0xcfd, 0xcfe, 0xcff
|
||||
//
|
||||
PciDataStride = Pci.Bits.Reg & 0x03;
|
||||
|
||||
while (Count) {
|
||||
CopyMem (&PciAligned, &Pci, sizeof (PciAligned));
|
||||
PciAligned.Bits.Reg &= 0xfc;
|
||||
PciData = (UINTN)PrivateData->PciData + PciDataStride;
|
||||
EfiAcquireLock(&PrivateData->PciLock);
|
||||
This->Io.Write (This, EfiPciWidthUint32, PrivateData->PciAddress, 1, &PciAligned);
|
||||
if (Write) {
|
||||
This->Io.Write (This, Width, PciData, 1, UserBuffer);
|
||||
} else {
|
||||
This->Io.Read (This, Width, PciData, 1, UserBuffer);
|
||||
}
|
||||
EfiReleaseLock(&PrivateData->PciLock);
|
||||
UserBuffer = ((UINT8 *)UserBuffer) + OutStride;
|
||||
PciDataStride = (PciDataStride + InStride) % 4;
|
||||
Pci.Bits.Reg += InStride;
|
||||
Count -= 1;
|
||||
}
|
||||
|
||||
return EFI_SUCCESS;
|
||||
}
|
||||
|
|
|
|||
Loading…
Reference in New Issue