mirror of
https://github.com/acidanthera/audk.git
synced 2025-04-08 17:05:09 +02:00
Remove items moved to OMAP350 Package
git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@9855 6f19259b-4bc3-4df7-8a09-765794883524
This commit is contained in:
andrewfish
parent
a3f98646f6
commit
cb0f9ff1ae
@ -35,30 +35,3 @@
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[Guids.common]
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gBeagleBoardTokenSpaceGuid = { 0x6834fe45, 0x4aee, 0x4fc6, { 0xbc, 0xb5, 0xff, 0x45, 0xb7, 0xa8, 0x71, 0xe2 } }
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#[PcdsEnumerations.common]
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# OMAP3530_GPTIMER:
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# OMAP3530_GPTIMER1|1
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# OMAP3530_GPTIMER2|2
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# OMAP3530_GPTIMER3|3
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# OMAP3530_GPTIMER4|4
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# OMAP3530_GPTIMER5|5
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# OMAP3530_GPTIMER6|6
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# OMAP3530_GPTIMER7|7
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# OMAP3530_GPTIMER8|8
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# OMAP3530_GPTIMER9|9
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# OMAP3530_GPTIMER10|10
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# OMAP3530_GPTIMER11|11
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# OMAP3530_GPTIMER12|12
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[PcdsFeatureFlag.common]
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[PcdsFixedAtBuild.common]
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gBeagleBoardTokenSpaceGuid.PcdBeagleBoardIRAMFullSize|0x00000000|UINT32|0x00000201
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gBeagleBoardTokenSpaceGuid.PcdBeagleConsoleUart|3|UINT32|0x00000202
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gBeagleBoardTokenSpaceGuid.PcdBeagleGpmcOffset|0x00000000|UINT32|0x00000203
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gBeagleBoardTokenSpaceGuid.PcdBeagleMMCHS1Base|0x00000000|UINT32|0x00000204
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# gBeagleBoardTokenSpaceGuid.PcdBeagleArchTimer|OMAP3530_GPTIMER3|OMAP3530_GPTIMER|0x00000205
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gBeagleBoardTokenSpaceGuid.PcdBeagleArchTimer|3|UINT32|0x00000205
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# gBeagleBoardTokenSpaceGuid.PcdBeagleFreeTimer|OMAP3530_GPTIMER4|OMAP3530_GPTIMER|0x00000206
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gBeagleBoardTokenSpaceGuid.PcdBeagleFreeTimer|4|UINT32|0x00000206
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@ -74,7 +74,7 @@
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DefaultExceptioHandlerLib|ArmPkg/Library/DefaultExceptionHandlerLib/DefaultExceptionHandlerLib.inf
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PrePiLib|EmbeddedPkg/Library/PrePiLib/PrePiLib.inf
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SerialPortLib|BeagleBoardPkg/Library/SerialPortLib/SerialPortLib.inf
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SerialPortLib|Omap35xxPkg/Library/SerialPortLib/SerialPortLib.inf
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SemihostLib|ArmPkg/Library/SemihostLib/SemihostLib.inf
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RealTimeClockLib|EmbeddedPkg/Library/TemplateRealTimeClockLib/TemplateRealTimeClockLib.inf
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@ -107,11 +107,11 @@
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CpuLib|MdePkg/Library/BaseCpuLib/BaseCpuLib.inf
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TimerLib|BeagleBoardPkg/Library/BeagleBoardTimerLib/BeagleBoardTimerLib.inf
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OmapLib|BeagleBoardPkg/Library/OmapLib/OmapLib.inf
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TimerLib|Omap35xxPkg/Library/BeagleBoardTimerLib/BeagleBoardTimerLib.inf
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OmapLib|Omap35xxPkg/Library/OmapLib/OmapLib.inf
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EblNetworkLib|EmbeddedPkg/Library/EblNetworkLib/EblNetworkLib.inf
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GdbSerialLib|BeagleBoardPkg/Library/GdbSerialLib/GdbSerialLib.inf
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GdbSerialLib|Omap35xxPkg/Library/GdbSerialLib/GdbSerialLib.inf
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[LibraryClasses.common.SEC]
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@ -363,7 +363,7 @@
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#
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# USB
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#
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BeagleBoardPkg/PciEmulation/PciEmulation.inf
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Omap35xxPkg/PciEmulation/PciEmulation.inf
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#NOTE: Open source EHCI stack doesn't work on Beagleboard.
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#NOTE: UsbBus and UsbMassStorage don't work using iPhone SDK tool chain.
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@ -377,29 +377,29 @@
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#
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# Nand Flash
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#
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BeagleBoardPkg/Flash/Flash.inf
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Omap35xxPkg/Flash/Flash.inf
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#
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# MMC/SD
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#
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BeagleBoardPkg/MMCHSDxe/MMCHS.inf
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Omap35xxPkg/MMCHSDxe/MMCHS.inf
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#
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# I2C
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#
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BeagleBoardPkg/SmbusDxe/Smbus.inf
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Omap35xxPkg/SmbusDxe/Smbus.inf
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#
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# SoC Drivers
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#
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BeagleBoardPkg/Gpio/Gpio.inf
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BeagleBoardPkg/InterruptDxe/InterruptDxe.inf
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BeagleBoardPkg/TimerDxe/TimerDxe.inf
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Omap35xxPkg/Gpio/Gpio.inf
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Omap35xxPkg/InterruptDxe/InterruptDxe.inf
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Omap35xxPkg/TimerDxe/TimerDxe.inf
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#
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# Power IC
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#
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BeagleBoardPkg/TPS65950Dxe/TPS65950.inf
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Omap35xxPkg/TPS65950Dxe/TPS65950.inf
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#
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# Application
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@ -114,29 +114,29 @@ READ_LOCK_STATUS = TRUE
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#
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# Nand Flash
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#
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INF BeagleBoardPkg/Flash/Flash.inf
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INF Omap35xxPkg/Flash/Flash.inf
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#
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# MMC/SD
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#
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INF BeagleBoardPkg/MMCHSDxe/MMCHS.inf
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INF Omap35xxPkg/MMCHSDxe/MMCHS.inf
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#
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# I2C
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#
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INF BeagleBoardPkg/SmbusDxe/Smbus.inf
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INF Omap35xxPkg/SmbusDxe/Smbus.inf
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#
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# SoC Drivers
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#
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INF BeagleBoardPkg/Gpio/Gpio.inf
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INF BeagleBoardPkg/InterruptDxe/InterruptDxe.inf
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INF BeagleBoardPkg/TimerDxe/TimerDxe.inf
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INF Omap35xxPkg/Gpio/Gpio.inf
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INF Omap35xxPkg/InterruptDxe/InterruptDxe.inf
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INF Omap35xxPkg/TimerDxe/TimerDxe.inf
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#
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# Power IC
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#
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INF BeagleBoardPkg/TPS65950Dxe/TPS65950.inf
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INF Omap35xxPkg/TPS65950Dxe/TPS65950.inf
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#
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# FAT filesystem + GPT/MBR partitioning
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@ -150,7 +150,7 @@ READ_LOCK_STATUS = TRUE
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# USB Support
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#
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INF BeagleBoardPkg/PciEmulation/PciEmulation.inf
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INF Omap35xxPkg/PciEmulation/PciEmulation.inf
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#NOTE: Open source EHCI stack doesn't work on Beagleboard.
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#NOTE: UsbBus and UsbMassStorage don't work using iPhond SDK tool chain.
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@ -1,763 +0,0 @@
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/** @file
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Copyright (c) 2008-2009, Apple Inc. All rights reserved.
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All rights reserved. This program and the accompanying materials
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are licensed and made available under the terms and conditions of the BSD License
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which accompanies this distribution. The full text of the license may be found at
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http://opensource.org/licenses/bsd-license.php
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THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
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WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
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**/
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#include "Flash.h"
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NAND_PART_INFO_TABLE gNandPartInfoTable[1] = {
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{ 0x2C, 0xBA, 17, 11 }
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};
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NAND_FLASH_INFO *gNandFlashInfo = NULL;
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UINT8 *gEccCode;
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UINTN gNum512BytesChunks = 0;
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//
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// Device path for SemiHosting. It contains our autogened Caller ID GUID.
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//
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typedef struct {
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VENDOR_DEVICE_PATH Guid;
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EFI_DEVICE_PATH_PROTOCOL End;
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} FLASH_DEVICE_PATH;
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FLASH_DEVICE_PATH gDevicePath = {
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{
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{ HARDWARE_DEVICE_PATH, HW_VENDOR_DP, sizeof (VENDOR_DEVICE_PATH), 0 },
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EFI_CALLER_ID_GUID
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},
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{ END_DEVICE_PATH_TYPE, END_ENTIRE_DEVICE_PATH_SUBTYPE, sizeof (EFI_DEVICE_PATH_PROTOCOL), 0}
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};
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//Actual page address = Column address + Page address + Block address.
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UINTN
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GetActualPageAddressInBytes (
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UINTN BlockIndex,
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UINTN PageIndex
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)
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{
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//BlockAddressStart = Start of the Block address in actual NAND
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//PageAddressStart = Start of the Page address in actual NAND
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return ((BlockIndex << gNandFlashInfo->BlockAddressStart) + (PageIndex << gNandFlashInfo->PageAddressStart));
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}
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VOID
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NandSendCommand (
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UINT8 Command
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)
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{
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MmioWrite16(GPMC_NAND_COMMAND_0, Command);
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}
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VOID
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NandSendAddress (
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UINT8 Address
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)
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{
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MmioWrite16(GPMC_NAND_ADDRESS_0, Address);
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}
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UINT16
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NandReadStatus (
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VOID
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)
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{
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//Send READ STATUS command
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NandSendCommand(READ_STATUS_CMD);
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//Read status.
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return MmioRead16(GPMC_NAND_DATA_0);
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}
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VOID
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NandSendAddressCycles (
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UINTN Address
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)
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{
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//Column address
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NandSendAddress(Address & 0xff);
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Address >>= 8;
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//Column address
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NandSendAddress(Address & 0x07);
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Address >>= 3;
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//Page and Block address
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NandSendAddress(Address & 0xff);
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Address >>= 8;
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//Block address
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NandSendAddress(Address & 0xff);
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Address >>= 8;
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//Block address
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NandSendAddress(Address & 0x01);
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}
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VOID
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GpmcInit (
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VOID
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)
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{
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//Enable Smart-idle mode.
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MmioWrite32(GPMC_SYSCONFIG, SMARTIDLEMODE);
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//Set IRQSTATUS and IRQENABLE to the reset value
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MmioWrite32(GPMC_IRQSTATUS, 0x0);
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MmioWrite32(GPMC_IRQENABLE, 0x0);
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//Disable GPMC timeout control.
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MmioWrite32(GPMC_TIMEOUT_CONTROL, TIMEOUTDISABLE);
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//Set WRITEPROTECT bit to enable write access.
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MmioWrite32(GPMC_CONFIG, WRITEPROTECT_HIGH);
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//NOTE: Following GPMC_CONFIGi_0 register settings are taken from u-boot memory dump.
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MmioWrite32(GPMC_CONFIG1_0, DEVICETYPE_NAND | DEVICESIZE_X16);
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MmioWrite32(GPMC_CONFIG2_0, CSRDOFFTIME | CSWROFFTIME);
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MmioWrite32(GPMC_CONFIG3_0, ADVRDOFFTIME | ADVWROFFTIME);
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MmioWrite32(GPMC_CONFIG4_0, OEONTIME | OEOFFTIME | WEONTIME | WEOFFTIME);
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MmioWrite32(GPMC_CONFIG5_0, RDCYCLETIME | WRCYCLETIME | RDACCESSTIME | PAGEBURSTACCESSTIME);
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MmioWrite32(GPMC_CONFIG6_0, WRACCESSTIME | WRDATAONADMUXBUS | CYCLE2CYCLEDELAY | CYCLE2CYCLESAMECSEN);
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MmioWrite32(GPMC_CONFIG7_0, MASKADDRESS_128MB | CSVALID | BASEADDRESS);
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}
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EFI_STATUS
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NandDetectPart (
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VOID
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)
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{
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UINT8 NandInfo = 0;
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UINT8 PartInfo[5];
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UINTN Index;
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BOOLEAN Found = FALSE;
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//Send READ ID command
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NandSendCommand(READ_ID_CMD);
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//Send one address cycle.
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NandSendAddress(0);
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//Read 5-bytes to idenfity code programmed into the NAND flash devices.
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//BYTE 0 = Manufacture ID
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//Byte 1 = Device ID
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//Byte 2, 3, 4 = Nand part specific information (Page size, Block size etc)
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for (Index = 0; Index < sizeof(PartInfo); Index++) {
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PartInfo[Index] = MmioRead16(GPMC_NAND_DATA_0);
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}
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//Check if the ManufactureId and DeviceId are part of the currently supported nand parts.
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for (Index = 0; Index < sizeof(gNandPartInfoTable)/sizeof(NAND_PART_INFO_TABLE); Index++) {
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if (gNandPartInfoTable[Index].ManufactureId == PartInfo[0] && gNandPartInfoTable[Index].DeviceId == PartInfo[1]) {
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gNandFlashInfo->BlockAddressStart = gNandPartInfoTable[Index].BlockAddressStart;
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gNandFlashInfo->PageAddressStart = gNandPartInfoTable[Index].PageAddressStart;
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Found = TRUE;
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break;
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}
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}
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if (Found == FALSE) {
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DEBUG ((EFI_D_ERROR, "Nand part is not currently supported. Manufacture id: %x, Device id: %x\n", PartInfo[0], PartInfo[1]));
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return EFI_NOT_FOUND;
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}
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//Populate NAND_FLASH_INFO based on the result of READ ID command.
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gNandFlashInfo->ManufactureId = PartInfo[0];
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gNandFlashInfo->DeviceId = PartInfo[1];
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NandInfo = PartInfo[3];
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if (PAGE_SIZE(NandInfo) == PAGE_SIZE_2K_VAL) {
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gNandFlashInfo->PageSize = PAGE_SIZE_2K;
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} else {
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DEBUG ((EFI_D_ERROR, "Unknown Page size.\n"));
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return EFI_DEVICE_ERROR;
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}
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if (SPARE_AREA_SIZE(NandInfo) == SPARE_AREA_SIZE_64B_VAL) {
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gNandFlashInfo->SparePageSize = SPARE_AREA_SIZE_64B;
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} else {
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DEBUG ((EFI_D_ERROR, "Unknown Spare area size.\n"));
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return EFI_DEVICE_ERROR;
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}
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if (BLOCK_SIZE(NandInfo) == BLOCK_SIZE_128K_VAL) {
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gNandFlashInfo->BlockSize = BLOCK_SIZE_128K;
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} else {
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DEBUG ((EFI_D_ERROR, "Unknown Block size.\n"));
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return EFI_DEVICE_ERROR;
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}
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if (ORGANIZATION(NandInfo) == ORGANIZATION_X8) {
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gNandFlashInfo->Organization = 0;
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} else if (ORGANIZATION(NandInfo) == ORGANIZATION_X16) {
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gNandFlashInfo->Organization = 1;
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}
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//Calculate total number of blocks.
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gNandFlashInfo->NumPagesPerBlock = DivU64x32(gNandFlashInfo->BlockSize, gNandFlashInfo->PageSize);
|
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return EFI_SUCCESS;
|
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}
|
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|
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VOID
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NandConfigureEcc (
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VOID
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)
|
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{
|
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//Define ECC size 0 and size 1 to 512 bytes
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MmioWrite32(GPMC_ECC_SIZE_CONFIG, (ECCSIZE0_512BYTES | ECCSIZE1_512BYTES));
|
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}
|
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VOID
|
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NandEnableEcc (
|
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VOID
|
||||
)
|
||||
{
|
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//Clear all the ECC result registers and select ECC result register 1
|
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MmioWrite32(GPMC_ECC_CONTROL, (ECCCLEAR | ECCPOINTER_REG1));
|
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|
||||
//Enable ECC engine on CS0
|
||||
MmioWrite32(GPMC_ECC_CONFIG, (ECCENABLE | ECCCS_0 | ECC16B));
|
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}
|
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|
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VOID
|
||||
NandDisableEcc (
|
||||
VOID
|
||||
)
|
||||
{
|
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//Turn off ECC engine.
|
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MmioWrite32(GPMC_ECC_CONFIG, ECCDISABLE);
|
||||
}
|
||||
|
||||
VOID
|
||||
NandCalculateEcc (
|
||||
VOID
|
||||
)
|
||||
{
|
||||
UINTN Index;
|
||||
UINTN EccResultRegister;
|
||||
UINTN EccResult;
|
||||
|
||||
//Capture 32-bit ECC result for each 512-bytes chunk.
|
||||
//In our case PageSize is 2K so read ECC1-ECC4 result registers and
|
||||
//generate total of 12-bytes of ECC code for the particular page.
|
||||
|
||||
EccResultRegister = GPMC_ECC1_RESULT;
|
||||
|
||||
for (Index = 0; Index < gNum512BytesChunks; Index++) {
|
||||
|
||||
EccResult = MmioRead32(EccResultRegister);
|
||||
|
||||
//Calculate ECC code from 32-bit ECC result value.
|
||||
//NOTE: Following calculation is not part of TRM. We got this information
|
||||
//from Beagleboard mailing list.
|
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gEccCode[Index * 3] = EccResult & 0xFF;
|
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gEccCode[(Index * 3) + 1] = (EccResult >> 16) & 0xFF;
|
||||
gEccCode[(Index * 3) + 2] = (((EccResult >> 20) & 0xF0) | ((EccResult >> 8) & 0x0F));
|
||||
|
||||
//Point to next ECC result register.
|
||||
EccResultRegister += 4;
|
||||
}
|
||||
}
|
||||
|
||||
EFI_STATUS
|
||||
NandReadPage (
|
||||
IN UINTN BlockIndex,
|
||||
IN UINTN PageIndex,
|
||||
OUT VOID *Buffer,
|
||||
OUT UINT8 *SpareBuffer
|
||||
)
|
||||
{
|
||||
UINTN Address;
|
||||
UINTN Index;
|
||||
UINTN NumMainAreaWords = (gNandFlashInfo->PageSize/2);
|
||||
UINTN NumSpareAreaWords = (gNandFlashInfo->SparePageSize/2);
|
||||
UINT16 *MainAreaWordBuffer = Buffer;
|
||||
UINT16 *SpareAreaWordBuffer = (UINT16 *)SpareBuffer;
|
||||
UINTN Timeout = MAX_RETRY_COUNT;
|
||||
|
||||
//Generate device address in bytes to access specific block and page index
|
||||
Address = GetActualPageAddressInBytes(BlockIndex, PageIndex);
|
||||
|
||||
//Send READ command
|
||||
NandSendCommand(PAGE_READ_CMD);
|
||||
|
||||
//Send 5 Address cycles to access specific device address
|
||||
NandSendAddressCycles(Address);
|
||||
|
||||
//Send READ CONFIRM command
|
||||
NandSendCommand(PAGE_READ_CONFIRM_CMD);
|
||||
|
||||
//Poll till device is busy.
|
||||
while (Timeout) {
|
||||
if ((NandReadStatus() & NAND_READY) == NAND_READY) {
|
||||
break;
|
||||
}
|
||||
Timeout--;
|
||||
}
|
||||
|
||||
if (Timeout == 0) {
|
||||
DEBUG ((EFI_D_ERROR, "Read page timed out.\n"));
|
||||
return EFI_TIMEOUT;
|
||||
}
|
||||
|
||||
//Reissue READ command
|
||||
NandSendCommand(PAGE_READ_CMD);
|
||||
|
||||
//Enable ECC engine.
|
||||
NandEnableEcc();
|
||||
|
||||
//Read data into the buffer.
|
||||
for (Index = 0; Index < NumMainAreaWords; Index++) {
|
||||
*MainAreaWordBuffer++ = MmioRead16(GPMC_NAND_DATA_0);
|
||||
}
|
||||
|
||||
//Read spare area into the buffer.
|
||||
for (Index = 0; Index < NumSpareAreaWords; Index++) {
|
||||
*SpareAreaWordBuffer++ = MmioRead16(GPMC_NAND_DATA_0);
|
||||
}
|
||||
|
||||
//Calculate ECC.
|
||||
NandCalculateEcc();
|
||||
|
||||
//Turn off ECC engine.
|
||||
NandDisableEcc();
|
||||
|
||||
//Perform ECC correction.
|
||||
//Need to implement..
|
||||
|
||||
return EFI_SUCCESS;
|
||||
}
|
||||
|
||||
EFI_STATUS
|
||||
NandWritePage (
|
||||
IN UINTN BlockIndex,
|
||||
IN UINTN PageIndex,
|
||||
OUT VOID *Buffer,
|
||||
IN UINT8 *SpareBuffer
|
||||
)
|
||||
{
|
||||
UINTN Address;
|
||||
UINT16 *MainAreaWordBuffer = Buffer;
|
||||
UINT16 *SpareAreaWordBuffer = (UINT16 *)SpareBuffer;
|
||||
UINTN Index;
|
||||
UINTN NandStatus;
|
||||
UINTN Timeout = MAX_RETRY_COUNT;
|
||||
|
||||
//Generate device address in bytes to access specific block and page index
|
||||
Address = GetActualPageAddressInBytes(BlockIndex, PageIndex);
|
||||
|
||||
//Send SERIAL DATA INPUT command
|
||||
NandSendCommand(PROGRAM_PAGE_CMD);
|
||||
|
||||
//Send 5 Address cycles to access specific device address
|
||||
NandSendAddressCycles(Address);
|
||||
|
||||
//Enable ECC engine.
|
||||
NandEnableEcc();
|
||||
|
||||
//Data input from Buffer
|
||||
for (Index = 0; Index < (gNandFlashInfo->PageSize/2); Index++) {
|
||||
MmioWrite16(GPMC_NAND_DATA_0, *MainAreaWordBuffer++);
|
||||
|
||||
//After each write access, device has to wait to accept data.
|
||||
//Currently we may not be programming proper timing parameters to
|
||||
//the GPMC_CONFIGi_0 registers and we would need to figure that out.
|
||||
//Without following delay, page programming fails.
|
||||
gBS->Stall(1);
|
||||
}
|
||||
|
||||
//Calculate ECC.
|
||||
NandCalculateEcc();
|
||||
|
||||
//Turn off ECC engine.
|
||||
NandDisableEcc();
|
||||
|
||||
//Prepare Spare area buffer with ECC codes.
|
||||
SetMem(SpareBuffer, gNandFlashInfo->SparePageSize, 0xFF);
|
||||
CopyMem(&SpareBuffer[ECC_POSITION], gEccCode, gNum512BytesChunks * 3);
|
||||
|
||||
//Program spare area with calculated ECC.
|
||||
for (Index = 0; Index < (gNandFlashInfo->SparePageSize/2); Index++) {
|
||||
MmioWrite16(GPMC_NAND_DATA_0, *SpareAreaWordBuffer++);
|
||||
}
|
||||
|
||||
//Send PROGRAM command
|
||||
NandSendCommand(PROGRAM_PAGE_CONFIRM_CMD);
|
||||
|
||||
//Poll till device is busy.
|
||||
while (Timeout) {
|
||||
NandStatus = NandReadStatus();
|
||||
if ((NandStatus & NAND_READY) == NAND_READY) {
|
||||
break;
|
||||
}
|
||||
Timeout--;
|
||||
}
|
||||
|
||||
if (Timeout == 0) {
|
||||
DEBUG ((EFI_D_ERROR, "Program page timed out.\n"));
|
||||
return EFI_TIMEOUT;
|
||||
}
|
||||
|
||||
//Bit0 indicates Pass/Fail status
|
||||
if (NandStatus & NAND_FAILURE) {
|
||||
return EFI_DEVICE_ERROR;
|
||||
}
|
||||
|
||||
return EFI_SUCCESS;
|
||||
}
|
||||
|
||||
EFI_STATUS
|
||||
NandEraseBlock (
|
||||
IN UINTN BlockIndex
|
||||
)
|
||||
{
|
||||
UINTN Address;
|
||||
UINTN NandStatus;
|
||||
UINTN Timeout = MAX_RETRY_COUNT;
|
||||
|
||||
//Generate device address in bytes to access specific block and page index
|
||||
Address = GetActualPageAddressInBytes(BlockIndex, 0);
|
||||
|
||||
//Send ERASE SETUP command
|
||||
NandSendCommand(BLOCK_ERASE_CMD);
|
||||
|
||||
//Send 3 address cycles to device to access Page address and Block address
|
||||
Address >>= 11; //Ignore column addresses
|
||||
|
||||
NandSendAddress(Address & 0xff);
|
||||
Address >>= 8;
|
||||
|
||||
NandSendAddress(Address & 0xff);
|
||||
Address >>= 8;
|
||||
|
||||
NandSendAddress(Address & 0xff);
|
||||
|
||||
//Send ERASE CONFIRM command
|
||||
NandSendCommand(BLOCK_ERASE_CONFIRM_CMD);
|
||||
|
||||
//Poll till device is busy.
|
||||
while (Timeout) {
|
||||
NandStatus = NandReadStatus();
|
||||
if ((NandStatus & NAND_READY) == NAND_READY) {
|
||||
break;
|
||||
}
|
||||
Timeout--;
|
||||
gBS->Stall(1);
|
||||
}
|
||||
|
||||
if (Timeout == 0) {
|
||||
DEBUG ((EFI_D_ERROR, "Erase block timed out for Block: %d.\n", BlockIndex));
|
||||
return EFI_TIMEOUT;
|
||||
}
|
||||
|
||||
//Bit0 indicates Pass/Fail status
|
||||
if (NandStatus & NAND_FAILURE) {
|
||||
return EFI_DEVICE_ERROR;
|
||||
}
|
||||
|
||||
return EFI_SUCCESS;
|
||||
}
|
||||
|
||||
EFI_STATUS
|
||||
NandReadBlock (
|
||||
IN UINTN StartBlockIndex,
|
||||
IN UINTN EndBlockIndex,
|
||||
OUT VOID *Buffer,
|
||||
OUT VOID *SpareBuffer
|
||||
)
|
||||
{
|
||||
UINTN BlockIndex;
|
||||
UINTN PageIndex;
|
||||
EFI_STATUS Status = EFI_SUCCESS;
|
||||
|
||||
for (BlockIndex = StartBlockIndex; BlockIndex <= EndBlockIndex; BlockIndex++) {
|
||||
//For each block read number of pages
|
||||
for (PageIndex = 0; PageIndex < gNandFlashInfo->NumPagesPerBlock; PageIndex++) {
|
||||
Status = NandReadPage(BlockIndex, PageIndex, Buffer, SpareBuffer);
|
||||
if (EFI_ERROR(Status)) {
|
||||
return Status;
|
||||
}
|
||||
Buffer = ((UINT8 *)Buffer + gNandFlashInfo->PageSize);
|
||||
}
|
||||
}
|
||||
|
||||
return Status;
|
||||
}
|
||||
|
||||
EFI_STATUS
|
||||
NandWriteBlock (
|
||||
IN UINTN StartBlockIndex,
|
||||
IN UINTN EndBlockIndex,
|
||||
OUT VOID *Buffer,
|
||||
OUT VOID *SpareBuffer
|
||||
)
|
||||
{
|
||||
UINTN BlockIndex;
|
||||
UINTN PageIndex;
|
||||
EFI_STATUS Status = EFI_SUCCESS;
|
||||
|
||||
for (BlockIndex = StartBlockIndex; BlockIndex <= EndBlockIndex; BlockIndex++) {
|
||||
//Page programming.
|
||||
for (PageIndex = 0; PageIndex < gNandFlashInfo->NumPagesPerBlock; PageIndex++) {
|
||||
Status = NandWritePage(BlockIndex, PageIndex, Buffer, SpareBuffer);
|
||||
if (EFI_ERROR(Status)) {
|
||||
return Status;
|
||||
}
|
||||
Buffer = ((UINT8 *)Buffer + gNandFlashInfo->PageSize);
|
||||
}
|
||||
}
|
||||
|
||||
return Status;
|
||||
}
|
||||
|
||||
EFI_STATUS
|
||||
EFIAPI
|
||||
NandFlashReset (
|
||||
IN EFI_BLOCK_IO_PROTOCOL *This,
|
||||
IN BOOLEAN ExtendedVerification
|
||||
)
|
||||
{
|
||||
UINTN BusyStall = 50; // microSeconds
|
||||
UINTN ResetBusyTimeout = (1000000 / BusyStall); // 1 Second
|
||||
|
||||
//Send RESET command to device.
|
||||
NandSendCommand(RESET_CMD);
|
||||
|
||||
//Wait for 1ms before we check status register.
|
||||
gBS->Stall(1000);
|
||||
|
||||
//Check BIT#5 & BIT#6 in Status register to make sure RESET is done.
|
||||
while ((NandReadStatus() & NAND_RESET_STATUS) != NAND_RESET_STATUS) {
|
||||
|
||||
//In case of extended verification, wait for extended amount of time
|
||||
//to make sure device is reset.
|
||||
if (ExtendedVerification) {
|
||||
if (ResetBusyTimeout == 0) {
|
||||
return EFI_DEVICE_ERROR;
|
||||
}
|
||||
|
||||
gBS->Stall(BusyStall);
|
||||
ResetBusyTimeout--;
|
||||
}
|
||||
}
|
||||
|
||||
return EFI_SUCCESS;
|
||||
}
|
||||
|
||||
EFI_STATUS
|
||||
EFIAPI
|
||||
NandFlashReadBlocks (
|
||||
IN EFI_BLOCK_IO_PROTOCOL *This,
|
||||
IN UINT32 MediaId,
|
||||
IN EFI_LBA Lba,
|
||||
IN UINTN BufferSize,
|
||||
OUT VOID *Buffer
|
||||
)
|
||||
{
|
||||
UINTN NumBlocks;
|
||||
UINTN EndBlockIndex;
|
||||
EFI_STATUS Status;
|
||||
UINT8 *SpareBuffer = NULL;
|
||||
|
||||
if (Buffer == NULL) {
|
||||
Status = EFI_INVALID_PARAMETER;
|
||||
goto exit;
|
||||
}
|
||||
|
||||
if (Lba > LAST_BLOCK) {
|
||||
Status = EFI_INVALID_PARAMETER;
|
||||
goto exit;
|
||||
}
|
||||
|
||||
if ((BufferSize % gNandFlashInfo->BlockSize) != 0) {
|
||||
Status = EFI_BAD_BUFFER_SIZE;
|
||||
goto exit;
|
||||
}
|
||||
|
||||
NumBlocks = DivU64x32(BufferSize, gNandFlashInfo->BlockSize);
|
||||
EndBlockIndex = ((UINTN)Lba + NumBlocks) - 1;
|
||||
|
||||
SpareBuffer = (UINT8 *)AllocatePool(gNandFlashInfo->SparePageSize);
|
||||
if (SpareBuffer == NULL) {
|
||||
Status = EFI_OUT_OF_RESOURCES;
|
||||
goto exit;
|
||||
}
|
||||
|
||||
//Read block
|
||||
Status = NandReadBlock((UINTN)Lba, EndBlockIndex, Buffer, SpareBuffer);
|
||||
if (EFI_ERROR(Status)) {
|
||||
DEBUG((EFI_D_ERROR, "Read block fails: %x\n", Status));
|
||||
goto exit;
|
||||
}
|
||||
|
||||
exit:
|
||||
if (SpareBuffer != NULL) {
|
||||
FreePool (SpareBuffer);
|
||||
}
|
||||
|
||||
return Status;
|
||||
}
|
||||
|
||||
EFI_STATUS
|
||||
EFIAPI
|
||||
NandFlashWriteBlocks (
|
||||
IN EFI_BLOCK_IO_PROTOCOL *This,
|
||||
IN UINT32 MediaId,
|
||||
IN EFI_LBA Lba,
|
||||
IN UINTN BufferSize,
|
||||
IN VOID *Buffer
|
||||
)
|
||||
{
|
||||
UINTN BlockIndex;
|
||||
UINTN NumBlocks;
|
||||
UINTN EndBlockIndex;
|
||||
EFI_STATUS Status;
|
||||
UINT8 *SpareBuffer = NULL;
|
||||
|
||||
if (Buffer == NULL) {
|
||||
Status = EFI_INVALID_PARAMETER;
|
||||
goto exit;
|
||||
}
|
||||
|
||||
if (Lba > LAST_BLOCK) {
|
||||
Status = EFI_INVALID_PARAMETER;
|
||||
goto exit;
|
||||
}
|
||||
|
||||
if ((BufferSize % gNandFlashInfo->BlockSize) != 0) {
|
||||
Status = EFI_BAD_BUFFER_SIZE;
|
||||
goto exit;
|
||||
}
|
||||
|
||||
NumBlocks = DivU64x32(BufferSize, gNandFlashInfo->BlockSize);
|
||||
EndBlockIndex = ((UINTN)Lba + NumBlocks) - 1;
|
||||
|
||||
SpareBuffer = (UINT8 *)AllocatePool(gNandFlashInfo->SparePageSize);
|
||||
if (SpareBuffer == NULL) {
|
||||
Status = EFI_OUT_OF_RESOURCES;
|
||||
goto exit;
|
||||
}
|
||||
|
||||
// Erase block
|
||||
for (BlockIndex = (UINTN)Lba; BlockIndex <= EndBlockIndex; BlockIndex++) {
|
||||
Status = NandEraseBlock(BlockIndex);
|
||||
if (EFI_ERROR(Status)) {
|
||||
DEBUG((EFI_D_ERROR, "Erase block failed. Status: %x\n", Status));
|
||||
goto exit;
|
||||
}
|
||||
}
|
||||
|
||||
// Program data
|
||||
Status = NandWriteBlock((UINTN)Lba, EndBlockIndex, Buffer, SpareBuffer);
|
||||
if (EFI_ERROR(Status)) {
|
||||
DEBUG((EFI_D_ERROR, "Block write fails: %x\n", Status));
|
||||
goto exit;
|
||||
}
|
||||
|
||||
exit:
|
||||
if (SpareBuffer != NULL) {
|
||||
FreePool (SpareBuffer);
|
||||
}
|
||||
|
||||
return Status;
|
||||
}
|
||||
|
||||
EFI_STATUS
|
||||
EFIAPI
|
||||
NandFlashFlushBlocks (
|
||||
IN EFI_BLOCK_IO_PROTOCOL *This
|
||||
)
|
||||
{
|
||||
return EFI_SUCCESS;
|
||||
}
|
||||
|
||||
|
||||
|
||||
EFI_BLOCK_IO_MEDIA gNandFlashMedia = {
|
||||
SIGNATURE_32('n','a','n','d'), // MediaId
|
||||
FALSE, // RemovableMedia
|
||||
TRUE, // MediaPresent
|
||||
FALSE, // LogicalPartition
|
||||
FALSE, // ReadOnly
|
||||
FALSE, // WriteCaching
|
||||
0, // BlockSize
|
||||
2, // IoAlign
|
||||
0, // Pad
|
||||
0 // LastBlock
|
||||
};
|
||||
|
||||
EFI_BLOCK_IO_PROTOCOL BlockIo =
|
||||
{
|
||||
EFI_BLOCK_IO_INTERFACE_REVISION, // Revision
|
||||
&gNandFlashMedia, // *Media
|
||||
NandFlashReset, // Reset
|
||||
NandFlashReadBlocks, // ReadBlocks
|
||||
NandFlashWriteBlocks, // WriteBlocks
|
||||
NandFlashFlushBlocks // FlushBlocks
|
||||
};
|
||||
|
||||
EFI_STATUS
|
||||
NandFlashInitialize (
|
||||
IN EFI_HANDLE ImageHandle,
|
||||
IN EFI_SYSTEM_TABLE *SystemTable
|
||||
)
|
||||
{
|
||||
EFI_STATUS Status;
|
||||
|
||||
gNandFlashInfo = (NAND_FLASH_INFO *)AllocateZeroPool (sizeof(NAND_FLASH_INFO));
|
||||
|
||||
//Initialize GPMC module.
|
||||
GpmcInit();
|
||||
|
||||
//Reset NAND part
|
||||
NandFlashReset(&BlockIo, FALSE);
|
||||
|
||||
//Detect NAND part and populate gNandFlashInfo structure
|
||||
Status = NandDetectPart ();
|
||||
if (EFI_ERROR(Status)) {
|
||||
DEBUG((EFI_D_ERROR, "Nand part id detection failure: Status: %x\n", Status));
|
||||
return Status;
|
||||
}
|
||||
|
||||
//Count total number of 512Bytes chunk based on the page size.
|
||||
if (gNandFlashInfo->PageSize == PAGE_SIZE_512B) {
|
||||
gNum512BytesChunks = 1;
|
||||
} else if (gNandFlashInfo->PageSize == PAGE_SIZE_2K) {
|
||||
gNum512BytesChunks = 4;
|
||||
} else if (gNandFlashInfo->PageSize == PAGE_SIZE_4K) {
|
||||
gNum512BytesChunks = 8;
|
||||
}
|
||||
|
||||
gEccCode = (UINT8 *)AllocatePool(gNum512BytesChunks * 3);
|
||||
if (gEccCode == NULL) {
|
||||
return EFI_OUT_OF_RESOURCES;
|
||||
}
|
||||
|
||||
//Configure ECC
|
||||
NandConfigureEcc ();
|
||||
|
||||
//Patch EFI_BLOCK_IO_MEDIA structure.
|
||||
gNandFlashMedia.BlockSize = gNandFlashInfo->BlockSize;
|
||||
gNandFlashMedia.LastBlock = LAST_BLOCK;
|
||||
|
||||
//Publish BlockIO.
|
||||
Status = gBS->InstallMultipleProtocolInterfaces (
|
||||
&ImageHandle,
|
||||
&gEfiBlockIoProtocolGuid, &BlockIo,
|
||||
&gEfiDevicePathProtocolGuid, &gDevicePath,
|
||||
NULL
|
||||
);
|
||||
return Status;
|
||||
}
|
||||
|
||||
@ -1,106 +0,0 @@
|
||||
/** @file
|
||||
|
||||
Copyright (c) 2008-2009 Apple Inc. All rights reserved.<BR>
|
||||
|
||||
All rights reserved. This program and the accompanying materials
|
||||
are licensed and made available under the terms and conditions of the BSD License
|
||||
which accompanies this distribution. The full text of the license may be found at
|
||||
http://opensource.org/licenses/bsd-license.php
|
||||
|
||||
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
|
||||
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
|
||||
|
||||
**/
|
||||
|
||||
#ifndef FLASH_H
|
||||
#define FLASH_H
|
||||
|
||||
#include <Uefi.h>
|
||||
|
||||
#include <Library/BaseLib.h>
|
||||
#include <Library/BaseMemoryLib.h>
|
||||
#include <Library/MemoryAllocationLib.h>
|
||||
#include <Library/DebugLib.h>
|
||||
#include <Library/IoLib.h>
|
||||
#include <Library/PcdLib.h>
|
||||
#include <Library/UefiBootServicesTableLib.h>
|
||||
#include <Library/IoLib.h>
|
||||
|
||||
#include <Protocol/BlockIo.h>
|
||||
#include <Protocol/Cpu.h>
|
||||
#include <Omap3530/Omap3530.h>
|
||||
|
||||
#define PAGE_SIZE(x) ((x) & 0x01)
|
||||
#define PAGE_SIZE_2K_VAL (0x01UL)
|
||||
|
||||
#define SPARE_AREA_SIZE(x) (((x) >> 2) & 0x01)
|
||||
#define SPARE_AREA_SIZE_64B_VAL (0x1UL)
|
||||
|
||||
#define BLOCK_SIZE(x) (((x) >> 4) & 0x01)
|
||||
#define BLOCK_SIZE_128K_VAL (0x01UL)
|
||||
|
||||
#define ORGANIZATION(x) (((x) >> 6) & 0x01)
|
||||
#define ORGANIZATION_X8 (0x0UL)
|
||||
#define ORGANIZATION_X16 (0x1UL)
|
||||
|
||||
#define PAGE_SIZE_512B (512)
|
||||
#define PAGE_SIZE_2K (2048)
|
||||
#define PAGE_SIZE_4K (4096)
|
||||
#define SPARE_AREA_SIZE_16B (16)
|
||||
#define SPARE_AREA_SIZE_64B (64)
|
||||
|
||||
#define BLOCK_SIZE_16K (16*1024)
|
||||
#define BLOCK_SIZE_128K (128*1024)
|
||||
|
||||
#define BLOCK_COUNT (2048)
|
||||
#define LAST_BLOCK (BLOCK_COUNT - 1)
|
||||
|
||||
#define ECC_POSITION 2
|
||||
|
||||
//List of commands.
|
||||
#define RESET_CMD 0xFF
|
||||
#define READ_ID_CMD 0x90
|
||||
|
||||
#define READ_STATUS_CMD 0x70
|
||||
|
||||
#define PAGE_READ_CMD 0x00
|
||||
#define PAGE_READ_CONFIRM_CMD 0x30
|
||||
|
||||
#define BLOCK_ERASE_CMD 0x60
|
||||
#define BLOCK_ERASE_CONFIRM_CMD 0xD0
|
||||
|
||||
#define PROGRAM_PAGE_CMD 0x80
|
||||
#define PROGRAM_PAGE_CONFIRM_CMD 0x10
|
||||
|
||||
//Nand status register bit definition
|
||||
#define NAND_SUCCESS (0x0UL << 0)
|
||||
#define NAND_FAILURE (0x1UL << 0)
|
||||
|
||||
#define NAND_BUSY (0x0UL << 6)
|
||||
#define NAND_READY (0x1UL << 6)
|
||||
|
||||
#define NAND_RESET_STATUS (0x60UL << 0)
|
||||
|
||||
#define MAX_RETRY_COUNT 1500
|
||||
|
||||
|
||||
typedef struct {
|
||||
UINT8 ManufactureId;
|
||||
UINT8 DeviceId;
|
||||
UINT8 BlockAddressStart; //Start of the Block address in actual NAND
|
||||
UINT8 PageAddressStart; //Start of the Page address in actual NAND
|
||||
} NAND_PART_INFO_TABLE;
|
||||
|
||||
typedef struct {
|
||||
UINT8 ManufactureId;
|
||||
UINT8 DeviceId;
|
||||
UINT8 Organization; //x8 or x16
|
||||
UINT32 PageSize;
|
||||
UINT32 SparePageSize;
|
||||
UINT32 BlockSize;
|
||||
UINT32 NumPagesPerBlock;
|
||||
UINT8 BlockAddressStart; //Start of the Block address in actual NAND
|
||||
UINT8 PageAddressStart; //Start of the Page address in actual NAND
|
||||
} NAND_FLASH_INFO;
|
||||
|
||||
#endif //FLASH_H
|
||||
@ -1,48 +0,0 @@
|
||||
#/** @file
|
||||
#
|
||||
# Copyright (c) 2008 - 2010, Apple Inc. All rights reserved.
|
||||
# All rights reserved. This program and the accompanying materials
|
||||
# are licensed and made available under the terms and conditions of the BSD License
|
||||
# which accompanies this distribution. The full text of the license may be found at
|
||||
# http://opensource.org/licenses/bsd-license.php
|
||||
#
|
||||
# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
|
||||
# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
|
||||
#
|
||||
#**/
|
||||
|
||||
[Defines]
|
||||
INF_VERSION = 0x00010005
|
||||
BASE_NAME = NandFlash
|
||||
FILE_GUID = 4d00ef14-c4e0-426b-81b7-30a00a14aad6
|
||||
MODULE_TYPE = DXE_DRIVER
|
||||
VERSION_STRING = 1.0
|
||||
|
||||
ENTRY_POINT = NandFlashInitialize
|
||||
|
||||
|
||||
[Sources.common]
|
||||
Flash.c
|
||||
|
||||
[Packages]
|
||||
MdePkg/MdePkg.dec
|
||||
BeagleBoardPkg/BeagleBoardPkg.dec
|
||||
|
||||
[LibraryClasses]
|
||||
PcdLib
|
||||
UefiLib
|
||||
UefiDriverEntryPoint
|
||||
MemoryAllocationLib
|
||||
IoLib
|
||||
|
||||
[Guids]
|
||||
|
||||
[Protocols]
|
||||
gEfiBlockIoProtocolGuid
|
||||
gEfiCpuArchProtocolGuid
|
||||
|
||||
[Pcd]
|
||||
gBeagleBoardTokenSpaceGuid.PcdBeagleGpmcOffset
|
||||
|
||||
[depex]
|
||||
TRUE
|
||||
@ -1,135 +0,0 @@
|
||||
/** @file
|
||||
|
||||
Copyright (c) 2008-2009, Apple Inc. All rights reserved.
|
||||
|
||||
All rights reserved. This program and the accompanying materials
|
||||
are licensed and made available under the terms and conditions of the BSD License
|
||||
which accompanies this distribution. The full text of the license may be found at
|
||||
http://opensource.org/licenses/bsd-license.php
|
||||
|
||||
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
|
||||
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
|
||||
|
||||
**/
|
||||
|
||||
#include <Uefi.h>
|
||||
|
||||
#include <Library/IoLib.h>
|
||||
#include <Library/OmapLib.h>
|
||||
#include <Library/UefiBootServicesTableLib.h>
|
||||
|
||||
#include <Protocol/EmbeddedGpio.h>
|
||||
|
||||
#include <Omap3530/Omap3530.h>
|
||||
|
||||
EFI_STATUS
|
||||
Get (
|
||||
IN EMBEDDED_GPIO *This,
|
||||
IN EMBEDDED_GPIO_PIN Gpio,
|
||||
OUT UINTN *Value
|
||||
)
|
||||
{
|
||||
UINTN Port;
|
||||
UINTN Pin;
|
||||
UINT32 DataInRegister;
|
||||
|
||||
if (Value == NULL)
|
||||
{
|
||||
return EFI_UNSUPPORTED;
|
||||
}
|
||||
|
||||
Port = GPIO_PORT(Gpio);
|
||||
Pin = GPIO_PIN(Gpio);
|
||||
|
||||
DataInRegister = GpioBase(Port) + GPIO_DATAIN;
|
||||
|
||||
if (MmioRead32(DataInRegister) & GPIO_DATAIN_MASK(Pin)) {
|
||||
*Value = 1;
|
||||
} else {
|
||||
*Value = 0;
|
||||
}
|
||||
|
||||
return EFI_SUCCESS;
|
||||
}
|
||||
|
||||
EFI_STATUS
|
||||
Set (
|
||||
IN EMBEDDED_GPIO *This,
|
||||
IN EMBEDDED_GPIO_PIN Gpio,
|
||||
IN EMBEDDED_GPIO_MODE Mode
|
||||
)
|
||||
{
|
||||
UINTN Port;
|
||||
UINTN Pin;
|
||||
UINT32 OutputEnableRegister;
|
||||
UINT32 SetDataOutRegister;
|
||||
UINT32 ClearDataOutRegister;
|
||||
|
||||
Port = GPIO_PORT(Gpio);
|
||||
Pin = GPIO_PIN(Gpio);
|
||||
|
||||
OutputEnableRegister = GpioBase(Port) + GPIO_OE;
|
||||
SetDataOutRegister = GpioBase(Port) + GPIO_SETDATAOUT;
|
||||
ClearDataOutRegister = GpioBase(Port) + GPIO_CLEARDATAOUT;
|
||||
|
||||
switch (Mode)
|
||||
{
|
||||
case GPIO_MODE_INPUT:
|
||||
MmioAndThenOr32(OutputEnableRegister, ~GPIO_OE_MASK(Pin), GPIO_OE_INPUT(Pin));
|
||||
break;
|
||||
|
||||
case GPIO_MODE_OUTPUT_0:
|
||||
MmioWrite32(ClearDataOutRegister, GPIO_CLEARDATAOUT_BIT(Pin));
|
||||
MmioAndThenOr32(OutputEnableRegister, ~GPIO_OE_MASK(Pin), GPIO_OE_OUTPUT(Pin));
|
||||
break;
|
||||
|
||||
case GPIO_MODE_OUTPUT_1:
|
||||
MmioWrite32(SetDataOutRegister, GPIO_SETDATAOUT_BIT(Pin));
|
||||
MmioAndThenOr32(OutputEnableRegister, ~GPIO_OE_MASK(Pin), GPIO_OE_OUTPUT(Pin));
|
||||
break;
|
||||
|
||||
default:
|
||||
return EFI_UNSUPPORTED;
|
||||
}
|
||||
|
||||
return EFI_SUCCESS;
|
||||
}
|
||||
|
||||
EFI_STATUS
|
||||
GetMode (
|
||||
IN EMBEDDED_GPIO *This,
|
||||
IN EMBEDDED_GPIO_PIN Gpio,
|
||||
OUT EMBEDDED_GPIO_MODE *Mode
|
||||
)
|
||||
{
|
||||
return EFI_UNSUPPORTED;
|
||||
}
|
||||
|
||||
EFI_STATUS
|
||||
SetPull (
|
||||
IN EMBEDDED_GPIO *This,
|
||||
IN EMBEDDED_GPIO_PIN Gpio,
|
||||
IN EMBEDDED_GPIO_PULL Direction
|
||||
)
|
||||
{
|
||||
return EFI_UNSUPPORTED;
|
||||
}
|
||||
|
||||
EMBEDDED_GPIO Gpio = {
|
||||
Get,
|
||||
Set,
|
||||
GetMode,
|
||||
SetPull
|
||||
};
|
||||
|
||||
EFI_STATUS
|
||||
GpioInitialize (
|
||||
IN EFI_HANDLE ImageHandle,
|
||||
IN EFI_SYSTEM_TABLE *SystemTable
|
||||
)
|
||||
{
|
||||
EFI_STATUS Status;
|
||||
|
||||
Status = gBS->InstallMultipleProtocolInterfaces(&ImageHandle, &gEmbeddedGpioProtocolGuid, &Gpio, NULL);
|
||||
return Status;
|
||||
}
|
||||
@ -1,45 +0,0 @@
|
||||
#/** @file
|
||||
#
|
||||
# Copyright (c) 2008 - 2010, Apple Inc. All rights reserved.
|
||||
# All rights reserved. This program and the accompanying materials
|
||||
# are licensed and made available under the terms and conditions of the BSD License
|
||||
# which accompanies this distribution. The full text of the license may be found at
|
||||
# http://opensource.org/licenses/bsd-license.php
|
||||
#
|
||||
# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
|
||||
# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
|
||||
#
|
||||
#**/
|
||||
|
||||
[Defines]
|
||||
INF_VERSION = 0x00010005
|
||||
BASE_NAME = Gpio
|
||||
FILE_GUID = E7D9CAE1-6930-46E3-BDF9-0027446E7DF2
|
||||
MODULE_TYPE = DXE_DRIVER
|
||||
VERSION_STRING = 1.0
|
||||
|
||||
ENTRY_POINT = GpioInitialize
|
||||
|
||||
|
||||
[Sources.common]
|
||||
Gpio.c
|
||||
|
||||
[Packages]
|
||||
MdePkg/MdePkg.dec
|
||||
EmbeddedPkg/EmbeddedPkg.dec
|
||||
BeagleBoardPkg/BeagleBoardPkg.dec
|
||||
|
||||
[LibraryClasses]
|
||||
IoLib
|
||||
UefiDriverEntryPoint
|
||||
OmapLib
|
||||
|
||||
[Guids]
|
||||
|
||||
[Protocols]
|
||||
gEmbeddedGpioProtocolGuid
|
||||
|
||||
[Pcd]
|
||||
|
||||
[depex]
|
||||
TRUE
|
||||
@ -1,36 +0,0 @@
|
||||
/** @file
|
||||
|
||||
Copyright (c) 2008-2009 Apple Inc. All rights reserved.<BR>
|
||||
|
||||
All rights reserved. This program and the accompanying materials
|
||||
are licensed and made available under the terms and conditions of the BSD License
|
||||
which accompanies this distribution. The full text of the license may be found at
|
||||
http://opensource.org/licenses/bsd-license.php
|
||||
|
||||
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
|
||||
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
|
||||
|
||||
**/
|
||||
|
||||
#ifndef __BEAGLEBOARD_YSTEMLIB_H__
|
||||
#define __BEAGLEBOARD_YSTEMLIB_H__
|
||||
|
||||
VOID
|
||||
EFIAPI
|
||||
GoLittleEndian (
|
||||
UINTN ImageAddress
|
||||
);
|
||||
|
||||
VOID
|
||||
EFIAPI
|
||||
ResetSystem (
|
||||
IN EFI_RESET_TYPE ResetType
|
||||
);
|
||||
|
||||
VOID
|
||||
EFIAPI
|
||||
ShutdownEfi (
|
||||
VOID
|
||||
);
|
||||
|
||||
#endif // __BEAGLEBOARD_YSTEMLIB_H__
|
||||
@ -1,39 +0,0 @@
|
||||
/** @file
|
||||
|
||||
Copyright (c) 2008-2009 Apple Inc. All rights reserved.<BR>
|
||||
|
||||
All rights reserved. This program and the accompanying materials
|
||||
are licensed and made available under the terms and conditions of the BSD License
|
||||
which accompanies this distribution. The full text of the license may be found at
|
||||
http://opensource.org/licenses/bsd-license.php
|
||||
|
||||
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
|
||||
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
|
||||
|
||||
**/
|
||||
|
||||
#ifndef __OMAPLIB_H__
|
||||
#define __OMAPLIB_H__
|
||||
|
||||
UINT32
|
||||
GpioBase (
|
||||
IN UINTN Port
|
||||
);
|
||||
|
||||
UINT32
|
||||
TimerBase (
|
||||
IN UINTN Timer
|
||||
);
|
||||
|
||||
UINTN
|
||||
InterruptVectorForTimer (
|
||||
IN UINTN TImer
|
||||
);
|
||||
|
||||
UINT32
|
||||
UartBase (
|
||||
IN UINTN Uart
|
||||
);
|
||||
|
||||
#endif // __OMAPLIB_H__
|
||||
|
||||
@ -1,38 +0,0 @@
|
||||
/** @file
|
||||
|
||||
Copyright (c) 2008-2009 Apple Inc. All rights reserved.<BR>
|
||||
|
||||
All rights reserved. This program and the accompanying materials
|
||||
are licensed and made available under the terms and conditions of the BSD License
|
||||
which accompanies this distribution. The full text of the license may be found at
|
||||
http://opensource.org/licenses/bsd-license.php
|
||||
|
||||
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
|
||||
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
|
||||
|
||||
**/
|
||||
|
||||
#ifndef __OMAP3530_H__
|
||||
#define __OMAP3530_H__
|
||||
|
||||
#include "Omap3530Gpio.h"
|
||||
#include "Omap3530Interrupt.h"
|
||||
#include "Omap3530Prcm.h"
|
||||
#include "Omap3530Timer.h"
|
||||
#include "Omap3530Uart.h"
|
||||
#include "Omap3530Usb.h"
|
||||
#include "Omap3530MMCHS.h"
|
||||
#include "Omap3530I2c.h"
|
||||
#include "Omap3530PadConfiguration.h"
|
||||
#include "Omap3530Gpmc.h"
|
||||
|
||||
//CONTROL_PBIAS_LITE
|
||||
#define CONTROL_PBIAS_LITE 0x48002520
|
||||
#define PBIASLITEVMODE0 (0x1UL << 0)
|
||||
#define PBIASLITEPWRDNZ0 (0x1UL << 1)
|
||||
#define PBIASSPEEDCTRL0 (0x1UL << 2)
|
||||
#define PBIASLITEVMODE1 (0x1UL << 8)
|
||||
#define PBIASLITEWRDNZ1 (0x1UL << 9)
|
||||
|
||||
#endif // __OMAP3530_H__
|
||||
|
||||
@ -1,131 +0,0 @@
|
||||
/** @file
|
||||
|
||||
Copyright (c) 2008-2009 Apple Inc. All rights reserved.<BR>
|
||||
|
||||
All rights reserved. This program and the accompanying materials
|
||||
are licensed and made available under the terms and conditions of the BSD License
|
||||
which accompanies this distribution. The full text of the license may be found at
|
||||
http://opensource.org/licenses/bsd-license.php
|
||||
|
||||
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
|
||||
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
|
||||
|
||||
**/
|
||||
|
||||
#ifndef __OMAP3530GPIO_H__
|
||||
#define __OMAP3530GPIO_H__
|
||||
|
||||
#define GPIO1_BASE (0x48310000)
|
||||
#define GPIO2_BASE (0x49050000)
|
||||
#define GPIO3_BASE (0x49052000)
|
||||
#define GPIO4_BASE (0x49054000)
|
||||
#define GPIO5_BASE (0x49056000)
|
||||
#define GPIO6_BASE (0x49058000)
|
||||
|
||||
#define GPIO_SYSCONFIG (0x0010)
|
||||
#define GPIO_SYSSTATUS (0x0014)
|
||||
#define GPIO_IRQSTATUS1 (0x0018)
|
||||
#define GPIO_IRQENABLE1 (0x001C)
|
||||
#define GPIO_WAKEUPENABLE (0x0020)
|
||||
#define GPIO_IRQSTATUS2 (0x0028)
|
||||
#define GPIO_IRQENABLE2 (0x002C)
|
||||
#define GPIO_CTRL (0x0030)
|
||||
#define GPIO_OE (0x0034)
|
||||
#define GPIO_DATAIN (0x0038)
|
||||
#define GPIO_DATAOUT (0x003C)
|
||||
#define GPIO_LEVELDETECT0 (0x0040)
|
||||
#define GPIO_LEVELDETECT1 (0x0044)
|
||||
#define GPIO_RISINGDETECT (0x0048)
|
||||
#define GPIO_FALLINGDETECT (0x004C)
|
||||
#define GPIO_DEBOUNCENABLE (0x0050)
|
||||
#define GPIO_DEBOUNCINGTIME (0x0054)
|
||||
#define GPIO_CLEARIRQENABLE1 (0x0060)
|
||||
#define GPIO_SETIRQENABLE1 (0x0064)
|
||||
#define GPIO_CLEARIRQENABLE2 (0x0070)
|
||||
#define GPIO_SETIRQENABLE2 (0x0074)
|
||||
#define GPIO_CLEARWKUENA (0x0080)
|
||||
#define GPIO_SETWKUENA (0x0084)
|
||||
#define GPIO_CLEARDATAOUT (0x0090)
|
||||
#define GPIO_SETDATAOUT (0x0094)
|
||||
|
||||
#define GPIO_SYSCONFIG_IDLEMODE_MASK (3UL << 3)
|
||||
#define GPIO_SYSCONFIG_IDLEMODE_FORCE (0UL << 3)
|
||||
#define GPIO_SYSCONFIG_IDLEMODE_NONE (1UL << 3)
|
||||
#define GPIO_SYSCONFIG_IDLEMODE_SMART (2UL << 3)
|
||||
#define GPIO_SYSCONFIG_ENAWAKEUP_MASK (1UL << 2)
|
||||
#define GPIO_SYSCONFIG_ENAWAKEUP_DISABLE (0UL << 2)
|
||||
#define GPIO_SYSCONFIG_ENAWAKEUP_ENABLE (1UL << 2)
|
||||
#define GPIO_SYSCONFIG_SOFTRESET_MASK (1UL << 1)
|
||||
#define GPIO_SYSCONFIG_SOFTRESET_NORMAL (0UL << 1)
|
||||
#define GPIO_SYSCONFIG_SOFTRESET_RESET (1UL << 1)
|
||||
#define GPIO_SYSCONFIG_AUTOIDLE_MASK (1UL << 0)
|
||||
#define GPIO_SYSCONFIG_AUTOIDLE_FREE_RUN (0UL << 0)
|
||||
#define GPIO_SYSCONFIG_AUTOIDLE_ON (1UL << 0)
|
||||
|
||||
#define GPIO_SYSSTATUS_RESETDONE_MASK (1UL << 0)
|
||||
#define GPIO_SYSSTATUS_RESETDONE_ONGOING (0UL << 0)
|
||||
#define GPIO_SYSSTATUS_RESETDONE_COMPLETE (1UL << 0)
|
||||
|
||||
#define GPIO_IRQSTATUS_MASK(x) (1UL << (x))
|
||||
#define GPIO_IRQSTATUS_NOT_TRIGGERED(x) (0UL << (x))
|
||||
#define GPIO_IRQSTATUS_TRIGGERED(x) (1UL << (x))
|
||||
#define GPIO_IRQSTATUS_CLEAR(x) (1UL << (x))
|
||||
|
||||
#define GPIO_IRQENABLE_MASK(x) (1UL << (x))
|
||||
#define GPIO_IRQENABLE_DISABLE(x) (0UL << (x))
|
||||
#define GPIO_IRQENABLE_ENABLE(x) (1UL << (x))
|
||||
|
||||
#define GPIO_WAKEUPENABLE_MASK(x) (1UL << (x))
|
||||
#define GPIO_WAKEUPENABLE_DISABLE(x) (0UL << (x))
|
||||
#define GPIO_WAKEUPENABLE_ENABLE(x) (1UL << (x))
|
||||
|
||||
#define GPIO_CTRL_GATINGRATIO_MASK (3UL << 1)
|
||||
#define GPIO_CTRL_GATINGRATIO_DIV_1 (0UL << 1)
|
||||
#define GPIO_CTRL_GATINGRATIO_DIV_2 (1UL << 1)
|
||||
#define GPIO_CTRL_GATINGRATIO_DIV_4 (2UL << 1)
|
||||
#define GPIO_CTRL_GATINGRATIO_DIV_8 (3UL << 1)
|
||||
#define GPIO_CTRL_DISABLEMODULE_MASK (1UL << 0)
|
||||
#define GPIO_CTRL_DISABLEMODULE_ENABLE (0UL << 0)
|
||||
#define GPIO_CTRL_DISABLEMODULE_DISABLE (1UL << 0)
|
||||
|
||||
#define GPIO_OE_MASK(x) (1UL << (x))
|
||||
#define GPIO_OE_OUTPUT(x) (0UL << (x))
|
||||
#define GPIO_OE_INPUT(x) (1UL << (x))
|
||||
|
||||
#define GPIO_DATAIN_MASK(x) (1UL << (x))
|
||||
|
||||
#define GPIO_DATAOUT_MASK(x) (1UL << (x))
|
||||
|
||||
#define GPIO_LEVELDETECT_MASK(x) (1UL << (x))
|
||||
#define GPIO_LEVELDETECT_DISABLE(x) (0UL << (x))
|
||||
#define GPIO_LEVELDETECT_ENABLE(x) (1UL << (x))
|
||||
|
||||
#define GPIO_RISINGDETECT_MASK(x) (1UL << (x))
|
||||
#define GPIO_RISINGDETECT_DISABLE(x) (0UL << (x))
|
||||
#define GPIO_RISINGDETECT_ENABLE(x) (1UL << (x))
|
||||
|
||||
#define GPIO_FALLINGDETECT_MASK(x) (1UL << (x))
|
||||
#define GPIO_FALLINGDETECT_DISABLE(x) (0UL << (x))
|
||||
#define GPIO_FALLINGDETECT_ENABLE(x) (1UL << (x))
|
||||
|
||||
#define GPIO_DEBOUNCENABLE_MASK(x) (1UL << (x))
|
||||
#define GPIO_DEBOUNCENABLE_DISABLE(x) (0UL << (x))
|
||||
#define GPIO_DEBOUNCENABLE_ENABLE(x) (1UL << (x))
|
||||
|
||||
#define GPIO_DEBOUNCINGTIME_MASK (0xFF)
|
||||
#define GPIO_DEBOUNCINGTIME_US(x) ((((x) / 31) - 1) & GPIO_DEBOUNCINGTIME_MASK)
|
||||
|
||||
#define GPIO_CLEARIRQENABLE_BIT(x) (1UL << (x))
|
||||
|
||||
#define GPIO_SETIRQENABLE_BIT(x) (1UL << (x))
|
||||
|
||||
#define GPIO_CLEARWKUENA_BIT(x) (1UL << (x))
|
||||
|
||||
#define GPIO_SETWKUENA_BIT(x) (1UL << (x))
|
||||
|
||||
#define GPIO_CLEARDATAOUT_BIT(x) (1UL << (x))
|
||||
|
||||
#define GPIO_SETDATAOUT_BIT(x) (1UL << (x))
|
||||
|
||||
#endif // __OMAP3530GPIO_H__
|
||||
|
||||
@ -1,107 +0,0 @@
|
||||
/** @file
|
||||
|
||||
Copyright (c) 2008-2009 Apple Inc. All rights reserved.<BR>
|
||||
|
||||
All rights reserved. This program and the accompanying materials
|
||||
are licensed and made available under the terms and conditions of the BSD License
|
||||
which accompanies this distribution. The full text of the license may be found at
|
||||
http://opensource.org/licenses/bsd-license.php
|
||||
|
||||
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
|
||||
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
|
||||
|
||||
**/
|
||||
|
||||
#ifndef __OMAP3530GPMC_H__
|
||||
#define __OMAP3530GPMC_H__
|
||||
|
||||
#define GPMC_BASE (0x6E000000)
|
||||
|
||||
//GPMC NAND definitions.
|
||||
#define GPMC_SYSCONFIG (GPMC_BASE + 0x10)
|
||||
#define SMARTIDLEMODE (0x2UL << 3)
|
||||
|
||||
#define GPMC_SYSSTATUS (GPMC_BASE + 0x14)
|
||||
#define GPMC_IRQSTATUS (GPMC_BASE + 0x18)
|
||||
#define GPMC_IRQENABLE (GPMC_BASE + 0x1C)
|
||||
|
||||
#define GPMC_TIMEOUT_CONTROL (GPMC_BASE + 0x40)
|
||||
#define TIMEOUTENABLE (0x1UL << 0)
|
||||
#define TIMEOUTDISABLE (0x0UL << 0)
|
||||
|
||||
#define GPMC_ERR_ADDRESS (GPMC_BASE + 0x44)
|
||||
#define GPMC_ERR_TYPE (GPMC_BASE + 0x48)
|
||||
|
||||
#define GPMC_CONFIG (GPMC_BASE + 0x50)
|
||||
#define WRITEPROTECT_HIGH (0x1UL << 4)
|
||||
#define WRITEPROTECT_LOW (0x0UL << 4)
|
||||
|
||||
#define GPMC_STATUS (GPMC_BASE + 0x54)
|
||||
|
||||
#define GPMC_CONFIG1_0 (GPMC_BASE + 0x60)
|
||||
#define DEVICETYPE_NOR (0x0UL << 10)
|
||||
#define DEVICETYPE_NAND (0x2UL << 10)
|
||||
#define DEVICESIZE_X8 (0x0UL << 12)
|
||||
#define DEVICESIZE_X16 (0x1UL << 12)
|
||||
|
||||
#define GPMC_CONFIG2_0 (GPMC_BASE + 0x64)
|
||||
#define CSONTIME (0x0UL << 0)
|
||||
#define CSRDOFFTIME (0x14UL << 8)
|
||||
#define CSWROFFTIME (0x14UL << 16)
|
||||
|
||||
#define GPMC_CONFIG3_0 (GPMC_BASE + 0x68)
|
||||
#define ADVRDOFFTIME (0x14UL << 8)
|
||||
#define ADVWROFFTIME (0x14UL << 16)
|
||||
|
||||
#define GPMC_CONFIG4_0 (GPMC_BASE + 0x6C)
|
||||
#define OEONTIME (0x1UL << 0)
|
||||
#define OEOFFTIME (0xFUL << 8)
|
||||
#define WEONTIME (0x1UL << 16)
|
||||
#define WEOFFTIME (0xFUL << 24)
|
||||
|
||||
#define GPMC_CONFIG5_0 (GPMC_BASE + 0x70)
|
||||
#define RDCYCLETIME (0x14UL << 0)
|
||||
#define WRCYCLETIME (0x14UL << 8)
|
||||
#define RDACCESSTIME (0xCUL << 16)
|
||||
#define PAGEBURSTACCESSTIME (0x1UL << 24)
|
||||
|
||||
#define GPMC_CONFIG6_0 (GPMC_BASE + 0x74)
|
||||
#define CYCLE2CYCLESAMECSEN (0x1UL << 7)
|
||||
#define CYCLE2CYCLEDELAY (0xAUL << 8)
|
||||
#define WRDATAONADMUXBUS (0xFUL << 16)
|
||||
#define WRACCESSTIME (0x1FUL << 24)
|
||||
|
||||
#define GPMC_CONFIG7_0 (GPMC_BASE + 0x78)
|
||||
#define BASEADDRESS (0x30UL << 0)
|
||||
#define CSVALID (0x1UL << 6)
|
||||
#define MASKADDRESS_128MB (0x8UL << 8)
|
||||
|
||||
#define GPMC_NAND_COMMAND_0 (GPMC_BASE + 0x7C)
|
||||
#define GPMC_NAND_ADDRESS_0 (GPMC_BASE + 0x80)
|
||||
#define GPMC_NAND_DATA_0 (GPMC_BASE + 0x84)
|
||||
|
||||
#define GPMC_ECC_CONFIG (GPMC_BASE + 0x1F4)
|
||||
#define ECCENABLE (0x1UL << 0)
|
||||
#define ECCDISABLE (0x0UL << 0)
|
||||
#define ECCCS_0 (0x0UL << 1)
|
||||
#define ECC16B (0x1UL << 7)
|
||||
|
||||
#define GPMC_ECC_CONTROL (GPMC_BASE + 0x1F8)
|
||||
#define ECCPOINTER_REG1 (0x1UL << 0)
|
||||
#define ECCCLEAR (0x1UL << 8)
|
||||
|
||||
#define GPMC_ECC_SIZE_CONFIG (GPMC_BASE + 0x1FC)
|
||||
#define ECCSIZE0_512BYTES (0xFFUL << 12)
|
||||
#define ECCSIZE1_512BYTES (0xFFUL << 22)
|
||||
|
||||
#define GPMC_ECC1_RESULT (GPMC_BASE + 0x200)
|
||||
#define GPMC_ECC2_RESULT (GPMC_BASE + 0x204)
|
||||
#define GPMC_ECC3_RESULT (GPMC_BASE + 0x208)
|
||||
#define GPMC_ECC4_RESULT (GPMC_BASE + 0x20C)
|
||||
#define GPMC_ECC5_RESULT (GPMC_BASE + 0x210)
|
||||
#define GPMC_ECC6_RESULT (GPMC_BASE + 0x214)
|
||||
#define GPMC_ECC7_RESULT (GPMC_BASE + 0x218)
|
||||
#define GPMC_ECC8_RESULT (GPMC_BASE + 0x21C)
|
||||
#define GPMC_ECC9_RESULT (GPMC_BASE + 0x220)
|
||||
|
||||
#endif //__OMAP3530GPMC_H__
|
||||
@ -1,62 +0,0 @@
|
||||
/** @file
|
||||
|
||||
Copyright (c) 2008-2009 Apple Inc. All rights reserved.<BR>
|
||||
|
||||
All rights reserved. This program and the accompanying materials
|
||||
are licensed and made available under the terms and conditions of the BSD License
|
||||
which accompanies this distribution. The full text of the license may be found at
|
||||
http://opensource.org/licenses/bsd-license.php
|
||||
|
||||
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
|
||||
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
|
||||
|
||||
**/
|
||||
|
||||
#ifndef __OMAP3530I2C_H__
|
||||
#define __OMAP3530I2C_H__
|
||||
|
||||
//I2C register definitions.
|
||||
#define I2C1BASE 0x48070000
|
||||
|
||||
#define I2C_IE (I2C1BASE + 0x4)
|
||||
#define XRDY_IE (0x1UL << 4)
|
||||
#define RRDY_IE (0x1UL << 3)
|
||||
#define ARDY_IE (0x1UL << 2)
|
||||
#define NACK_IE (0x1UL << 1)
|
||||
|
||||
#define I2C_STAT (I2C1BASE + 0x8)
|
||||
#define BB (0x1UL << 12)
|
||||
#define XRDY (0x1UL << 4)
|
||||
#define RRDY (0x1UL << 3)
|
||||
#define ARDY (0x1UL << 2)
|
||||
#define NACK (0x1UL << 1)
|
||||
|
||||
#define I2C_WE (I2C1BASE + 0xC)
|
||||
#define I2C_SYSS (I2C1BASE + 0x10)
|
||||
#define I2C_BUF (I2C1BASE + 0x14)
|
||||
#define I2C_CNT (I2C1BASE + 0x18)
|
||||
#define I2C_DATA (I2C1BASE + 0x1C)
|
||||
#define I2C_SYSC (I2C1BASE + 0x20)
|
||||
|
||||
#define I2C_CON (I2C1BASE + 0x24)
|
||||
#define STT (0x1UL << 0)
|
||||
#define STP (0x1UL << 1)
|
||||
#define XSA (0x1UL << 8)
|
||||
#define TRX (0x1UL << 9)
|
||||
#define MST (0x1UL << 10)
|
||||
#define I2C_EN (0x1UL << 15)
|
||||
|
||||
#define I2C_OA0 (I2C1BASE + 0x28)
|
||||
#define I2C_SA (I2C1BASE + 0x2C)
|
||||
#define I2C_PSC (I2C1BASE + 0x30)
|
||||
#define I2C_SCLL (I2C1BASE + 0x34)
|
||||
#define I2C_SCLH (I2C1BASE + 0x38)
|
||||
#define I2C_SYSTEST (I2C1BASE + 0x3C)
|
||||
#define I2C_BUFSTAT (I2C1BASE + 0x40)
|
||||
#define I2C_OA1 (I2C1BASE + 0x44)
|
||||
#define I2C_OA2 (I2C1BASE + 0x48)
|
||||
#define I2C_OA3 (I2C1BASE + 0x4C)
|
||||
#define I2C_ACTOA (I2C1BASE + 0x50)
|
||||
#define I2C_SBLOCK (I2C1BASE + 0x54)
|
||||
|
||||
#endif //__OMAP3530I2C_H__
|
||||
@ -1,46 +0,0 @@
|
||||
/** @file
|
||||
|
||||
Copyright (c) 2008-2009 Apple Inc. All rights reserved.<BR>
|
||||
|
||||
All rights reserved. This program and the accompanying materials
|
||||
are licensed and made available under the terms and conditions of the BSD License
|
||||
which accompanies this distribution. The full text of the license may be found at
|
||||
http://opensource.org/licenses/bsd-license.php
|
||||
|
||||
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
|
||||
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
|
||||
|
||||
**/
|
||||
|
||||
#ifndef __OMAP3530INTERRUPT_H__
|
||||
#define __OMAP3530INTERRUPT_H__
|
||||
|
||||
#define INTERRUPT_BASE (0x48200000)
|
||||
|
||||
#define INT_NROF_VECTORS (96)
|
||||
#define MAX_VECTOR (INT_NROF_VECTORS - 1)
|
||||
#define INTCPS_SYSCONFIG (INTERRUPT_BASE + 0x0010)
|
||||
#define INTCPS_SYSSTATUS (INTERRUPT_BASE + 0x0014)
|
||||
#define INTCPS_SIR_IRQ (INTERRUPT_BASE + 0x0040)
|
||||
#define INTCPS_SIR_IFQ (INTERRUPT_BASE + 0x0044)
|
||||
#define INTCPS_CONTROL (INTERRUPT_BASE + 0x0048)
|
||||
#define INTCPS_PROTECTION (INTERRUPT_BASE + 0x004C)
|
||||
#define INTCPS_IDLE (INTERRUPT_BASE + 0x0050)
|
||||
#define INTCPS_IRQ_PRIORITY (INTERRUPT_BASE + 0x0060)
|
||||
#define INTCPS_FIQ_PRIORITY (INTERRUPT_BASE + 0x0064)
|
||||
#define INTCPS_THRESHOLD (INTERRUPT_BASE + 0x0068)
|
||||
#define INTCPS_ITR(n) (INTERRUPT_BASE + 0x0080 + (0x20 * (n)))
|
||||
#define INTCPS_MIR(n) (INTERRUPT_BASE + 0x0084 + (0x20 * (n)))
|
||||
#define INTCPS_MIR_CLEAR(n) (INTERRUPT_BASE + 0x0088 + (0x20 * (n)))
|
||||
#define INTCPS_MIR_SET(n) (INTERRUPT_BASE + 0x008C + (0x20 * (n)))
|
||||
#define INTCPS_ISR_SET(n) (INTERRUPT_BASE + 0x0090 + (0x20 * (n)))
|
||||
#define INTCPS_ISR_CLEAR(n) (INTERRUPT_BASE + 0x0094 + (0x20 * (n)))
|
||||
#define INTCPS_PENDING_IRQ(n) (INTERRUPT_BASE + 0x0098 + (0x20 * (n)))
|
||||
#define INTCPS_PENDING_FIQ(n) (INTERRUPT_BASE + 0x009C + (0x20 * (n)))
|
||||
#define INTCPS_ILR(m) (INTERRUPT_BASE + 0x0100 + (0x04 * (m)))
|
||||
|
||||
#define INTCPS_SIR_IRQ_MASK (0x7F)
|
||||
#define INTCPS_CONTROL_NEWIRQAGR (1UL << 0)
|
||||
|
||||
#endif // __OMAP3530INTERRUPT_H__
|
||||
|
||||
@ -1,208 +0,0 @@
|
||||
/** @file
|
||||
|
||||
Copyright (c) 2008-2009 Apple Inc. All rights reserved.<BR>
|
||||
|
||||
All rights reserved. This program and the accompanying materials
|
||||
are licensed and made available under the terms and conditions of the BSD License
|
||||
which accompanies this distribution. The full text of the license may be found at
|
||||
http://opensource.org/licenses/bsd-license.php
|
||||
|
||||
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
|
||||
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
|
||||
|
||||
**/
|
||||
|
||||
#ifndef __OMAP3530SDIO_H__
|
||||
#define __OMAP3530SDIO_H__
|
||||
|
||||
//MMC/SD/SDIO1 register definitions.
|
||||
#define MMCHS1BASE 0x4809C000
|
||||
#define MMC_REFERENCE_CLK (96000000)
|
||||
|
||||
#define MMCHS_SYSCONFIG (MMCHS1BASE + 0x10)
|
||||
#define SOFTRESET (0x1UL << 1)
|
||||
#define ENAWAKEUP (0x1UL << 2)
|
||||
|
||||
#define MMCHS_SYSSTATUS (MMCHS1BASE + 0x14)
|
||||
#define RESETDONE_MASK (0x1UL << 0)
|
||||
#define RESETDONE (0x1UL << 0)
|
||||
|
||||
#define MMCHS_CSRE (MMCHS1BASE + 0x24)
|
||||
#define MMCHS_SYSTEST (MMCHS1BASE + 0x28)
|
||||
|
||||
#define MMCHS_CON (MMCHS1BASE + 0x2C)
|
||||
#define OD (0x1UL << 0)
|
||||
#define NOINIT (0x0UL << 1)
|
||||
#define INIT (0x1UL << 1)
|
||||
#define HR (0x1UL << 2)
|
||||
#define STR (0x1UL << 3)
|
||||
#define MODE (0x1UL << 4)
|
||||
#define DW8_1_4_BIT (0x0UL << 5)
|
||||
#define DW8_8_BIT (0x1UL << 5)
|
||||
#define MIT (0x1UL << 6)
|
||||
#define CDP (0x1UL << 7)
|
||||
#define WPP (0x1UL << 8)
|
||||
#define CTPL (0x1UL << 11)
|
||||
#define CEATA_OFF (0x0UL << 12)
|
||||
#define CEATA_ON (0x1UL << 12)
|
||||
|
||||
#define MMCHS_PWCNT (MMCHS1BASE + 0x30)
|
||||
|
||||
#define MMCHS_BLK (MMCHS1BASE + 0x104)
|
||||
#define BLEN_512BYTES (0x200UL << 0)
|
||||
|
||||
#define MMCHS_ARG (MMCHS1BASE + 0x108)
|
||||
|
||||
#define MMCHS_CMD (MMCHS1BASE + 0x10C)
|
||||
#define DE_ENABLE (0x1UL << 0)
|
||||
#define BCE_ENABLE (0x1UL << 1)
|
||||
#define ACEN_ENABLE (0x1UL << 2)
|
||||
#define DDIR_READ (0x1UL << 4)
|
||||
#define DDIR_WRITE (0x0UL << 4)
|
||||
#define MSBS_SGLEBLK (0x0UL << 5)
|
||||
#define MSBS_MULTBLK (0x1UL << 5)
|
||||
#define RSP_TYPE_MASK (0x3UL << 16)
|
||||
#define RSP_TYPE_136BITS (0x1UL << 16)
|
||||
#define RSP_TYPE_48BITS (0x2UL << 16)
|
||||
#define CCCE_ENABLE (0x1UL << 19)
|
||||
#define CICE_ENABLE (0x1UL << 20)
|
||||
#define DP_ENABLE (0x1UL << 21)
|
||||
#define INDX(CMD_INDX) ((CMD_INDX & 0x3F) << 24)
|
||||
|
||||
#define MMCHS_RSP10 (MMCHS1BASE + 0x110)
|
||||
#define MMCHS_RSP32 (MMCHS1BASE + 0x114)
|
||||
#define MMCHS_RSP54 (MMCHS1BASE + 0x118)
|
||||
#define MMCHS_RSP76 (MMCHS1BASE + 0x11C)
|
||||
#define MMCHS_DATA (MMCHS1BASE + 0x120)
|
||||
|
||||
#define MMCHS_PSTATE (MMCHS1BASE + 0x124)
|
||||
#define CMDI_MASK (0x1UL << 0)
|
||||
#define CMDI_ALLOWED (0x0UL << 0)
|
||||
#define CMDI_NOT_ALLOWED (0x1UL << 0)
|
||||
#define DATI_MASK (0x1UL << 1)
|
||||
#define DATI_ALLOWED (0x0UL << 1)
|
||||
#define DATI_NOT_ALLOWED (0x1UL << 1)
|
||||
|
||||
#define MMCHS_HCTL (MMCHS1BASE + 0x128)
|
||||
#define DTW_1_BIT (0x0UL << 1)
|
||||
#define DTW_4_BIT (0x1UL << 1)
|
||||
#define SDBP_MASK (0x1UL << 8)
|
||||
#define SDBP_OFF (0x0UL << 8)
|
||||
#define SDBP_ON (0x1UL << 8)
|
||||
#define SDVS_1_8_V (0x5UL << 9)
|
||||
#define SDVS_3_0_V (0x6UL << 9)
|
||||
#define IWE (0x1UL << 24)
|
||||
|
||||
#define MMCHS_SYSCTL (MMCHS1BASE + 0x12C)
|
||||
#define ICE (0x1UL << 0)
|
||||
#define ICS_MASK (0x1UL << 1)
|
||||
#define ICS (0x1UL << 1)
|
||||
#define CEN (0x1UL << 2)
|
||||
#define CLKD_MASK (0x3FFUL << 6)
|
||||
#define CLKD_80KHZ (0x258UL) //(96*1000/80)/2
|
||||
#define CLKD_400KHZ (0xF0UL)
|
||||
#define DTO_MASK (0xFUL << 16)
|
||||
#define DTO_VAL (0xEUL << 16)
|
||||
#define SRA (0x1UL << 24)
|
||||
#define SRC_MASK (0x1UL << 25)
|
||||
#define SRC (0x1UL << 25)
|
||||
#define SRD (0x1UL << 26)
|
||||
|
||||
#define MMCHS_STAT (MMCHS1BASE + 0x130)
|
||||
#define CC (0x1UL << 0)
|
||||
#define TC (0x1UL << 1)
|
||||
#define BWR (0x1UL << 4)
|
||||
#define BRR (0x1UL << 5)
|
||||
#define ERRI (0x1UL << 15)
|
||||
#define CTO (0x1UL << 16)
|
||||
#define DTO (0x1UL << 20)
|
||||
#define DCRC (0x1UL << 21)
|
||||
#define DEB (0x1UL << 22)
|
||||
|
||||
#define MMCHS_IE (MMCHS1BASE + 0x134)
|
||||
#define CC_EN (0x1UL << 0)
|
||||
#define TC_EN (0x1UL << 1)
|
||||
#define BWR_EN (0x1UL << 4)
|
||||
#define BRR_EN (0x1UL << 5)
|
||||
#define CTO_EN (0x1UL << 16)
|
||||
#define CCRC_EN (0x1UL << 17)
|
||||
#define CEB_EN (0x1UL << 18)
|
||||
#define CIE_EN (0x1UL << 19)
|
||||
#define DTO_EN (0x1UL << 20)
|
||||
#define DCRC_EN (0x1UL << 21)
|
||||
#define DEB_EN (0x1UL << 22)
|
||||
#define CERR_EN (0x1UL << 28)
|
||||
#define BADA_EN (0x1UL << 29)
|
||||
|
||||
#define MMCHS_ISE (MMCHS1BASE + 0x138)
|
||||
#define CC_SIGEN (0x1UL << 0)
|
||||
#define TC_SIGEN (0x1UL << 1)
|
||||
#define BWR_SIGEN (0x1UL << 4)
|
||||
#define BRR_SIGEN (0x1UL << 5)
|
||||
#define CTO_SIGEN (0x1UL << 16)
|
||||
#define CCRC_SIGEN (0x1UL << 17)
|
||||
#define CEB_SIGEN (0x1UL << 18)
|
||||
#define CIE_SIGEN (0x1UL << 19)
|
||||
#define DTO_SIGEN (0x1UL << 20)
|
||||
#define DCRC_SIGEN (0x1UL << 21)
|
||||
#define DEB_SIGEN (0x1UL << 22)
|
||||
#define CERR_SIGEN (0x1UL << 28)
|
||||
#define BADA_SIGEN (0x1UL << 29)
|
||||
|
||||
#define MMCHS_AC12 (MMCHS1BASE + 0x13C)
|
||||
|
||||
#define MMCHS_CAPA (MMCHS1BASE + 0x140)
|
||||
#define VS30 (0x1UL << 25)
|
||||
#define VS18 (0x1UL << 26)
|
||||
|
||||
#define MMCHS_CUR_CAPA (MMCHS1BASE + 0x148)
|
||||
#define MMCHS_REV (MMCHS1BASE + 0x1FC)
|
||||
|
||||
#define CMD0 INDX(0)
|
||||
#define CMD0_INT_EN (CC_EN | CEB_EN)
|
||||
|
||||
#define CMD1 (INDX(1) | RSP_TYPE_48BITS)
|
||||
#define CMD1_INT_EN (CC_EN | CEB_EN | CTO_EN)
|
||||
|
||||
#define CMD2 (INDX(2) | CCCE_ENABLE | RSP_TYPE_136BITS)
|
||||
#define CMD2_INT_EN (CERR_EN | CIE_EN | CCRC_EN | CC_EN | CEB_EN | CTO_EN)
|
||||
|
||||
#define CMD3 (INDX(3) | CICE_ENABLE | CCCE_ENABLE | RSP_TYPE_48BITS)
|
||||
#define CMD3_INT_EN (CERR_EN | CIE_EN | CCRC_EN | CC_EN | CEB_EN | CTO_EN)
|
||||
|
||||
#define CMD5 (INDX(5) | RSP_TYPE_48BITS)
|
||||
#define CMD5_INT_EN (CC_EN | CEB_EN | CTO_EN)
|
||||
|
||||
#define CMD7 (INDX(7) | CICE_ENABLE | CCCE_ENABLE | RSP_TYPE_48BITS)
|
||||
#define CMD7_INT_EN (CERR_EN | CIE_EN | CCRC_EN | CC_EN | CEB_EN | CTO_EN)
|
||||
|
||||
#define CMD8 (INDX(8) | CICE_ENABLE | CCCE_ENABLE | RSP_TYPE_48BITS)
|
||||
#define CMD8_INT_EN (CERR_EN | CIE_EN | CCRC_EN | CC_EN | CEB_EN | CTO_EN)
|
||||
//Reserved(0)[12:31], Supply voltage(1)[11:8], check pattern(0xCE)[7:0] = 0x1CE
|
||||
#define CMD8_ARG (0x0UL << 12 | 0x1UL << 8 | 0xCEUL << 0)
|
||||
|
||||
#define CMD9 (INDX(9) | CCCE_ENABLE | RSP_TYPE_136BITS)
|
||||
#define CMD9_INT_EN (CCRC_EN | CC_EN | CEB_EN | CTO_EN)
|
||||
|
||||
#define CMD16 (INDX(16) | CICE_ENABLE | CCCE_ENABLE | RSP_TYPE_48BITS)
|
||||
#define CMD16_INT_EN (CERR_EN | CIE_EN | CCRC_EN | CC_EN | CEB_EN | CTO_EN)
|
||||
|
||||
#define CMD17 (INDX(17) | DP_ENABLE | CICE_ENABLE | CCCE_ENABLE | RSP_TYPE_48BITS | DDIR_READ)
|
||||
#define CMD17_INT_EN (CERR_EN | CIE_EN | CCRC_EN | CC_EN | TC_EN | BRR_EN | CTO_EN | DTO_EN | DCRC_EN | DEB_EN | CEB_EN)
|
||||
|
||||
#define CMD18 (INDX(18) | DP_ENABLE | CICE_ENABLE | CCCE_ENABLE | RSP_TYPE_48BITS | MSBS_MULTBLK | DDIR_READ | BCE_ENABLE | DE_ENABLE)
|
||||
#define CMD18_INT_EN (CERR_EN | CIE_EN | CCRC_EN | CC_EN | TC_EN | BRR_EN | CTO_EN | DTO_EN | DCRC_EN | DEB_EN | CEB_EN)
|
||||
|
||||
#define CMD23 (INDX(23) | CICE_ENABLE | CCCE_ENABLE | RSP_TYPE_48BITS)
|
||||
#define CMD23_INT_EN (CERR_EN | CIE_EN | CCRC_EN | CC_EN | CEB_EN | CTO_EN)
|
||||
|
||||
#define CMD24 (INDX(24) | DP_ENABLE | CICE_ENABLE | CCCE_ENABLE | RSP_TYPE_48BITS | DDIR_WRITE)
|
||||
#define CMD24_INT_EN (CERR_EN | CIE_EN | CCRC_EN | CC_EN | TC_EN | BWR_EN | CTO_EN | DTO_EN | DCRC_EN | DEB_EN | CEB_EN)
|
||||
|
||||
#define CMD55 (INDX(55) | CICE_ENABLE | CCCE_ENABLE | RSP_TYPE_48BITS)
|
||||
#define CMD55_INT_EN (CERR_EN | CIE_EN | CCRC_EN | CC_EN | CEB_EN | CTO_EN)
|
||||
|
||||
#define ACMD41 (INDX(41) | RSP_TYPE_48BITS)
|
||||
#define ACMD41_INT_EN (CERR_EN | CIE_EN | CCRC_EN | CC_EN | CEB_EN | CTO_EN)
|
||||
|
||||
#endif //__OMAP3530SDIO_H__
|
||||
@ -1,298 +0,0 @@
|
||||
/** @file
|
||||
|
||||
Copyright (c) 2008-2009 Apple Inc. All rights reserved.<BR>
|
||||
|
||||
All rights reserved. This program and the accompanying materials
|
||||
are licensed and made available under the terms and conditions of the BSD License
|
||||
which accompanies this distribution. The full text of the license may be found at
|
||||
http://opensource.org/licenses/bsd-license.php
|
||||
|
||||
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
|
||||
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
|
||||
|
||||
**/
|
||||
|
||||
#ifndef __OMAP3530_PAD_CONFIGURATION_H__
|
||||
#define __OMAP3530_PAD_CONFIGURATION_H__
|
||||
|
||||
#define SYSTEM_CONTROL_MODULE_BASE 0x48002000
|
||||
|
||||
//Pin definition
|
||||
#define SDRC_D0 (SYSTEM_CONTROL_MODULE_BASE + 0x030)
|
||||
#define SDRC_D1 (SYSTEM_CONTROL_MODULE_BASE + 0x032)
|
||||
#define SDRC_D2 (SYSTEM_CONTROL_MODULE_BASE + 0x034)
|
||||
#define SDRC_D3 (SYSTEM_CONTROL_MODULE_BASE + 0x036)
|
||||
#define SDRC_D4 (SYSTEM_CONTROL_MODULE_BASE + 0x038)
|
||||
#define SDRC_D5 (SYSTEM_CONTROL_MODULE_BASE + 0x03A)
|
||||
#define SDRC_D6 (SYSTEM_CONTROL_MODULE_BASE + 0x03C)
|
||||
#define SDRC_D7 (SYSTEM_CONTROL_MODULE_BASE + 0x03E)
|
||||
#define SDRC_D8 (SYSTEM_CONTROL_MODULE_BASE + 0x040)
|
||||
#define SDRC_D9 (SYSTEM_CONTROL_MODULE_BASE + 0x042)
|
||||
#define SDRC_D10 (SYSTEM_CONTROL_MODULE_BASE + 0x044)
|
||||
#define SDRC_D11 (SYSTEM_CONTROL_MODULE_BASE + 0x046)
|
||||
#define SDRC_D12 (SYSTEM_CONTROL_MODULE_BASE + 0x048)
|
||||
#define SDRC_D13 (SYSTEM_CONTROL_MODULE_BASE + 0x04A)
|
||||
#define SDRC_D14 (SYSTEM_CONTROL_MODULE_BASE + 0x04C)
|
||||
#define SDRC_D15 (SYSTEM_CONTROL_MODULE_BASE + 0x04E)
|
||||
#define SDRC_D16 (SYSTEM_CONTROL_MODULE_BASE + 0x050)
|
||||
#define SDRC_D17 (SYSTEM_CONTROL_MODULE_BASE + 0x052)
|
||||
#define SDRC_D18 (SYSTEM_CONTROL_MODULE_BASE + 0x054)
|
||||
#define SDRC_D19 (SYSTEM_CONTROL_MODULE_BASE + 0x056)
|
||||
#define SDRC_D20 (SYSTEM_CONTROL_MODULE_BASE + 0x058)
|
||||
#define SDRC_D21 (SYSTEM_CONTROL_MODULE_BASE + 0x05A)
|
||||
#define SDRC_D22 (SYSTEM_CONTROL_MODULE_BASE + 0x05C)
|
||||
#define SDRC_D23 (SYSTEM_CONTROL_MODULE_BASE + 0x05E)
|
||||
#define SDRC_D24 (SYSTEM_CONTROL_MODULE_BASE + 0x060)
|
||||
#define SDRC_D25 (SYSTEM_CONTROL_MODULE_BASE + 0x062)
|
||||
#define SDRC_D26 (SYSTEM_CONTROL_MODULE_BASE + 0x064)
|
||||
#define SDRC_D27 (SYSTEM_CONTROL_MODULE_BASE + 0x066)
|
||||
#define SDRC_D28 (SYSTEM_CONTROL_MODULE_BASE + 0x068)
|
||||
#define SDRC_D29 (SYSTEM_CONTROL_MODULE_BASE + 0x06A)
|
||||
#define SDRC_D30 (SYSTEM_CONTROL_MODULE_BASE + 0x06C)
|
||||
#define SDRC_D31 (SYSTEM_CONTROL_MODULE_BASE + 0x06E)
|
||||
#define SDRC_CLK (SYSTEM_CONTROL_MODULE_BASE + 0x070)
|
||||
#define SDRC_DQS0 (SYSTEM_CONTROL_MODULE_BASE + 0x072)
|
||||
#define SDRC_CKE0 (SYSTEM_CONTROL_MODULE_BASE + 0x262)
|
||||
#define SDRC_CKE1 (SYSTEM_CONTROL_MODULE_BASE + 0x264)
|
||||
#define SDRC_DQS1 (SYSTEM_CONTROL_MODULE_BASE + 0x074)
|
||||
#define SDRC_DQS2 (SYSTEM_CONTROL_MODULE_BASE + 0x076)
|
||||
#define SDRC_DQS3 (SYSTEM_CONTROL_MODULE_BASE + 0x078)
|
||||
#define GPMC_A1 (SYSTEM_CONTROL_MODULE_BASE + 0x07A)
|
||||
#define GPMC_A2 (SYSTEM_CONTROL_MODULE_BASE + 0x07C)
|
||||
#define GPMC_A3 (SYSTEM_CONTROL_MODULE_BASE + 0x07E)
|
||||
#define GPMC_A4 (SYSTEM_CONTROL_MODULE_BASE + 0x080)
|
||||
#define GPMC_A5 (SYSTEM_CONTROL_MODULE_BASE + 0x082)
|
||||
#define GPMC_A6 (SYSTEM_CONTROL_MODULE_BASE + 0x084)
|
||||
#define GPMC_A7 (SYSTEM_CONTROL_MODULE_BASE + 0x086)
|
||||
#define GPMC_A8 (SYSTEM_CONTROL_MODULE_BASE + 0x088)
|
||||
#define GPMC_A9 (SYSTEM_CONTROL_MODULE_BASE + 0x08A)
|
||||
#define GPMC_A10 (SYSTEM_CONTROL_MODULE_BASE + 0x08C)
|
||||
#define GPMC_D0 (SYSTEM_CONTROL_MODULE_BASE + 0x08E)
|
||||
#define GPMC_D1 (SYSTEM_CONTROL_MODULE_BASE + 0x090)
|
||||
#define GPMC_D2 (SYSTEM_CONTROL_MODULE_BASE + 0x092)
|
||||
#define GPMC_D3 (SYSTEM_CONTROL_MODULE_BASE + 0x094)
|
||||
#define GPMC_D4 (SYSTEM_CONTROL_MODULE_BASE + 0x096)
|
||||
#define GPMC_D5 (SYSTEM_CONTROL_MODULE_BASE + 0x098)
|
||||
#define GPMC_D6 (SYSTEM_CONTROL_MODULE_BASE + 0x09A)
|
||||
#define GPMC_D7 (SYSTEM_CONTROL_MODULE_BASE + 0x09C)
|
||||
#define GPMC_D8 (SYSTEM_CONTROL_MODULE_BASE + 0x09E)
|
||||
#define GPMC_D9 (SYSTEM_CONTROL_MODULE_BASE + 0x0A0)
|
||||
#define GPMC_D10 (SYSTEM_CONTROL_MODULE_BASE + 0x0A2)
|
||||
#define GPMC_D11 (SYSTEM_CONTROL_MODULE_BASE + 0x0A4)
|
||||
#define GPMC_D12 (SYSTEM_CONTROL_MODULE_BASE + 0x0A6)
|
||||
#define GPMC_D13 (SYSTEM_CONTROL_MODULE_BASE + 0x0A8)
|
||||
#define GPMC_D14 (SYSTEM_CONTROL_MODULE_BASE + 0x0AA)
|
||||
#define GPMC_D15 (SYSTEM_CONTROL_MODULE_BASE + 0x0AC)
|
||||
#define GPMC_NCS0 (SYSTEM_CONTROL_MODULE_BASE + 0x0AE)
|
||||
#define GPMC_NCS1 (SYSTEM_CONTROL_MODULE_BASE + 0x0B0)
|
||||
#define GPMC_NCS2 (SYSTEM_CONTROL_MODULE_BASE + 0x0B2)
|
||||
#define GPMC_NCS3 (SYSTEM_CONTROL_MODULE_BASE + 0x0B4)
|
||||
#define GPMC_NCS4 (SYSTEM_CONTROL_MODULE_BASE + 0x0B6)
|
||||
#define GPMC_NCS5 (SYSTEM_CONTROL_MODULE_BASE + 0x0B8)
|
||||
#define GPMC_NCS6 (SYSTEM_CONTROL_MODULE_BASE + 0x0BA)
|
||||
#define GPMC_NCS7 (SYSTEM_CONTROL_MODULE_BASE + 0x0BC)
|
||||
#define GPMC_CLK (SYSTEM_CONTROL_MODULE_BASE + 0x0BE)
|
||||
#define GPMC_NADV_ALE (SYSTEM_CONTROL_MODULE_BASE + 0x0C0)
|
||||
#define GPMC_NOE (SYSTEM_CONTROL_MODULE_BASE + 0x0C2)
|
||||
#define GPMC_NWE (SYSTEM_CONTROL_MODULE_BASE + 0x0C4)
|
||||
#define GPMC_NBE0_CLE (SYSTEM_CONTROL_MODULE_BASE + 0x0C6)
|
||||
#define GPMC_NBE1 (SYSTEM_CONTROL_MODULE_BASE + 0x0C8)
|
||||
#define GPMC_NWP (SYSTEM_CONTROL_MODULE_BASE + 0x0CA)
|
||||
#define GPMC_WAIT0 (SYSTEM_CONTROL_MODULE_BASE + 0x0CC)
|
||||
#define GPMC_WAIT1 (SYSTEM_CONTROL_MODULE_BASE + 0x0CE)
|
||||
#define GPMC_WAIT2 (SYSTEM_CONTROL_MODULE_BASE + 0x0D0)
|
||||
#define GPMC_WAIT3 (SYSTEM_CONTROL_MODULE_BASE + 0x0D2)
|
||||
#define DSS_PCLK (SYSTEM_CONTROL_MODULE_BASE + 0x0D4)
|
||||
#define DSS_HSYNC (SYSTEM_CONTROL_MODULE_BASE + 0x0D6)
|
||||
#define DSS_PSYNC (SYSTEM_CONTROL_MODULE_BASE + 0x0D8)
|
||||
#define DSS_ACBIAS (SYSTEM_CONTROL_MODULE_BASE + 0x0DA)
|
||||
#define DSS_DATA0 (SYSTEM_CONTROL_MODULE_BASE + 0x0DC)
|
||||
#define DSS_DATA1 (SYSTEM_CONTROL_MODULE_BASE + 0x0DE)
|
||||
#define DSS_DATA2 (SYSTEM_CONTROL_MODULE_BASE + 0x0E0)
|
||||
#define DSS_DATA3 (SYSTEM_CONTROL_MODULE_BASE + 0x0E2)
|
||||
#define DSS_DATA4 (SYSTEM_CONTROL_MODULE_BASE + 0x0E4)
|
||||
#define DSS_DATA5 (SYSTEM_CONTROL_MODULE_BASE + 0x0E6)
|
||||
#define DSS_DATA6 (SYSTEM_CONTROL_MODULE_BASE + 0x0E8)
|
||||
#define DSS_DATA7 (SYSTEM_CONTROL_MODULE_BASE + 0x0EA)
|
||||
#define DSS_DATA8 (SYSTEM_CONTROL_MODULE_BASE + 0x0EC)
|
||||
#define DSS_DATA9 (SYSTEM_CONTROL_MODULE_BASE + 0x0EE)
|
||||
#define DSS_DATA10 (SYSTEM_CONTROL_MODULE_BASE + 0x0F0)
|
||||
#define DSS_DATA11 (SYSTEM_CONTROL_MODULE_BASE + 0x0F2)
|
||||
#define DSS_DATA12 (SYSTEM_CONTROL_MODULE_BASE + 0x0F4)
|
||||
#define DSS_DATA13 (SYSTEM_CONTROL_MODULE_BASE + 0x0F6)
|
||||
#define DSS_DATA14 (SYSTEM_CONTROL_MODULE_BASE + 0x0F8)
|
||||
#define DSS_DATA15 (SYSTEM_CONTROL_MODULE_BASE + 0x0FA)
|
||||
#define DSS_DATA16 (SYSTEM_CONTROL_MODULE_BASE + 0x0FC)
|
||||
#define DSS_DATA17 (SYSTEM_CONTROL_MODULE_BASE + 0x0FE)
|
||||
#define DSS_DATA18 (SYSTEM_CONTROL_MODULE_BASE + 0x100)
|
||||
#define DSS_DATA19 (SYSTEM_CONTROL_MODULE_BASE + 0x102)
|
||||
#define DSS_DATA20 (SYSTEM_CONTROL_MODULE_BASE + 0x104)
|
||||
#define DSS_DATA21 (SYSTEM_CONTROL_MODULE_BASE + 0x106)
|
||||
#define DSS_DATA22 (SYSTEM_CONTROL_MODULE_BASE + 0x108)
|
||||
#define DSS_DATA23 (SYSTEM_CONTROL_MODULE_BASE + 0x10A)
|
||||
#define CAM_HS (SYSTEM_CONTROL_MODULE_BASE + 0x10C)
|
||||
#define CAM_VS (SYSTEM_CONTROL_MODULE_BASE + 0x10E)
|
||||
#define CAM_XCLKA (SYSTEM_CONTROL_MODULE_BASE + 0x110)
|
||||
#define CAM_PCLK (SYSTEM_CONTROL_MODULE_BASE + 0x112)
|
||||
#define CAM_FLD (SYSTEM_CONTROL_MODULE_BASE + 0x114)
|
||||
#define CAM_D0 (SYSTEM_CONTROL_MODULE_BASE + 0x116)
|
||||
#define CAM_D1 (SYSTEM_CONTROL_MODULE_BASE + 0x118)
|
||||
#define CAM_D2 (SYSTEM_CONTROL_MODULE_BASE + 0x11A)
|
||||
#define CAM_D3 (SYSTEM_CONTROL_MODULE_BASE + 0x11C)
|
||||
#define CAM_D4 (SYSTEM_CONTROL_MODULE_BASE + 0x11E)
|
||||
#define CAM_D5 (SYSTEM_CONTROL_MODULE_BASE + 0x120)
|
||||
#define CAM_D6 (SYSTEM_CONTROL_MODULE_BASE + 0x122)
|
||||
#define CAM_D7 (SYSTEM_CONTROL_MODULE_BASE + 0x124)
|
||||
#define CAM_D8 (SYSTEM_CONTROL_MODULE_BASE + 0x126)
|
||||
#define CAM_D9 (SYSTEM_CONTROL_MODULE_BASE + 0x128)
|
||||
#define CAM_D10 (SYSTEM_CONTROL_MODULE_BASE + 0x12A)
|
||||
#define CAM_D11 (SYSTEM_CONTROL_MODULE_BASE + 0x12C)
|
||||
#define CAM_XCLKB (SYSTEM_CONTROL_MODULE_BASE + 0x12E)
|
||||
#define CAM_WEN (SYSTEM_CONTROL_MODULE_BASE + 0x130)
|
||||
#define CAM_STROBE (SYSTEM_CONTROL_MODULE_BASE + 0x132)
|
||||
#define CSI2_DX0 (SYSTEM_CONTROL_MODULE_BASE + 0x134)
|
||||
#define CSI2_DY0 (SYSTEM_CONTROL_MODULE_BASE + 0x136)
|
||||
#define CSI2_DX1 (SYSTEM_CONTROL_MODULE_BASE + 0x138)
|
||||
#define CSI2_DY1 (SYSTEM_CONTROL_MODULE_BASE + 0x13A)
|
||||
#define MCBSP2_FSX (SYSTEM_CONTROL_MODULE_BASE + 0x13C)
|
||||
#define MCBSP2_CLKX (SYSTEM_CONTROL_MODULE_BASE + 0x13E)
|
||||
#define MCBSP2_DR (SYSTEM_CONTROL_MODULE_BASE + 0x140)
|
||||
#define MCBSP2_DX (SYSTEM_CONTROL_MODULE_BASE + 0x142)
|
||||
#define MMC1_CLK (SYSTEM_CONTROL_MODULE_BASE + 0x144)
|
||||
#define MMC1_CMD (SYSTEM_CONTROL_MODULE_BASE + 0x146)
|
||||
#define MMC1_DAT0 (SYSTEM_CONTROL_MODULE_BASE + 0x148)
|
||||
#define MMC1_DAT1 (SYSTEM_CONTROL_MODULE_BASE + 0x14A)
|
||||
#define MMC1_DAT2 (SYSTEM_CONTROL_MODULE_BASE + 0x14C)
|
||||
#define MMC1_DAT3 (SYSTEM_CONTROL_MODULE_BASE + 0x14E)
|
||||
#define MMC1_DAT4 (SYSTEM_CONTROL_MODULE_BASE + 0x150)
|
||||
#define MMC1_DAT5 (SYSTEM_CONTROL_MODULE_BASE + 0x152)
|
||||
#define MMC1_DAT6 (SYSTEM_CONTROL_MODULE_BASE + 0x154)
|
||||
#define MMC1_DAT7 (SYSTEM_CONTROL_MODULE_BASE + 0x156)
|
||||
#define MMC2_CLK (SYSTEM_CONTROL_MODULE_BASE + 0x158)
|
||||
#define MMC2_CMD (SYSTEM_CONTROL_MODULE_BASE + 0x15A)
|
||||
#define MMC2_DAT0 (SYSTEM_CONTROL_MODULE_BASE + 0x15C)
|
||||
#define MMC2_DAT1 (SYSTEM_CONTROL_MODULE_BASE + 0x15E)
|
||||
#define MMC2_DAT2 (SYSTEM_CONTROL_MODULE_BASE + 0x160)
|
||||
#define MMC2_DAT3 (SYSTEM_CONTROL_MODULE_BASE + 0x162)
|
||||
#define MMC2_DAT4 (SYSTEM_CONTROL_MODULE_BASE + 0x164)
|
||||
#define MMC2_DAT5 (SYSTEM_CONTROL_MODULE_BASE + 0x166)
|
||||
#define MMC2_DAT6 (SYSTEM_CONTROL_MODULE_BASE + 0x168)
|
||||
#define MMC2_DAT7 (SYSTEM_CONTROL_MODULE_BASE + 0x16A)
|
||||
#define MCBSP3_DX (SYSTEM_CONTROL_MODULE_BASE + 0x16C)
|
||||
#define MCBSP3_DR (SYSTEM_CONTROL_MODULE_BASE + 0x16E)
|
||||
#define MCBSP3_CLKX (SYSTEM_CONTROL_MODULE_BASE + 0x170)
|
||||
#define MCBSP3_FSX (SYSTEM_CONTROL_MODULE_BASE + 0x172)
|
||||
#define UART2_CTS (SYSTEM_CONTROL_MODULE_BASE + 0x174)
|
||||
#define UART2_RTS (SYSTEM_CONTROL_MODULE_BASE + 0x176)
|
||||
#define UART2_TX (SYSTEM_CONTROL_MODULE_BASE + 0x178)
|
||||
#define UART2_RX (SYSTEM_CONTROL_MODULE_BASE + 0x17A)
|
||||
#define UART1_TX (SYSTEM_CONTROL_MODULE_BASE + 0x17C)
|
||||
#define UART1_RTS (SYSTEM_CONTROL_MODULE_BASE + 0x17E)
|
||||
#define UART1_CTS (SYSTEM_CONTROL_MODULE_BASE + 0x180)
|
||||
#define UART1_RX (SYSTEM_CONTROL_MODULE_BASE + 0x182)
|
||||
#define MCBSP4_CLKX (SYSTEM_CONTROL_MODULE_BASE + 0x184)
|
||||
#define MCBSP4_DR (SYSTEM_CONTROL_MODULE_BASE + 0x186)
|
||||
#define MCBSP4_DX (SYSTEM_CONTROL_MODULE_BASE + 0x188)
|
||||
#define MCBSP4_FSX (SYSTEM_CONTROL_MODULE_BASE + 0x18A)
|
||||
#define MCBSP1_CLKR (SYSTEM_CONTROL_MODULE_BASE + 0x18C)
|
||||
#define MCBSP1_FSR (SYSTEM_CONTROL_MODULE_BASE + 0x18E)
|
||||
#define MCBSP1_DX (SYSTEM_CONTROL_MODULE_BASE + 0x190)
|
||||
#define MCBSP1_DR (SYSTEM_CONTROL_MODULE_BASE + 0x192)
|
||||
#define MCBSP1_CLKS (SYSTEM_CONTROL_MODULE_BASE + 0x194)
|
||||
#define MCBSP1_FSX (SYSTEM_CONTROL_MODULE_BASE + 0x196)
|
||||
#define MCBSP1_CLKX (SYSTEM_CONTROL_MODULE_BASE + 0x198)
|
||||
#define UART3_CTS_RCTX (SYSTEM_CONTROL_MODULE_BASE + 0x19A)
|
||||
#define UART3_RTS_SD (SYSTEM_CONTROL_MODULE_BASE + 0x19C)
|
||||
#define UART3_RX_IRRX (SYSTEM_CONTROL_MODULE_BASE + 0x19E)
|
||||
#define UART3_TX_IRTX (SYSTEM_CONTROL_MODULE_BASE + 0x1A0)
|
||||
#define HSUSB0_CLK (SYSTEM_CONTROL_MODULE_BASE + 0x1A2)
|
||||
#define HSUSB0_STP (SYSTEM_CONTROL_MODULE_BASE + 0x1A4)
|
||||
#define HSUSB0_DIR (SYSTEM_CONTROL_MODULE_BASE + 0x1A6)
|
||||
#define HSUSB0_NXT (SYSTEM_CONTROL_MODULE_BASE + 0x1A8)
|
||||
#define HSUSB0_DATA0 (SYSTEM_CONTROL_MODULE_BASE + 0x1AA)
|
||||
#define HSUSB0_DATA1 (SYSTEM_CONTROL_MODULE_BASE + 0x1AC)
|
||||
#define HSUSB0_DATA2 (SYSTEM_CONTROL_MODULE_BASE + 0x1AE)
|
||||
#define HSUSB0_DATA3 (SYSTEM_CONTROL_MODULE_BASE + 0x1B0)
|
||||
#define HSUSB0_DATA4 (SYSTEM_CONTROL_MODULE_BASE + 0x1B2)
|
||||
#define HSUSB0_DATA5 (SYSTEM_CONTROL_MODULE_BASE + 0x1B4)
|
||||
#define HSUSB0_DATA6 (SYSTEM_CONTROL_MODULE_BASE + 0x1B6)
|
||||
#define HSUSB0_DATA7 (SYSTEM_CONTROL_MODULE_BASE + 0x1B8)
|
||||
#define I2C1_SCL (SYSTEM_CONTROL_MODULE_BASE + 0x1BA)
|
||||
#define I2C1_SDA (SYSTEM_CONTROL_MODULE_BASE + 0x1BC)
|
||||
#define I2C2_SCL (SYSTEM_CONTROL_MODULE_BASE + 0x1BE)
|
||||
#define I2C2_SDA (SYSTEM_CONTROL_MODULE_BASE + 0x1C0)
|
||||
#define I2C3_SCL (SYSTEM_CONTROL_MODULE_BASE + 0x1C2)
|
||||
#define I2C3_SDA (SYSTEM_CONTROL_MODULE_BASE + 0x1C4)
|
||||
#define HDQ_SIO (SYSTEM_CONTROL_MODULE_BASE + 0x1C6)
|
||||
#define MCSPI1_CLK (SYSTEM_CONTROL_MODULE_BASE + 0x1C8)
|
||||
#define MCSPI1_SIMO (SYSTEM_CONTROL_MODULE_BASE + 0x1CA)
|
||||
#define MCSPI1_SOMI (SYSTEM_CONTROL_MODULE_BASE + 0x1CC)
|
||||
#define MCSPI1_CS0 (SYSTEM_CONTROL_MODULE_BASE + 0x1CE)
|
||||
#define MCSPI1_CS1 (SYSTEM_CONTROL_MODULE_BASE + 0x1D0)
|
||||
#define MCSPI1_CS2 (SYSTEM_CONTROL_MODULE_BASE + 0x1D2)
|
||||
#define MCSPI1_CS3 (SYSTEM_CONTROL_MODULE_BASE + 0x1D4)
|
||||
#define MCSPI2_CLK (SYSTEM_CONTROL_MODULE_BASE + 0x1D6)
|
||||
#define MCSPI2_SIMO (SYSTEM_CONTROL_MODULE_BASE + 0x1D8)
|
||||
#define MCSPI2_SOMI (SYSTEM_CONTROL_MODULE_BASE + 0x1DA)
|
||||
#define MCSPI2_CS0 (SYSTEM_CONTROL_MODULE_BASE + 0x1DC)
|
||||
#define MCSPI2_CS1 (SYSTEM_CONTROL_MODULE_BASE + 0x1DE)
|
||||
#define SYS_NIRQ (SYSTEM_CONTROL_MODULE_BASE + 0x1E0)
|
||||
#define SYS_CLKOUT2 (SYSTEM_CONTROL_MODULE_BASE + 0x1E2)
|
||||
#define ETK_CLK (SYSTEM_CONTROL_MODULE_BASE + 0x5D8)
|
||||
#define ETK_CTL (SYSTEM_CONTROL_MODULE_BASE + 0x5DA)
|
||||
#define ETK_D0 (SYSTEM_CONTROL_MODULE_BASE + 0x5DC)
|
||||
#define ETK_D1 (SYSTEM_CONTROL_MODULE_BASE + 0x5DE)
|
||||
#define ETK_D2 (SYSTEM_CONTROL_MODULE_BASE + 0x5E0)
|
||||
#define ETK_D3 (SYSTEM_CONTROL_MODULE_BASE + 0x5E2)
|
||||
#define ETK_D4 (SYSTEM_CONTROL_MODULE_BASE + 0x5E4)
|
||||
#define ETK_D5 (SYSTEM_CONTROL_MODULE_BASE + 0x5E6)
|
||||
#define ETK_D6 (SYSTEM_CONTROL_MODULE_BASE + 0x5E8)
|
||||
#define ETK_D7 (SYSTEM_CONTROL_MODULE_BASE + 0x5EA)
|
||||
#define ETK_D8 (SYSTEM_CONTROL_MODULE_BASE + 0x5EC)
|
||||
#define ETK_D9 (SYSTEM_CONTROL_MODULE_BASE + 0x5EE)
|
||||
#define ETK_D10 (SYSTEM_CONTROL_MODULE_BASE + 0x5F0)
|
||||
#define ETK_D11 (SYSTEM_CONTROL_MODULE_BASE + 0x5F2)
|
||||
#define ETK_D12 (SYSTEM_CONTROL_MODULE_BASE + 0x5F4)
|
||||
#define ETK_D13 (SYSTEM_CONTROL_MODULE_BASE + 0x5F6)
|
||||
#define ETK_D14 (SYSTEM_CONTROL_MODULE_BASE + 0x5F8)
|
||||
#define ETK_D15 (SYSTEM_CONTROL_MODULE_BASE + 0x5FA)
|
||||
|
||||
//Mux modes
|
||||
#define MUXMODE0 (0x0UL)
|
||||
#define MUXMODE1 (0x1UL)
|
||||
#define MUXMODE2 (0x2UL)
|
||||
#define MUXMODE3 (0x3UL)
|
||||
#define MUXMODE4 (0x4UL)
|
||||
#define MUXMODE5 (0x5UL)
|
||||
#define MUXMODE6 (0x6UL)
|
||||
#define MUXMODE7 (0x7UL)
|
||||
|
||||
//Pad configuration register.
|
||||
#define PAD_CONFIG_MASK (0xFFFFUL)
|
||||
#define MUXMODE_OFFSET 0
|
||||
#define MUXMODE_MASK (0x7UL << MUXMODE_OFFSET)
|
||||
#define PULL_CONFIG_OFFSET 3
|
||||
#define PULL_CONFIG_MASK (0x3UL << PULL_CONFIG_OFFSET)
|
||||
#define INPUTENABLE_OFFSET 8
|
||||
#define INPUTENABLE_MASK (0x1UL << INPUTENABLE_OFFSET)
|
||||
#define OFFMODE_VALUE_OFFSET 9
|
||||
#define OFFMODE_VALUE_MASK (0x1FUL << OFFMODE_VALUE_OFFSET)
|
||||
#define WAKEUP_OFFSET 14
|
||||
#define WAKEUP_MASK (0x2UL << WAKEUP_OFFSET)
|
||||
|
||||
#define PULLUDDISABLE (0x0UL << 0)
|
||||
#define PULLUDENABLE (0x1UL << 0)
|
||||
#define PULLTYPENOSELECT (0x0UL << 1)
|
||||
#define PULLTYPESELECT (0x1UL << 1)
|
||||
|
||||
#define OUTPUT (0x0UL) //Pin is configured in output only mode.
|
||||
#define INPUT (0x1UL) //Pin is configured in bi-directional mode.
|
||||
|
||||
typedef struct {
|
||||
UINTN Pin;
|
||||
UINTN MuxMode;
|
||||
UINTN PullConfig;
|
||||
UINTN InputEnable;
|
||||
} PAD_CONFIGURATION;
|
||||
|
||||
#endif //__OMAP3530_PAD_CONFIGURATION_H__
|
||||
@ -1,164 +0,0 @@
|
||||
/** @file
|
||||
|
||||
Copyright (c) 2008-2009 Apple Inc. All rights reserved.<BR>
|
||||
|
||||
All rights reserved. This program and the accompanying materials
|
||||
are licensed and made available under the terms and conditions of the BSD License
|
||||
which accompanies this distribution. The full text of the license may be found at
|
||||
http://opensource.org/licenses/bsd-license.php
|
||||
|
||||
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
|
||||
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
|
||||
|
||||
**/
|
||||
|
||||
#ifndef __OMAP3530PRCM_H__
|
||||
#define __OMAP3530PRCM_H__
|
||||
|
||||
#define CM_FCLKEN1_CORE (0x48004A00)
|
||||
#define CM_FCLKEN3_CORE (0x48004A08)
|
||||
#define CM_ICLKEN1_CORE (0x48004A10)
|
||||
#define CM_ICLKEN3_CORE (0x48004A18)
|
||||
#define CM_CLKEN2_PLL (0x48004D04)
|
||||
#define CM_CLKSEL4_PLL (0x48004D4C)
|
||||
#define CM_CLKSEL5_PLL (0x48004D50)
|
||||
#define CM_FCLKEN_USBHOST (0x48005400)
|
||||
#define CM_ICLKEN_USBHOST (0x48005410)
|
||||
|
||||
//Wakeup clock defintion
|
||||
#define CM_FCLKEN_WKUP (0x48004C00)
|
||||
#define CM_ICLKEN_WKUP (0x48004C10)
|
||||
|
||||
//Peripheral clock definition
|
||||
#define CM_FCLKEN_PER (0x48005000)
|
||||
#define CM_ICLKEN_PER (0x48005010)
|
||||
#define CM_CLKSEL_PER (0x48005040)
|
||||
|
||||
//Reset management definition
|
||||
#define PRM_RSTCTRL (0x48307250)
|
||||
#define PRM_RSTST (0x48307258)
|
||||
|
||||
//CORE clock
|
||||
#define CM_FCLKEN1_CORE_EN_I2C1_MASK (1UL << 15)
|
||||
#define CM_FCLKEN1_CORE_EN_I2C1_DISABLE (0UL << 15)
|
||||
#define CM_FCLKEN1_CORE_EN_I2C1_ENABLE (1UL << 15)
|
||||
|
||||
#define CM_ICLKEN1_CORE_EN_I2C1_MASK (1UL << 15)
|
||||
#define CM_ICLKEN1_CORE_EN_I2C1_DISABLE (0UL << 15)
|
||||
#define CM_ICLKEN1_CORE_EN_I2C1_ENABLE (1UL << 15)
|
||||
|
||||
#define CM_FCLKEN1_CORE_EN_MMC1_MASK (1UL << 24)
|
||||
#define CM_FCLKEN1_CORE_EN_MMC1_DISABLE (0UL << 24)
|
||||
#define CM_FCLKEN1_CORE_EN_MMC1_ENABLE (1UL << 24)
|
||||
|
||||
#define CM_FCLKEN3_CORE_EN_USBTLL_MASK (1UL << 2)
|
||||
#define CM_FCLKEN3_CORE_EN_USBTLL_DISABLE (0UL << 2)
|
||||
#define CM_FCLKEN3_CORE_EN_USBTLL_ENABLE (1UL << 2)
|
||||
|
||||
#define CM_ICLKEN1_CORE_EN_MMC1_MASK (1UL << 24)
|
||||
#define CM_ICLKEN1_CORE_EN_MMC1_DISABLE (0UL << 24)
|
||||
#define CM_ICLKEN1_CORE_EN_MMC1_ENABLE (1UL << 24)
|
||||
|
||||
#define CM_ICLKEN3_CORE_EN_USBTLL_MASK (1UL << 2)
|
||||
#define CM_ICLKEN3_CORE_EN_USBTLL_DISABLE (0UL << 2)
|
||||
#define CM_ICLKEN3_CORE_EN_USBTLL_ENABLE (1UL << 2)
|
||||
|
||||
#define CM_CLKEN_FREQSEL_075_100 (0x03UL << 4)
|
||||
#define CM_CLKEN_ENABLE (7UL << 0)
|
||||
|
||||
#define CM_CLKSEL_PLL_MULT(x) (((x) & 0x07FF) << 8)
|
||||
#define CM_CLKSEL_PLL_DIV(x) ((((x) - 1) & 0x7F) << 0)
|
||||
|
||||
#define CM_CLKSEL_DIV_120M(x) (((x) & 0x1F) << 0)
|
||||
|
||||
#define CM_FCLKEN_USBHOST_EN_USBHOST2_MASK (1UL << 1)
|
||||
#define CM_FCLKEN_USBHOST_EN_USBHOST2_DISABLE (0UL << 1)
|
||||
#define CM_FCLKEN_USBHOST_EN_USBHOST2_ENABLE (1UL << 1)
|
||||
|
||||
#define CM_FCLKEN_USBHOST_EN_USBHOST1_MASK (1UL << 0)
|
||||
#define CM_FCLKEN_USBHOST_EN_USBHOST1_DISABLE (0UL << 0)
|
||||
#define CM_FCLKEN_USBHOST_EN_USBHOST1_ENABLE (1UL << 0)
|
||||
|
||||
#define CM_ICLKEN_USBHOST_EN_USBHOST_MASK (1UL << 0)
|
||||
#define CM_ICLKEN_USBHOST_EN_USBHOST_DISABLE (0UL << 0)
|
||||
#define CM_ICLKEN_USBHOST_EN_USBHOST_ENABLE (1UL << 0)
|
||||
|
||||
//Wakeup functional clock
|
||||
#define CM_FCLKEN_WKUP_EN_GPIO1_DISABLE (0UL << 3)
|
||||
#define CM_FCLKEN_WKUP_EN_GPIO1_ENABLE (1UL << 3)
|
||||
|
||||
#define CM_FCLKEN_WKUP_EN_WDT2_DISABLE (0UL << 5)
|
||||
#define CM_FCLKEN_WKUP_EN_WDT2_ENABLE (1UL << 5)
|
||||
|
||||
//Wakeup interface clock
|
||||
#define CM_ICLKEN_WKUP_EN_GPIO1_DISABLE (0UL << 3)
|
||||
#define CM_ICLKEN_WKUP_EN_GPIO1_ENABLE (1UL << 3)
|
||||
|
||||
#define CM_ICLKEN_WKUP_EN_WDT2_DISABLE (0UL << 5)
|
||||
#define CM_ICLKEN_WKUP_EN_WDT2_ENABLE (1UL << 5)
|
||||
|
||||
//Peripheral functional clock
|
||||
#define CM_FCLKEN_PER_EN_GPT3_DISABLE (0UL << 4)
|
||||
#define CM_FCLKEN_PER_EN_GPT3_ENABLE (1UL << 4)
|
||||
|
||||
#define CM_FCLKEN_PER_EN_GPT4_DISABLE (0UL << 5)
|
||||
#define CM_FCLKEN_PER_EN_GPT4_ENABLE (1UL << 5)
|
||||
|
||||
#define CM_FCLKEN_PER_EN_UART3_DISABLE (0UL << 11)
|
||||
#define CM_FCLKEN_PER_EN_UART3_ENABLE (1UL << 11)
|
||||
|
||||
#define CM_FCLKEN_PER_EN_GPIO2_DISABLE (0UL << 13)
|
||||
#define CM_FCLKEN_PER_EN_GPIO2_ENABLE (1UL << 13)
|
||||
|
||||
#define CM_FCLKEN_PER_EN_GPIO3_DISABLE (0UL << 14)
|
||||
#define CM_FCLKEN_PER_EN_GPIO3_ENABLE (1UL << 14)
|
||||
|
||||
#define CM_FCLKEN_PER_EN_GPIO4_DISABLE (0UL << 15)
|
||||
#define CM_FCLKEN_PER_EN_GPIO4_ENABLE (1UL << 15)
|
||||
|
||||
#define CM_FCLKEN_PER_EN_GPIO5_DISABLE (0UL << 16)
|
||||
#define CM_FCLKEN_PER_EN_GPIO5_ENABLE (1UL << 16)
|
||||
|
||||
#define CM_FCLKEN_PER_EN_GPIO6_DISABLE (0UL << 17)
|
||||
#define CM_FCLKEN_PER_EN_GPIO6_ENABLE (1UL << 17)
|
||||
|
||||
//Peripheral interface clock
|
||||
#define CM_ICLKEN_PER_EN_GPT3_DISABLE (0UL << 4)
|
||||
#define CM_ICLKEN_PER_EN_GPT3_ENABLE (1UL << 4)
|
||||
|
||||
#define CM_ICLKEN_PER_EN_GPT4_DISABLE (0UL << 5)
|
||||
#define CM_ICLKEN_PER_EN_GPT4_ENABLE (1UL << 5)
|
||||
|
||||
#define CM_ICLKEN_PER_EN_UART3_DISABLE (0UL << 11)
|
||||
#define CM_ICLKEN_PER_EN_UART3_ENABLE (1UL << 11)
|
||||
|
||||
#define CM_ICLKEN_PER_EN_GPIO2_DISABLE (0UL << 13)
|
||||
#define CM_ICLKEN_PER_EN_GPIO2_ENABLE (1UL << 13)
|
||||
|
||||
#define CM_ICLKEN_PER_EN_GPIO3_DISABLE (0UL << 14)
|
||||
#define CM_ICLKEN_PER_EN_GPIO3_ENABLE (1UL << 14)
|
||||
|
||||
#define CM_ICLKEN_PER_EN_GPIO4_DISABLE (0UL << 15)
|
||||
#define CM_ICLKEN_PER_EN_GPIO4_ENABLE (1UL << 15)
|
||||
|
||||
#define CM_ICLKEN_PER_EN_GPIO5_DISABLE (0UL << 16)
|
||||
#define CM_ICLKEN_PER_EN_GPIO5_ENABLE (1UL << 16)
|
||||
|
||||
#define CM_ICLKEN_PER_EN_GPIO6_DISABLE (0UL << 17)
|
||||
#define CM_ICLKEN_PER_EN_GPIO6_ENABLE (1UL << 17)
|
||||
|
||||
//Timer source clock selection
|
||||
#define CM_CLKSEL_PER_CLKSEL_GPT3_32K (0UL << 1)
|
||||
#define CM_CLKSEL_PER_CLKSEL_GPT3_SYS (1UL << 1)
|
||||
|
||||
#define CM_CLKSEL_PER_CLKSEL_GPT4_32K (0UL << 2)
|
||||
#define CM_CLKSEL_PER_CLKSEL_GPT4_SYS (1UL << 2)
|
||||
|
||||
//Reset management (Global and Cold reset)
|
||||
#define RST_GS (0x1UL << 1)
|
||||
#define RST_DPLL3 (0x1UL << 2)
|
||||
#define GLOBAL_SW_RST (0x1UL << 1)
|
||||
#define GLOBAL_COLD_RST (0x0UL << 0)
|
||||
|
||||
#endif // __OMAP3530PRCM_H__
|
||||
|
||||
@ -1,82 +0,0 @@
|
||||
/** @file
|
||||
|
||||
Copyright (c) 2008-2009 Apple Inc. All rights reserved.<BR>
|
||||
|
||||
All rights reserved. This program and the accompanying materials
|
||||
are licensed and made available under the terms and conditions of the BSD License
|
||||
which accompanies this distribution. The full text of the license may be found at
|
||||
http://opensource.org/licenses/bsd-license.php
|
||||
|
||||
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
|
||||
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
|
||||
|
||||
**/
|
||||
|
||||
#ifndef __OMAP3530TIMER_H__
|
||||
#define __OMAP3530TIMER_H__
|
||||
|
||||
#define GPTIMER1_BASE (0x48313000)
|
||||
#define GPTIMER2_BASE (0x49032000)
|
||||
#define GPTIMER3_BASE (0x49034000)
|
||||
#define GPTIMER4_BASE (0x49036000)
|
||||
#define GPTIMER5_BASE (0x49038000)
|
||||
#define GPTIMER6_BASE (0x4903A000)
|
||||
#define GPTIMER7_BASE (0x4903C000)
|
||||
#define GPTIMER8_BASE (0x4903E000)
|
||||
#define GPTIMER9_BASE (0x49040000)
|
||||
#define GPTIMER10_BASE (0x48086000)
|
||||
#define GPTIMER11_BASE (0x48088000)
|
||||
#define GPTIMER12_BASE (0x48304000)
|
||||
#define WDTIMER2_BASE (0x48314000)
|
||||
|
||||
#define GPTIMER_TIOCP_CFG (0x0010)
|
||||
#define GPTIMER_TISTAT (0x0014)
|
||||
#define GPTIMER_TISR (0x0018)
|
||||
#define GPTIMER_TIER (0x001C)
|
||||
#define GPTIMER_TWER (0x0020)
|
||||
#define GPTIMER_TCLR (0x0024)
|
||||
#define GPTIMER_TCRR (0x0028)
|
||||
#define GPTIMER_TLDR (0x002C)
|
||||
#define GPTIMER_TTGR (0x0030)
|
||||
#define GPTIMER_TWPS (0x0034)
|
||||
#define GPTIMER_TMAR (0x0038)
|
||||
#define GPTIMER_TCAR1 (0x003C)
|
||||
#define GPTIMER_TSICR (0x0040)
|
||||
#define GPTIMER_TCAR2 (0x0044)
|
||||
#define GPTIMER_TPIR (0x0048)
|
||||
#define GPTIMER_TNIR (0x004C)
|
||||
#define GPTIMER_TCVR (0x0050)
|
||||
#define GPTIMER_TOCR (0x0054)
|
||||
#define GPTIMER_TOWR (0x0058)
|
||||
|
||||
#define WSPR (0x048)
|
||||
|
||||
#define TISR_TCAR_IT_FLAG_MASK (1UL << 2)
|
||||
#define TISR_OVF_IT_FLAG_MASK (1UL << 1)
|
||||
#define TISR_MAT_IT_FLAG_MASK (1UL << 0)
|
||||
#define TISR_ALL_INTERRUPT_MASK (TISR_TCAR_IT_FLAG_MASK | TISR_OVF_IT_FLAG_MASK | TISR_MAT_IT_FLAG_MASK)
|
||||
|
||||
#define TISR_TCAR_IT_FLAG_NOT_PENDING (0UL << 2)
|
||||
#define TISR_OVF_IT_FLAG_NOT_PENDING (0UL << 1)
|
||||
#define TISR_MAT_IT_FLAG_NOT_PENDING (0UL << 0)
|
||||
#define TISR_NO_INTERRUPTS_PENDING (TISR_TCAR_IT_FLAG_NOT_PENDING | TISR_OVF_IT_FLAG_NOT_PENDING | TISR_MAT_IT_FLAG_NOT_PENDING)
|
||||
|
||||
#define TISR_TCAR_IT_FLAG_CLEAR (1UL << 2)
|
||||
#define TISR_OVF_IT_FLAG_CLEAR (1UL << 1)
|
||||
#define TISR_MAT_IT_FLAG_CLEAR (1UL << 0)
|
||||
#define TISR_CLEAR_ALL (TISR_TCAR_IT_FLAG_CLEAR | TISR_OVF_IT_FLAG_CLEAR | TISR_MAT_IT_FLAG_CLEAR)
|
||||
|
||||
#define TCLR_AR_AUTORELOAD (1UL << 1)
|
||||
#define TCLR_AR_ONESHOT (0UL << 1)
|
||||
#define TCLR_ST_ON (1UL << 0)
|
||||
#define TCLR_ST_OFF (0UL << 0)
|
||||
|
||||
#define TIER_TCAR_IT_ENABLE (1UL << 2)
|
||||
#define TIER_TCAR_IT_DISABLE (0UL << 2)
|
||||
#define TIER_OVF_IT_ENABLE (1UL << 1)
|
||||
#define TIER_OVF_IT_DISABLE (0UL << 1)
|
||||
#define TIER_MAT_IT_ENABLE (1UL << 0)
|
||||
#define TIER_MAT_IT_DISABLE (0UL << 0)
|
||||
|
||||
#endif // __OMAP3530TIMER_H__
|
||||
|
||||
@ -1,53 +0,0 @@
|
||||
/** @file
|
||||
|
||||
Copyright (c) 2008-2009 Apple Inc. All rights reserved.<BR>
|
||||
|
||||
All rights reserved. This program and the accompanying materials
|
||||
are licensed and made available under the terms and conditions of the BSD License
|
||||
which accompanies this distribution. The full text of the license may be found at
|
||||
http://opensource.org/licenses/bsd-license.php
|
||||
|
||||
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
|
||||
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
|
||||
|
||||
**/
|
||||
|
||||
#ifndef __OMAP3530UART_H__
|
||||
#define __OMAP3530UART_H__
|
||||
|
||||
#define UART1_BASE (0x4806A000)
|
||||
#define UART2_BASE (0x4806C000)
|
||||
#define UART3_BASE (0x49020000)
|
||||
|
||||
#define UART_DLL_REG (0x0000)
|
||||
#define UART_RBR_REG (0x0000)
|
||||
#define UART_THR_REG (0x0000)
|
||||
#define UART_DLH_REG (0x0004)
|
||||
#define UART_FCR_REG (0x0008)
|
||||
#define UART_LCR_REG (0x000C)
|
||||
#define UART_MCR_REG (0x0010)
|
||||
#define UART_LSR_REG (0x0014)
|
||||
#define UART_MDR1_REG (0x0020)
|
||||
|
||||
#define UART_FCR_TX_FIFO_CLEAR (1UL << 3)
|
||||
#define UART_FCR_RX_FIFO_CLEAR (1UL << 3)
|
||||
#define UART_FCR_FIFO_ENABLE (1UL << 3)
|
||||
|
||||
#define UART_LCR_DIV_EN_ENABLE (1UL << 7)
|
||||
#define UART_LCR_DIV_EN_DISABLE (0UL << 7)
|
||||
#define UART_LCR_CHAR_LENGTH_8 (3UL << 0)
|
||||
|
||||
#define UART_MCR_RTS_FORCE_ACTIVE (1UL << 1)
|
||||
#define UART_MCR_DTR_FORCE_ACTIVE (1UL << 0)
|
||||
|
||||
#define UART_LSR_TX_FIFO_E_MASK (1UL << 5)
|
||||
#define UART_LSR_TX_FIFO_E_NOT_EMPTY (0UL << 5)
|
||||
#define UART_LSR_TX_FIFO_E_EMPTY (1UL << 5)
|
||||
#define UART_LSR_RX_FIFO_E_MASK (1UL << 0)
|
||||
#define UART_LSR_RX_FIFO_E_NOT_EMPTY (1UL << 0)
|
||||
#define UART_LSR_RX_FIFO_E_EMPTY (0UL << 0)
|
||||
|
||||
#define UART_MDR1_MODE_SELECT_DISABLE (7UL << 0)
|
||||
#define UART_MDR1_MODE_SELECT_UART_16X (0UL << 0)
|
||||
|
||||
#endif // __OMAP3530UART_H__
|
||||
@ -1,42 +0,0 @@
|
||||
/** @file
|
||||
|
||||
Copyright (c) 2008-2009 Apple Inc. All rights reserved.<BR>
|
||||
|
||||
All rights reserved. This program and the accompanying materials
|
||||
are licensed and made available under the terms and conditions of the BSD License
|
||||
which accompanies this distribution. The full text of the license may be found at
|
||||
http://opensource.org/licenses/bsd-license.php
|
||||
|
||||
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
|
||||
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
|
||||
|
||||
**/
|
||||
|
||||
#ifndef __OMAP3530USB_H__
|
||||
#define __OMAP3530USB_H__
|
||||
|
||||
#define USB_BASE (0x48060000)
|
||||
|
||||
#define UHH_SYSCONFIG (USB_BASE + 0x4010)
|
||||
#define UHH_HOSTCONFIG (USB_BASE + 0x4040)
|
||||
|
||||
#define USB_EHCI_HCCAPBASE (USB_BASE + 0x4800)
|
||||
|
||||
#define UHH_SYSCONFIG_MIDLEMODE_NO_STANDBY (1UL << 12)
|
||||
#define UHH_SYSCONFIG_CLOCKACTIVITY_ON (1UL << 8)
|
||||
#define UHH_SYSCONFIG_SIDLEMODE_NO_STANDBY (1UL << 3)
|
||||
#define UHH_SYSCONFIG_ENAWAKEUP_ENABLE (1UL << 2)
|
||||
#define UHH_SYSCONFIG_AUTOIDLE_ALWAYS_RUN (0UL << 0)
|
||||
|
||||
#define UHH_HOSTCONFIG_P3_CONNECT_STATUS_DISCONNECT (0UL << 10)
|
||||
#define UHH_HOSTCONFIG_P2_CONNECT_STATUS_DISCONNECT (0UL << 9)
|
||||
#define UHH_HOSTCONFIG_P1_CONNECT_STATUS_DISCONNECT (0UL << 8)
|
||||
#define UHH_HOSTCONFIG_ENA_INCR_ALIGN_DISABLE (0UL << 5)
|
||||
#define UHH_HOSTCONFIG_ENA_INCR16_ENABLE (1UL << 4)
|
||||
#define UHH_HOSTCONFIG_ENA_INCR8_ENABLE (1UL << 3)
|
||||
#define UHH_HOSTCONFIG_ENA_INCR4_ENABLE (1UL << 2)
|
||||
#define UHH_HOSTCONFIG_AUTOPPD_ON_OVERCUR_EN_ON (0UL << 1)
|
||||
#define UHH_HOSTCONFIG_P1_ULPI_BYPASS_ULPI_MODE (0UL << 0)
|
||||
|
||||
#endif // __OMAP3530USB_H__
|
||||
|
||||
@ -1,46 +0,0 @@
|
||||
/** @file
|
||||
|
||||
Copyright (c) 2008-2009 Apple Inc. All rights reserved.<BR>
|
||||
|
||||
All rights reserved. This program and the accompanying materials
|
||||
are licensed and made available under the terms and conditions of the BSD License
|
||||
which accompanies this distribution. The full text of the license may be found at
|
||||
http://opensource.org/licenses/bsd-license.php
|
||||
|
||||
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
|
||||
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
|
||||
|
||||
**/
|
||||
|
||||
#ifndef __TPS65950_H__
|
||||
#define __TPS65950_H__
|
||||
|
||||
#define EXTERNAL_DEVICE_REGISTER_TO_SLAVE_ADDRESS(x) (((x) >> 8) & 0xFF)
|
||||
#define EXTERNAL_DEVICE_REGISTER_TO_REGISTER(x) ((x) & 0xFF)
|
||||
#define EXTERNAL_DEVICE_REGISTER(SlaveAddress, Register) (((SlaveAddress) & 0xFF) << 8 | ((Register) & 0xFF))
|
||||
|
||||
//I2C Address group
|
||||
#define I2C_ADDR_GRP_ID1 0x48
|
||||
#define I2C_ADDR_GRP_ID2 0x49
|
||||
#define I2C_ADDR_GRP_ID3 0x4A
|
||||
#define I2C_ADDR_GRP_ID4 0x4B
|
||||
#define I2C_ADDR_GRP_ID5 0x12
|
||||
|
||||
//MMC definitions.
|
||||
#define VMMC1_DEV_GRP 0x82
|
||||
#define DEV_GRP_P1 (0x01UL << 5)
|
||||
|
||||
#define VMMC1_DEDICATED_REG 0x85
|
||||
#define VSEL_1_85V 0x0
|
||||
#define VSEL_2_85V 0x1
|
||||
#define VSEL_3_00V 0x2
|
||||
#define VSEL_3_15V 0x3
|
||||
|
||||
//LEDEN register
|
||||
#define LEDEN 0xEE
|
||||
#define LEDAON (0x1UL << 0)
|
||||
#define LEDBON (0x1UL << 1)
|
||||
#define LEDAPWM (0x1UL << 4)
|
||||
#define LEDBPWM (0x1UL << 5)
|
||||
|
||||
#endif //__TPS65950_H__
|
||||
@ -1,342 +0,0 @@
|
||||
/** @file
|
||||
Template for Metronome Architecture Protocol driver of the ARM flavor
|
||||
|
||||
Copyright (c) 2008-2009, Apple Inc. All rights reserved.
|
||||
|
||||
All rights reserved. This program and the accompanying materials
|
||||
are licensed and made available under the terms and conditions of the BSD License
|
||||
which accompanies this distribution. The full text of the license may be found at
|
||||
http://opensource.org/licenses/bsd-license.php
|
||||
|
||||
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
|
||||
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
|
||||
|
||||
**/
|
||||
#include <PiDxe.h>
|
||||
|
||||
#include <Library/BaseLib.h>
|
||||
#include <Library/DebugLib.h>
|
||||
#include <Library/BaseMemoryLib.h>
|
||||
#include <Library/UefiBootServicesTableLib.h>
|
||||
#include <Library/UefiLib.h>
|
||||
#include <Library/PcdLib.h>
|
||||
#include <Library/IoLib.h>
|
||||
|
||||
#include <Protocol/Cpu.h>
|
||||
#include <Protocol/HardwareInterrupt.h>
|
||||
|
||||
#include <Omap3530/Omap3530.h>
|
||||
|
||||
//
|
||||
// Notifications
|
||||
//
|
||||
VOID *CpuProtocolNotificationToken = NULL;
|
||||
EFI_EVENT CpuProtocolNotificationEvent = (EFI_EVENT)NULL;
|
||||
EFI_EVENT EfiExitBootServicesEvent = (EFI_EVENT)NULL;
|
||||
|
||||
|
||||
HARDWARE_INTERRUPT_HANDLER gRegisteredInterruptHandlers[INT_NROF_VECTORS];
|
||||
|
||||
/**
|
||||
Shutdown our hardware
|
||||
|
||||
DXE Core will disable interrupts and turn off the timer and disable interrupts
|
||||
after all the event handlers have run.
|
||||
|
||||
@param[in] Event The Event that is being processed
|
||||
@param[in] Context Event Context
|
||||
**/
|
||||
VOID
|
||||
EFIAPI
|
||||
ExitBootServicesEvent (
|
||||
IN EFI_EVENT Event,
|
||||
IN VOID *Context
|
||||
)
|
||||
{
|
||||
// Disable all interrupts
|
||||
MmioWrite32(INTCPS_MIR(0), 0xFFFFFFFF);
|
||||
MmioWrite32(INTCPS_MIR(1), 0xFFFFFFFF);
|
||||
MmioWrite32(INTCPS_MIR(2), 0xFFFFFFFF);
|
||||
MmioWrite32(INTCPS_CONTROL, INTCPS_CONTROL_NEWIRQAGR);
|
||||
}
|
||||
|
||||
/**
|
||||
Register Handler for the specified interrupt source.
|
||||
|
||||
@param This Instance pointer for this protocol
|
||||
@param Source Hardware source of the interrupt
|
||||
@param Handler Callback for interrupt. NULL to unregister
|
||||
|
||||
@retval EFI_SUCCESS Source was updated to support Handler.
|
||||
@retval EFI_DEVICE_ERROR Hardware could not be programmed.
|
||||
|
||||
**/
|
||||
EFI_STATUS
|
||||
EFIAPI
|
||||
RegisterInterruptSource (
|
||||
IN EFI_HARDWARE_INTERRUPT_PROTOCOL *This,
|
||||
IN HARDWARE_INTERRUPT_SOURCE Source,
|
||||
IN HARDWARE_INTERRUPT_HANDLER Handler
|
||||
)
|
||||
{
|
||||
if (Source > MAX_VECTOR) {
|
||||
ASSERT(FALSE);
|
||||
return EFI_UNSUPPORTED;
|
||||
}
|
||||
|
||||
if ((Handler == NULL) && (gRegisteredInterruptHandlers[Source] == NULL)) {
|
||||
return EFI_INVALID_PARAMETER;
|
||||
}
|
||||
|
||||
if ((Handler != NULL) && (gRegisteredInterruptHandlers[Source] != NULL)) {
|
||||
return EFI_ALREADY_STARTED;
|
||||
}
|
||||
|
||||
gRegisteredInterruptHandlers[Source] = Handler;
|
||||
return This->EnableInterruptSource(This, Source);
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
Enable interrupt source Source.
|
||||
|
||||
@param This Instance pointer for this protocol
|
||||
@param Source Hardware source of the interrupt
|
||||
|
||||
@retval EFI_SUCCESS Source interrupt enabled.
|
||||
@retval EFI_DEVICE_ERROR Hardware could not be programmed.
|
||||
|
||||
**/
|
||||
EFI_STATUS
|
||||
EFIAPI
|
||||
EnableInterruptSource (
|
||||
IN EFI_HARDWARE_INTERRUPT_PROTOCOL *This,
|
||||
IN HARDWARE_INTERRUPT_SOURCE Source
|
||||
)
|
||||
{
|
||||
UINTN Bank;
|
||||
UINTN Bit;
|
||||
|
||||
if (Source > MAX_VECTOR) {
|
||||
ASSERT(FALSE);
|
||||
return EFI_UNSUPPORTED;
|
||||
}
|
||||
|
||||
Bank = Source / 32;
|
||||
Bit = 1UL << (Source % 32);
|
||||
|
||||
MmioWrite32(INTCPS_MIR_CLEAR(Bank), Bit);
|
||||
|
||||
return EFI_SUCCESS;
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
Disable interrupt source Source.
|
||||
|
||||
@param This Instance pointer for this protocol
|
||||
@param Source Hardware source of the interrupt
|
||||
|
||||
@retval EFI_SUCCESS Source interrupt disabled.
|
||||
@retval EFI_DEVICE_ERROR Hardware could not be programmed.
|
||||
|
||||
**/
|
||||
EFI_STATUS
|
||||
EFIAPI
|
||||
DisableInterruptSource(
|
||||
IN EFI_HARDWARE_INTERRUPT_PROTOCOL *This,
|
||||
IN HARDWARE_INTERRUPT_SOURCE Source
|
||||
)
|
||||
{
|
||||
UINTN Bank;
|
||||
UINTN Bit;
|
||||
|
||||
if (Source > MAX_VECTOR) {
|
||||
ASSERT(FALSE);
|
||||
return EFI_UNSUPPORTED;
|
||||
}
|
||||
|
||||
Bank = Source / 32;
|
||||
Bit = 1UL << (Source % 32);
|
||||
|
||||
MmioWrite32(INTCPS_MIR_SET(Bank), Bit);
|
||||
|
||||
return EFI_SUCCESS;
|
||||
}
|
||||
|
||||
|
||||
|
||||
/**
|
||||
Return current state of interrupt source Source.
|
||||
|
||||
@param This Instance pointer for this protocol
|
||||
@param Source Hardware source of the interrupt
|
||||
@param InterruptState TRUE: source enabled, FALSE: source disabled.
|
||||
|
||||
@retval EFI_SUCCESS InterruptState is valid
|
||||
@retval EFI_DEVICE_ERROR InterruptState is not valid
|
||||
|
||||
**/
|
||||
EFI_STATUS
|
||||
EFIAPI
|
||||
GetInterruptSourceState (
|
||||
IN EFI_HARDWARE_INTERRUPT_PROTOCOL *This,
|
||||
IN HARDWARE_INTERRUPT_SOURCE Source,
|
||||
IN BOOLEAN *InterruptState
|
||||
)
|
||||
{
|
||||
UINTN Bank;
|
||||
UINTN Bit;
|
||||
|
||||
if (InterruptState == NULL) {
|
||||
return EFI_INVALID_PARAMETER;
|
||||
}
|
||||
|
||||
if (Source > MAX_VECTOR) {
|
||||
ASSERT(FALSE);
|
||||
return EFI_UNSUPPORTED;
|
||||
}
|
||||
|
||||
Bank = Source / 32;
|
||||
Bit = 1UL << (Source % 32);
|
||||
|
||||
if ((MmioRead32(INTCPS_MIR(Bank)) & Bit) == Bit) {
|
||||
*InterruptState = FALSE;
|
||||
} else {
|
||||
*InterruptState = TRUE;
|
||||
}
|
||||
|
||||
return EFI_SUCCESS;
|
||||
}
|
||||
|
||||
|
||||
|
||||
/**
|
||||
EFI_CPU_INTERRUPT_HANDLER that is called when a processor interrupt occurs.
|
||||
|
||||
@param InterruptType Defines the type of interrupt or exception that
|
||||
occurred on the processor.This parameter is processor architecture specific.
|
||||
@param SystemContext A pointer to the processor context when
|
||||
the interrupt occurred on the processor.
|
||||
|
||||
@return None
|
||||
|
||||
**/
|
||||
VOID
|
||||
EFIAPI
|
||||
IrqInterruptHandler (
|
||||
IN EFI_EXCEPTION_TYPE InterruptType,
|
||||
IN EFI_SYSTEM_CONTEXT SystemContext
|
||||
)
|
||||
{
|
||||
UINT32 Vector;
|
||||
HARDWARE_INTERRUPT_HANDLER InterruptHandler;
|
||||
|
||||
Vector = MmioRead32(INTCPS_SIR_IRQ) & INTCPS_SIR_IRQ_MASK;
|
||||
|
||||
// Needed to prevent infinite nesting when Time Driver lowers TPL
|
||||
MmioWrite32(INTCPS_CONTROL, INTCPS_CONTROL_NEWIRQAGR);
|
||||
|
||||
InterruptHandler = gRegisteredInterruptHandlers[Vector];
|
||||
if (InterruptHandler != NULL) {
|
||||
// Call the registered interrupt handler.
|
||||
InterruptHandler(Vector, SystemContext);
|
||||
}
|
||||
|
||||
// Needed to clear after running the handler
|
||||
MmioWrite32(INTCPS_CONTROL, INTCPS_CONTROL_NEWIRQAGR);
|
||||
}
|
||||
|
||||
//
|
||||
// Making this global saves a few bytes in image size
|
||||
//
|
||||
EFI_HANDLE gHardwareInterruptHandle = NULL;
|
||||
|
||||
//
|
||||
// The protocol instance produced by this driver
|
||||
//
|
||||
EFI_HARDWARE_INTERRUPT_PROTOCOL gHardwareInterruptProtocol = {
|
||||
RegisterInterruptSource,
|
||||
EnableInterruptSource,
|
||||
DisableInterruptSource,
|
||||
GetInterruptSourceState
|
||||
};
|
||||
|
||||
//
|
||||
// Notification routines
|
||||
//
|
||||
VOID
|
||||
CpuProtocolInstalledNotification (
|
||||
IN EFI_EVENT Event,
|
||||
IN VOID *Context
|
||||
)
|
||||
{
|
||||
EFI_STATUS Status;
|
||||
EFI_CPU_ARCH_PROTOCOL *Cpu;
|
||||
|
||||
//
|
||||
// Get the cpu protocol that this driver requires.
|
||||
//
|
||||
Status = gBS->LocateProtocol(&gEfiCpuArchProtocolGuid, NULL, (VOID **)&Cpu);
|
||||
ASSERT_EFI_ERROR(Status);
|
||||
|
||||
//
|
||||
// Unregister the default exception handler.
|
||||
//
|
||||
Status = Cpu->RegisterInterruptHandler(Cpu, EXCEPT_ARM_IRQ, NULL);
|
||||
ASSERT_EFI_ERROR(Status);
|
||||
|
||||
//
|
||||
// Register to receive interrupts
|
||||
//
|
||||
Status = Cpu->RegisterInterruptHandler(Cpu, EXCEPT_ARM_IRQ, IrqInterruptHandler);
|
||||
ASSERT_EFI_ERROR(Status);
|
||||
}
|
||||
|
||||
/**
|
||||
Initialize the state information for the CPU Architectural Protocol
|
||||
|
||||
@param ImageHandle of the loaded driver
|
||||
@param SystemTable Pointer to the System Table
|
||||
|
||||
@retval EFI_SUCCESS Protocol registered
|
||||
@retval EFI_OUT_OF_RESOURCES Cannot allocate protocol data structure
|
||||
@retval EFI_DEVICE_ERROR Hardware problems
|
||||
|
||||
**/
|
||||
EFI_STATUS
|
||||
InterruptDxeInitialize (
|
||||
IN EFI_HANDLE ImageHandle,
|
||||
IN EFI_SYSTEM_TABLE *SystemTable
|
||||
)
|
||||
{
|
||||
EFI_STATUS Status;
|
||||
|
||||
// Make sure the Interrupt Controller Protocol is not already installed in the system.
|
||||
ASSERT_PROTOCOL_ALREADY_INSTALLED (NULL, &gHardwareInterruptProtocolGuid);
|
||||
|
||||
// Make sure all interrupts are disabled by default.
|
||||
MmioWrite32(INTCPS_MIR(0), 0xFFFFFFFF);
|
||||
MmioWrite32(INTCPS_MIR(1), 0xFFFFFFFF);
|
||||
MmioWrite32(INTCPS_MIR(2), 0xFFFFFFFF);
|
||||
MmioWrite32(INTCPS_CONTROL, INTCPS_CONTROL_NEWIRQAGR);
|
||||
|
||||
Status = gBS->InstallMultipleProtocolInterfaces(&gHardwareInterruptHandle,
|
||||
&gHardwareInterruptProtocolGuid, &gHardwareInterruptProtocol,
|
||||
NULL);
|
||||
ASSERT_EFI_ERROR(Status);
|
||||
|
||||
// Set up to be notified when the Cpu protocol is installed.
|
||||
Status = gBS->CreateEvent(EVT_NOTIFY_SIGNAL, TPL_CALLBACK, CpuProtocolInstalledNotification, NULL, &CpuProtocolNotificationEvent);
|
||||
ASSERT_EFI_ERROR(Status);
|
||||
|
||||
Status = gBS->RegisterProtocolNotify(&gEfiCpuArchProtocolGuid, CpuProtocolNotificationEvent, (VOID *)&CpuProtocolNotificationToken);
|
||||
ASSERT_EFI_ERROR(Status);
|
||||
|
||||
// Register for an ExitBootServicesEvent
|
||||
Status = gBS->CreateEvent(EVT_SIGNAL_EXIT_BOOT_SERVICES, TPL_NOTIFY, ExitBootServicesEvent, NULL, &EfiExitBootServicesEvent);
|
||||
ASSERT_EFI_ERROR(Status);
|
||||
|
||||
return Status;
|
||||
}
|
||||
|
||||
@ -1,68 +0,0 @@
|
||||
#/** @file
|
||||
#
|
||||
# Copyright (c) 2008 - 2010, Apple Inc. All rights reserved.
|
||||
# All rights reserved. This program and the accompanying materials
|
||||
# are licensed and made available under the terms and conditions of the BSD License
|
||||
# which accompanies this distribution. The full text of the license may be found at
|
||||
# http://opensource.org/licenses/bsd-license.php
|
||||
#
|
||||
# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
|
||||
# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
|
||||
#
|
||||
#**/
|
||||
|
||||
#/** @file
|
||||
#
|
||||
# Interrupt DXE driver
|
||||
#
|
||||
# Copyright (c) 2009, Apple, Inc <BR>
|
||||
# All rights reserved. This program and the accompanying materials
|
||||
# are licensed and made available under the terms and conditions of the BSD License
|
||||
# which accompanies this distribution. The full text of the license may be found at
|
||||
# http://opensource.org/licenses/bsd-license.php
|
||||
#
|
||||
# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
|
||||
# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
|
||||
#
|
||||
#**/
|
||||
|
||||
[Defines]
|
||||
INF_VERSION = 0x00010005
|
||||
BASE_NAME = BeagleBoardInterruptDxe
|
||||
FILE_GUID = 23eed05d-1b93-4a1a-8e1b-931d69e37952
|
||||
MODULE_TYPE = DXE_DRIVER
|
||||
VERSION_STRING = 1.0
|
||||
|
||||
ENTRY_POINT = InterruptDxeInitialize
|
||||
|
||||
|
||||
[Sources.common]
|
||||
HardwareInterrupt.c
|
||||
|
||||
|
||||
[Packages]
|
||||
BeagleBoardPkg/BeagleBoardPkg.dec
|
||||
MdePkg/MdePkg.dec
|
||||
EmbeddedPkg/EmbeddedPkg.dec
|
||||
|
||||
[LibraryClasses]
|
||||
BaseLib
|
||||
UefiLib
|
||||
UefiBootServicesTableLib
|
||||
DebugLib
|
||||
PrintLib
|
||||
UefiDriverEntryPoint
|
||||
IoLib
|
||||
|
||||
[Guids]
|
||||
|
||||
|
||||
[Protocols]
|
||||
gHardwareInterruptProtocolGuid
|
||||
gEfiCpuArchProtocolGuid
|
||||
|
||||
[FixedPcd.common]
|
||||
gEmbeddedTokenSpaceGuid.PcdInterruptBaseAddress
|
||||
|
||||
[depex]
|
||||
TRUE
|
||||
@ -30,6 +30,7 @@
|
||||
MdePkg/MdePkg.dec
|
||||
EmbeddedPkg/EmbeddedPkg.dec
|
||||
ArmPkg/ArmPkg.dec
|
||||
Omap35xxPkg/Omap35xxPkg.dec
|
||||
BeagleBoardPkg/BeagleBoardPkg.dec
|
||||
|
||||
[LibraryClasses]
|
||||
|
||||
@ -1,45 +0,0 @@
|
||||
#/** @file
|
||||
# Timer library implementation
|
||||
#
|
||||
# A non-functional instance of the Timer Library that can be used as a template
|
||||
# for the implementation of a functional timer library instance. This library instance can
|
||||
# also be used to test build DXE, Runtime, DXE SAL, and DXE SMM modules that require timer
|
||||
# services as well as EBC modules that require timer services
|
||||
# Copyright (c) 2007, Intel Corporation.
|
||||
#
|
||||
# All rights reserved. This program and the accompanying materials
|
||||
# are licensed and made available under the terms and conditions of the BSD License
|
||||
# which accompanies this distribution. The full text of the license may be found at
|
||||
# http://opensource.org/licenses/bsd-license.php
|
||||
# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
|
||||
# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
|
||||
#
|
||||
#
|
||||
#**/
|
||||
|
||||
[Defines]
|
||||
INF_VERSION = 0x00010005
|
||||
BASE_NAME = BeagleBoardTimerLib
|
||||
FILE_GUID = fe1d7183-9abb-42ce-9a3b-36d7c6a8959f
|
||||
MODULE_TYPE = BASE
|
||||
VERSION_STRING = 1.0
|
||||
LIBRARY_CLASS = TimerLib
|
||||
|
||||
[Sources.common]
|
||||
TimerLib.c
|
||||
|
||||
[Packages]
|
||||
BeagleBoardPkg/BeagleBoardPkg.dec
|
||||
MdePkg/MdePkg.dec
|
||||
EmbeddedPkg/EmbeddedPkg.dec
|
||||
|
||||
[LibraryClasses]
|
||||
DebugLib
|
||||
OmapLib
|
||||
IoLib
|
||||
|
||||
[Pcd]
|
||||
gEmbeddedTokenSpaceGuid.PcdEmbeddedPerformanceCounterFreqencyInHz
|
||||
gEmbeddedTokenSpaceGuid.PcdEmbeddedFdPerformanceCounterPeriodInNanoseconds
|
||||
gBeagleBoardTokenSpaceGuid.PcdBeagleFreeTimer
|
||||
|
||||
@ -1,102 +0,0 @@
|
||||
/** @file
|
||||
|
||||
Copyright (c) 2008-2009, Apple Inc. All rights reserved.
|
||||
|
||||
All rights reserved. This program and the accompanying materials
|
||||
are licensed and made available under the terms and conditions of the BSD License
|
||||
which accompanies this distribution. The full text of the license may be found at
|
||||
http://opensource.org/licenses/bsd-license.php
|
||||
|
||||
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
|
||||
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
|
||||
|
||||
**/
|
||||
|
||||
#include <Base.h>
|
||||
|
||||
#include <Library/BaseLib.h>
|
||||
#include <Library/TimerLib.h>
|
||||
#include <Library/DebugLib.h>
|
||||
#include <Library/PcdLib.h>
|
||||
#include <Library/IoLib.h>
|
||||
#include <Library/OmapLib.h>
|
||||
|
||||
#include <Omap3530/Omap3530.h>
|
||||
|
||||
UINTN
|
||||
EFIAPI
|
||||
MicroSecondDelay (
|
||||
IN UINTN MicroSeconds
|
||||
)
|
||||
{
|
||||
UINT64 NanoSeconds;
|
||||
|
||||
NanoSeconds = MultU64x32(MicroSeconds, 1000);
|
||||
|
||||
while (NanoSeconds > (UINTN)-1) {
|
||||
NanoSecondDelay((UINTN)-1);
|
||||
NanoSeconds -= (UINTN)-1;
|
||||
}
|
||||
|
||||
NanoSecondDelay(NanoSeconds);
|
||||
|
||||
return MicroSeconds;
|
||||
}
|
||||
|
||||
UINTN
|
||||
EFIAPI
|
||||
NanoSecondDelay (
|
||||
IN UINTN NanoSeconds
|
||||
)
|
||||
{
|
||||
UINT32 Delay;
|
||||
UINT32 StartTime;
|
||||
UINT32 CurrentTime;
|
||||
UINT32 ElapsedTime;
|
||||
UINT32 TimerCountRegister;
|
||||
|
||||
Delay = (NanoSeconds / PcdGet32(PcdEmbeddedFdPerformanceCounterPeriodInNanoseconds)) + 1;
|
||||
|
||||
TimerCountRegister = TimerBase(PcdGet32(PcdBeagleFreeTimer)) + GPTIMER_TCRR;
|
||||
|
||||
StartTime = MmioRead32(TimerCountRegister);
|
||||
|
||||
do
|
||||
{
|
||||
CurrentTime = MmioRead32(TimerCountRegister);
|
||||
ElapsedTime = CurrentTime - StartTime;
|
||||
} while (ElapsedTime < Delay);
|
||||
|
||||
NanoSeconds = ElapsedTime * PcdGet32(PcdEmbeddedFdPerformanceCounterPeriodInNanoseconds);
|
||||
|
||||
return NanoSeconds;
|
||||
}
|
||||
|
||||
UINT64
|
||||
EFIAPI
|
||||
GetPerformanceCounter (
|
||||
VOID
|
||||
)
|
||||
{
|
||||
return (UINT64)MmioRead32(TimerBase(PcdGet32(PcdBeagleFreeTimer)) + GPTIMER_TCRR);
|
||||
}
|
||||
|
||||
UINT64
|
||||
EFIAPI
|
||||
GetPerformanceCounterProperties (
|
||||
OUT UINT64 *StartValue, OPTIONAL
|
||||
OUT UINT64 *EndValue OPTIONAL
|
||||
)
|
||||
{
|
||||
if (StartValue != NULL) {
|
||||
// Timer starts with the reload value
|
||||
*StartValue = (UINT64)MmioRead32(TimerBase(PcdGet32(PcdBeagleFreeTimer)) + GPTIMER_TLDR);
|
||||
}
|
||||
|
||||
if (EndValue != NULL) {
|
||||
// Timer counts up to 0xFFFFFFFF
|
||||
*EndValue = 0xFFFFFFFF;
|
||||
}
|
||||
|
||||
return PcdGet64(PcdEmbeddedPerformanceCounterFreqencyInHz);
|
||||
}
|
||||
@ -29,7 +29,7 @@
|
||||
[Packages]
|
||||
MdePkg/MdePkg.dec
|
||||
EmbeddedPkg/EmbeddedPkg.dec
|
||||
BeagleBoardPkg/BeagleBoardPkg.dec
|
||||
Omap35xxPkg/Omap35xxPkg.dec
|
||||
|
||||
[LibraryClasses]
|
||||
DebugLib
|
||||
@ -37,5 +37,5 @@
|
||||
OmapLib
|
||||
|
||||
[FixedPcd]
|
||||
gBeagleBoardTokenSpaceGuid.PcdBeagleConsoleUart
|
||||
gOmap35xxTokenSpaceGuid.PcdBeagleConsoleUart
|
||||
|
||||
|
||||
@ -1,83 +0,0 @@
|
||||
/** @file
|
||||
|
||||
Copyright (c) 2008-2009, Apple Inc. All rights reserved.
|
||||
|
||||
All rights reserved. This program and the accompanying materials
|
||||
are licensed and made available under the terms and conditions of the BSD License
|
||||
which accompanies this distribution. The full text of the license may be found at
|
||||
http://opensource.org/licenses/bsd-license.php
|
||||
|
||||
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
|
||||
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
|
||||
|
||||
**/
|
||||
|
||||
#include <Base.h>
|
||||
#include <Library/DebugLib.h>
|
||||
#include <Library/OmapLib.h>
|
||||
#include <Omap3530/Omap3530.h>
|
||||
|
||||
UINT32
|
||||
GpioBase (
|
||||
IN UINTN Port
|
||||
)
|
||||
{
|
||||
switch (Port) {
|
||||
case 1: return GPIO1_BASE;
|
||||
case 2: return GPIO2_BASE;
|
||||
case 3: return GPIO3_BASE;
|
||||
case 4: return GPIO4_BASE;
|
||||
case 5: return GPIO5_BASE;
|
||||
case 6: return GPIO6_BASE;
|
||||
default: ASSERT(FALSE); return 0;
|
||||
}
|
||||
}
|
||||
|
||||
UINT32
|
||||
TimerBase (
|
||||
IN UINTN Timer
|
||||
)
|
||||
{
|
||||
switch (Timer) {
|
||||
case 1: return GPTIMER1_BASE;
|
||||
case 2: return GPTIMER2_BASE;
|
||||
case 3: return GPTIMER3_BASE;
|
||||
case 4: return GPTIMER4_BASE;
|
||||
case 5: return GPTIMER5_BASE;
|
||||
case 6: return GPTIMER6_BASE;
|
||||
case 7: return GPTIMER7_BASE;
|
||||
case 8: return GPTIMER8_BASE;
|
||||
case 9: return GPTIMER9_BASE;
|
||||
case 10: return GPTIMER10_BASE;
|
||||
case 11: return GPTIMER11_BASE;
|
||||
case 12: return GPTIMER12_BASE;
|
||||
default: return 0;
|
||||
}
|
||||
}
|
||||
|
||||
UINTN
|
||||
InterruptVectorForTimer (
|
||||
IN UINTN Timer
|
||||
)
|
||||
{
|
||||
if ((Timer < 1) || (Timer > 12)) {
|
||||
ASSERT(FALSE);
|
||||
return 0xFFFFFFFF;
|
||||
}
|
||||
|
||||
return 36 + Timer;
|
||||
}
|
||||
|
||||
UINT32
|
||||
UartBase (
|
||||
IN UINTN Uart
|
||||
)
|
||||
{
|
||||
switch (Uart) {
|
||||
case 1: return UART1_BASE;
|
||||
case 2: return UART2_BASE;
|
||||
case 3: return UART3_BASE;
|
||||
default: ASSERT(FALSE); return 0;
|
||||
}
|
||||
}
|
||||
|
||||
@ -1,37 +0,0 @@
|
||||
#/** @file
|
||||
#
|
||||
# Copyright (c) 2008 - 2010, Apple Inc. All rights reserved.
|
||||
# All rights reserved. This program and the accompanying materials
|
||||
# are licensed and made available under the terms and conditions of the BSD License
|
||||
# which accompanies this distribution. The full text of the license may be found at
|
||||
# http://opensource.org/licenses/bsd-license.php
|
||||
#
|
||||
# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
|
||||
# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
|
||||
#
|
||||
#**/
|
||||
|
||||
[Defines]
|
||||
INF_VERSION = 0x00010005
|
||||
BASE_NAME = OmapLib
|
||||
FILE_GUID = d035f5c2-1b92-4746-9f6c-5ff6202970df
|
||||
MODULE_TYPE = UEFI_DRIVER
|
||||
VERSION_STRING = 1.0
|
||||
LIBRARY_CLASS = OmapLib
|
||||
|
||||
[Sources.common]
|
||||
OmapLib.c
|
||||
|
||||
[Packages]
|
||||
MdePkg/MdePkg.dec
|
||||
EmbeddedPkg/EmbeddedPkg.dec
|
||||
BeagleBoardPkg/BeagleBoardPkg.dec
|
||||
|
||||
[LibraryClasses]
|
||||
DebugLib
|
||||
|
||||
[Protocols]
|
||||
|
||||
[Guids]
|
||||
|
||||
[Pcd]
|
||||
@ -1,84 +0,0 @@
|
||||
/** @file
|
||||
Template library implementation to support ResetSystem Runtime call.
|
||||
|
||||
Fill in the templates with what ever makes you system reset.
|
||||
|
||||
|
||||
Copyright (c) 2008-2009, Apple Inc. All rights reserved.
|
||||
|
||||
All rights reserved. This program and the accompanying materials
|
||||
are licensed and made available under the terms and conditions of the BSD License
|
||||
which accompanies this distribution. The full text of the license may be found at
|
||||
http://opensource.org/licenses/bsd-license.php
|
||||
|
||||
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
|
||||
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
|
||||
|
||||
**/
|
||||
|
||||
|
||||
#include <PiDxe.h>
|
||||
|
||||
#include <Library/PcdLib.h>
|
||||
#include <Library/ArmLib.h>
|
||||
#include <Library/CacheMaintenanceLib.h>
|
||||
#include <Library/DebugLib.h>
|
||||
#include <Library/EfiResetSystemLib.h>
|
||||
|
||||
#include <Library/BeagleBoardSystemLib.h>
|
||||
|
||||
/**
|
||||
Resets the entire platform.
|
||||
|
||||
@param ResetType The type of reset to perform.
|
||||
@param ResetStatus The status code for the reset.
|
||||
@param DataSize The size, in bytes, of WatchdogData.
|
||||
@param ResetData For a ResetType of EfiResetCold, EfiResetWarm, or
|
||||
EfiResetShutdown the data buffer starts with a Null-terminated
|
||||
Unicode string, optionally followed by additional binary data.
|
||||
|
||||
**/
|
||||
EFI_STATUS
|
||||
EFIAPI
|
||||
LibResetSystem (
|
||||
IN EFI_RESET_TYPE ResetType,
|
||||
IN EFI_STATUS ResetStatus,
|
||||
IN UINTN DataSize,
|
||||
IN CHAR16 *ResetData OPTIONAL
|
||||
)
|
||||
{
|
||||
if (ResetData != NULL) {
|
||||
DEBUG((EFI_D_ERROR, "%s", ResetData));
|
||||
}
|
||||
|
||||
//Shutdown EFI services.
|
||||
ShutdownEfi();
|
||||
|
||||
//Reset the sytem.
|
||||
ResetSystem(ResetType);
|
||||
|
||||
// If the reset didn't work, return an error.
|
||||
return EFI_DEVICE_ERROR;
|
||||
}
|
||||
|
||||
|
||||
|
||||
/**
|
||||
Initialize any infrastructure required for LibResetSystem () to function.
|
||||
|
||||
@param ImageHandle The firmware allocated handle for the EFI image.
|
||||
@param SystemTable A pointer to the EFI System Table.
|
||||
|
||||
@retval EFI_SUCCESS The constructor always returns EFI_SUCCESS.
|
||||
|
||||
**/
|
||||
EFI_STATUS
|
||||
EFIAPI
|
||||
LibInitializeResetSystem (
|
||||
IN EFI_HANDLE ImageHandle,
|
||||
IN EFI_SYSTEM_TABLE *SystemTable
|
||||
)
|
||||
{
|
||||
return EFI_SUCCESS;
|
||||
}
|
||||
|
||||
@ -1,40 +0,0 @@
|
||||
#/** @file
|
||||
# Reset System lib to make it easy to port new platforms
|
||||
#
|
||||
# Copyright (c) 2008, Apple Inc.
|
||||
#
|
||||
# All rights reserved. This program and the accompanying materials
|
||||
# are licensed and made available under the terms and conditions of the BSD License
|
||||
# which accompanies this distribution. The full text of the license may be found at
|
||||
# http://opensource.org/licenses/bsd-license.php
|
||||
# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
|
||||
# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
|
||||
#
|
||||
#
|
||||
#**/
|
||||
|
||||
[Defines]
|
||||
INF_VERSION = 0x00010005
|
||||
BASE_NAME = BeagleBoardResetSystemLib
|
||||
FILE_GUID = 781371a2-3fdd-41d4-96a1-7b34cbc9e895
|
||||
MODULE_TYPE = BASE
|
||||
VERSION_STRING = 1.0
|
||||
LIBRARY_CLASS = EfiResetSystemLib
|
||||
|
||||
|
||||
[Sources.common]
|
||||
ResetSystemLib.c
|
||||
|
||||
[Packages]
|
||||
BeagleBoardPkg/BeagleBoardPkg.dec
|
||||
ArmPkg/ArmPkg.dec
|
||||
MdePkg/MdePkg.dec
|
||||
EmbeddedPkg/EmbeddedPkg.dec
|
||||
|
||||
[Pcd.common]
|
||||
gArmTokenSpaceGuid.PcdCpuResetAddress
|
||||
gEmbeddedTokenSpaceGuid.PcdEmbeddedFdBaseAddress
|
||||
|
||||
[LibraryClasses]
|
||||
DebugLib
|
||||
BeagleBoardSystemLib
|
||||
@ -1,124 +0,0 @@
|
||||
/** @file
|
||||
Serial I/O Port library functions with no library constructor/destructor
|
||||
|
||||
|
||||
Copyright (c) 2008-2009, Apple Inc. All rights reserved.
|
||||
|
||||
All rights reserved. This program and the accompanying materials
|
||||
are licensed and made available under the terms and conditions of the BSD License
|
||||
which accompanies this distribution. The full text of the license may be found at
|
||||
http://opensource.org/licenses/bsd-license.php
|
||||
|
||||
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
|
||||
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
|
||||
|
||||
**/
|
||||
|
||||
#include <Base.h>
|
||||
#include <Library/DebugLib.h>
|
||||
#include <Library/SerialPortLib.h>
|
||||
#include <Library/PcdLib.h>
|
||||
#include <Library/IoLib.h>
|
||||
#include <Library/OmapLib.h>
|
||||
#include <Omap3530/Omap3530.h>
|
||||
|
||||
/*
|
||||
|
||||
Programmed hardware of Serial port.
|
||||
|
||||
@return Always return EFI_UNSUPPORTED.
|
||||
|
||||
**/
|
||||
RETURN_STATUS
|
||||
EFIAPI
|
||||
SerialPortInitialize (
|
||||
VOID
|
||||
)
|
||||
{
|
||||
// assume assembly code at reset vector has setup UART
|
||||
return RETURN_SUCCESS;
|
||||
}
|
||||
|
||||
/**
|
||||
Write data to serial device.
|
||||
|
||||
@param Buffer Point of data buffer which need to be writed.
|
||||
@param NumberOfBytes Number of output bytes which are cached in Buffer.
|
||||
|
||||
@retval 0 Write data failed.
|
||||
@retval !0 Actual number of bytes writed to serial device.
|
||||
|
||||
**/
|
||||
UINTN
|
||||
EFIAPI
|
||||
SerialPortWrite (
|
||||
IN UINT8 *Buffer,
|
||||
IN UINTN NumberOfBytes
|
||||
)
|
||||
{
|
||||
UINT32 LSR = UartBase(PcdGet32(PcdBeagleConsoleUart)) + UART_LSR_REG;
|
||||
UINT32 THR = UartBase(PcdGet32(PcdBeagleConsoleUart)) + UART_THR_REG;
|
||||
UINTN Count;
|
||||
|
||||
for (Count = 0; Count < NumberOfBytes; Count++, Buffer++) {
|
||||
while ((MmioRead8(LSR) & UART_LSR_TX_FIFO_E_MASK) == UART_LSR_TX_FIFO_E_NOT_EMPTY);
|
||||
MmioWrite8(THR, *Buffer);
|
||||
}
|
||||
|
||||
return NumberOfBytes;
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
Read data from serial device and save the datas in buffer.
|
||||
|
||||
@param Buffer Point of data buffer which need to be writed.
|
||||
@param NumberOfBytes Number of output bytes which are cached in Buffer.
|
||||
|
||||
@retval 0 Read data failed.
|
||||
@retval !0 Aactual number of bytes read from serial device.
|
||||
|
||||
**/
|
||||
UINTN
|
||||
EFIAPI
|
||||
SerialPortRead (
|
||||
OUT UINT8 *Buffer,
|
||||
IN UINTN NumberOfBytes
|
||||
)
|
||||
{
|
||||
UINT32 LSR = UartBase(PcdGet32(PcdBeagleConsoleUart)) + UART_LSR_REG;
|
||||
UINT32 RBR = UartBase(PcdGet32(PcdBeagleConsoleUart)) + UART_RBR_REG;
|
||||
UINTN Count;
|
||||
|
||||
for (Count = 0; Count < NumberOfBytes; Count++, Buffer++) {
|
||||
while ((MmioRead8(LSR) & UART_LSR_RX_FIFO_E_MASK) == UART_LSR_RX_FIFO_E_EMPTY);
|
||||
*Buffer = MmioRead8(RBR);
|
||||
}
|
||||
|
||||
return NumberOfBytes;
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
Check to see if any data is avaiable to be read from the debug device.
|
||||
|
||||
@retval EFI_SUCCESS At least one byte of data is avaiable to be read
|
||||
@retval EFI_NOT_READY No data is avaiable to be read
|
||||
@retval EFI_DEVICE_ERROR The serial device is not functioning properly
|
||||
|
||||
**/
|
||||
BOOLEAN
|
||||
EFIAPI
|
||||
SerialPortPoll (
|
||||
VOID
|
||||
)
|
||||
{
|
||||
UINT32 LSR = UartBase(PcdGet32(PcdBeagleConsoleUart)) + UART_LSR_REG;
|
||||
|
||||
if ((MmioRead8(LSR) & UART_LSR_RX_FIFO_E_MASK) == UART_LSR_RX_FIFO_E_NOT_EMPTY) {
|
||||
return TRUE;
|
||||
} else {
|
||||
return FALSE;
|
||||
}
|
||||
}
|
||||
|
||||
@ -1,43 +0,0 @@
|
||||
#/** @file
|
||||
# EDK Serial port lib
|
||||
#
|
||||
# Copyright (c) 2009, Apple Inc.
|
||||
#
|
||||
# All rights reserved. This program and the accompanying materials
|
||||
# are licensed and made available under the terms and conditions of the BSD License
|
||||
# which accompanies this distribution. The full text of the license may be found at
|
||||
# http://opensource.org/licenses/bsd-license.php
|
||||
# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
|
||||
# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
|
||||
#
|
||||
#
|
||||
#**/
|
||||
|
||||
[Defines]
|
||||
INF_VERSION = 0x00010005
|
||||
BASE_NAME = BeagleBoardSerialPortLib
|
||||
FILE_GUID = 97546cbd-c0ff-4c48-ab0b-e4f58862acd3
|
||||
MODULE_TYPE = PEIM
|
||||
VERSION_STRING = 1.0
|
||||
LIBRARY_CLASS = SerialPortLib
|
||||
|
||||
|
||||
#
|
||||
# VALID_ARCHITECTURES = IA32 X64 IPF EBC
|
||||
#
|
||||
|
||||
[Sources.common]
|
||||
SerialPortLib.c
|
||||
|
||||
[LibraryClasses]
|
||||
DebugLib
|
||||
IoLib
|
||||
OmapLib
|
||||
|
||||
[Packages]
|
||||
MdePkg/MdePkg.dec
|
||||
BeagleBoardPkg/BeagleBoardPkg.dec
|
||||
|
||||
[FixedPcd]
|
||||
gBeagleBoardTokenSpaceGuid.PcdBeagleConsoleUart
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@ -1,158 +0,0 @@
|
||||
/** @file
|
||||
|
||||
Copyright (c) 2008-2009 Apple Inc. All rights reserved.<BR>
|
||||
|
||||
All rights reserved. This program and the accompanying materials
|
||||
are licensed and made available under the terms and conditions of the BSD License
|
||||
which accompanies this distribution. The full text of the license may be found at
|
||||
http://opensource.org/licenses/bsd-license.php
|
||||
|
||||
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
|
||||
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
|
||||
|
||||
**/
|
||||
|
||||
#ifndef _MMCHS_H_
|
||||
#define _MMCHS_H_
|
||||
|
||||
#include <Library/BaseLib.h>
|
||||
#include <Library/MemoryAllocationLib.h>
|
||||
#include <Library/DebugLib.h>
|
||||
#include <Library/IoLib.h>
|
||||
#include <Library/PcdLib.h>
|
||||
#include <Library/UefiBootServicesTableLib.h>
|
||||
|
||||
#include <Protocol/EmbeddedExternalDevice.h>
|
||||
#include <Protocol/BlockIo.h>
|
||||
#include <Protocol/Cpu.h>
|
||||
#include <Protocol/DevicePath.h>
|
||||
|
||||
#include <Omap3530/Omap3530.h>
|
||||
#include <TPS65950.h>
|
||||
|
||||
#define MAX_RETRY_COUNT 100
|
||||
|
||||
#define HCS (0x1UL << 30) //Host capacity support/1 = Supporting high capacity
|
||||
#define CCS (0x1UL << 30) //Card capacity status/1 = High capacity card
|
||||
typedef struct {
|
||||
UINT32 Reserved0: 7; // 0
|
||||
UINT32 V170_V195: 1; // 1.70V - 1.95V
|
||||
UINT32 V200_V260: 7; // 2.00V - 2.60V
|
||||
UINT32 V270_V360: 9; // 2.70V - 3.60V
|
||||
UINT32 RESERVED_1: 5; // Reserved
|
||||
UINT32 AccessMode: 2; // 00b (byte mode), 10b (sector mode)
|
||||
UINT32 Busy: 1; // This bit is set to LOW if the card has not finished the power up routine
|
||||
}OCR;
|
||||
|
||||
typedef struct {
|
||||
UINT32 NOT_USED; // 1 [0:0]
|
||||
UINT32 CRC; // CRC7 checksum [7:1]
|
||||
UINT32 MDT; // Manufacturing date [19:8]
|
||||
UINT32 RESERVED_1; // Reserved [23:20]
|
||||
UINT32 PSN; // Product serial number [55:24]
|
||||
UINT8 PRV; // Product revision [63:56]
|
||||
UINT8 PNM[5]; // Product name [64:103]
|
||||
UINT16 OID; // OEM/Application ID [119:104]
|
||||
UINT8 MID; // Manufacturer ID [127:120]
|
||||
}CID;
|
||||
|
||||
typedef struct {
|
||||
UINT8 NOT_USED: 1; // Not used, always 1 [0:0]
|
||||
UINT8 CRC: 7; // CRC [7:1]
|
||||
UINT8 RESERVED_1: 2; // Reserved [9:8]
|
||||
UINT8 FILE_FORMAT: 2; // File format [11:10]
|
||||
UINT8 TMP_WRITE_PROTECT: 1; // Temporary write protection [12:12]
|
||||
UINT8 PERM_WRITE_PROTECT: 1; // Permanent write protection [13:13]
|
||||
UINT8 COPY: 1; // Copy flag (OTP) [14:14]
|
||||
UINT8 FILE_FORMAT_GRP: 1; // File format group [15:15]
|
||||
UINT16 RESERVED_2: 5; // Reserved [20:16]
|
||||
UINT16 WRITE_BL_PARTIAL: 1; // Partial blocks for write allowed [21:21]
|
||||
UINT16 WRITE_BL_LEN: 4; // Max. write data block length [25:22]
|
||||
UINT16 R2W_FACTOR: 3; // Write speed factor [28:26]
|
||||
UINT16 RESERVED_3: 2; // Reserved [30:29]
|
||||
UINT16 WP_GRP_ENABLE: 1; // Write protect group enable [31:31]
|
||||
UINT32 WP_GRP_SIZE: 7; // Write protect group size [38:32]
|
||||
UINT32 SECTOR_SIZE: 7; // Erase sector size [45:39]
|
||||
UINT32 ERASE_BLK_EN: 1; // Erase single block enable [46:46]
|
||||
UINT32 C_SIZE_MULT: 3; // Device size multiplier [49:47]
|
||||
UINT32 VDD_W_CURR_MAX: 3; // Max. write current @ VDD max [52:50]
|
||||
UINT32 VDD_W_CURR_MIN: 3; // Max. write current @ VDD min [55:53]
|
||||
UINT32 VDD_R_CURR_MAX: 3; // Max. read current @ VDD max [58:56]
|
||||
UINT32 VDD_R_CURR_MIN: 3; // Max. read current @ VDD min [61:59]
|
||||
UINT32 C_SIZELow2: 2; // Device size [73:62]
|
||||
UINT32 C_SIZEHigh10: 10;// Device size [73:62]
|
||||
UINT32 RESERVED_4: 2; // Reserved [75:74]
|
||||
UINT32 DSR_IMP: 1; // DSR implemented [76:76]
|
||||
UINT32 READ_BLK_MISALIGN: 1; // Read block misalignment [77:77]
|
||||
UINT32 WRITE_BLK_MISALIGN: 1; // Write block misalignment [78:78]
|
||||
UINT32 READ_BL_PARTIAL: 1; // Partial blocks for read allowed [79:79]
|
||||
UINT32 READ_BL_LEN: 4; // Max. read data block length [83:80]
|
||||
UINT32 CCC: 12;// Card command classes [95:84]
|
||||
UINT8 TRAN_SPEED ; // Max. bus clock frequency [103:96]
|
||||
UINT8 NSAC ; // Data read access-time 2 in CLK cycles (NSAC*100) [111:104]
|
||||
UINT8 TAAC ; // Data read access-time 1 [119:112]
|
||||
UINT8 RESERVED_5: 6; // Reserved [125:120]
|
||||
UINT8 CSD_STRUCTURE: 2; // CSD structure [127:126]
|
||||
}CSD;
|
||||
|
||||
typedef struct {
|
||||
UINT8 NOT_USED: 1; // Not used, always 1 [0:0]
|
||||
UINT8 CRC: 7; // CRC [7:1]
|
||||
UINT8 RESERVED_1: 2; // Reserved [9:8]
|
||||
UINT8 FILE_FORMAT: 2; // File format [11:10]
|
||||
UINT8 TMP_WRITE_PROTECT: 1; // Temporary write protection [12:12]
|
||||
UINT8 PERM_WRITE_PROTECT: 1; // Permanent write protection [13:13]
|
||||
UINT8 COPY: 1; // Copy flag (OTP) [14:14]
|
||||
UINT8 FILE_FORMAT_GRP: 1; // File format group [15:15]
|
||||
UINT16 RESERVED_2: 5; // Reserved [20:16]
|
||||
UINT16 WRITE_BL_PARTIAL: 1; // Partial blocks for write allowed [21:21]
|
||||
UINT16 WRITE_BL_LEN: 4; // Max. write data block length [25:22]
|
||||
UINT16 R2W_FACTOR: 3; // Write speed factor [28:26]
|
||||
UINT16 RESERVED_3: 2; // Reserved [30:29]
|
||||
UINT16 WP_GRP_ENABLE: 1; // Write protect group enable [31:31]
|
||||
UINT16 WP_GRP_SIZE: 7; // Write protect group size [38:32]
|
||||
UINT16 SECTOR_SIZE: 7; // Erase sector size [45:39]
|
||||
UINT16 ERASE_BLK_EN: 1; // Erase single block enable [46:46]
|
||||
UINT16 RESERVED_4: 1; // Reserved [47:47]
|
||||
UINT32 C_SIZELow16: 16;// Device size [69:48]
|
||||
UINT32 C_SIZEHigh6: 6; // Device size [69:48]
|
||||
UINT32 RESERVED_5: 6; // Reserved [75:70]
|
||||
UINT32 DSR_IMP: 1; // DSR implemented [76:76]
|
||||
UINT32 READ_BLK_MISALIGN: 1; // Read block misalignment [77:77]
|
||||
UINT32 WRITE_BLK_MISALIGN: 1; // Write block misalignment [78:78]
|
||||
UINT32 READ_BL_PARTIAL: 1; // Partial blocks for read allowed [79:79]
|
||||
UINT16 READ_BL_LEN: 4; // Max. read data block length [83:80]
|
||||
UINT16 CCC: 12;// Card command classes [95:84]
|
||||
UINT8 TRAN_SPEED ; // Max. bus clock frequency [103:96]
|
||||
UINT8 NSAC ; // Data read access-time 2 in CLK cycles (NSAC*100) [111:104]
|
||||
UINT8 TAAC ; // Data read access-time 1 [119:112]
|
||||
UINT8 RESERVED_6: 6; // 0 [125:120]
|
||||
UINT8 CSD_STRUCTURE: 2; // CSD structure [127:126]
|
||||
}CSD_SDV2;
|
||||
|
||||
typedef enum {
|
||||
UNKNOWN_CARD,
|
||||
MMC_CARD, //MMC card
|
||||
SD_CARD, //SD 1.1 card
|
||||
SD_CARD_2, //SD 2.0 or above standard card
|
||||
SD_CARD_2_HIGH //SD 2.0 or above high capacity card
|
||||
} CARD_TYPE;
|
||||
|
||||
typedef enum {
|
||||
READ,
|
||||
WRITE
|
||||
} OPERATION_TYPE;
|
||||
|
||||
typedef struct
|
||||
{
|
||||
UINT16 RCA;
|
||||
UINTN BlockSize;
|
||||
UINTN NumBlocks;
|
||||
UINTN ClockFrequencySelect;
|
||||
CARD_TYPE CardType;
|
||||
OCR OCRData;
|
||||
CID CIDData;
|
||||
CSD CSDData;
|
||||
} CARD_INFO;
|
||||
|
||||
#endif
|
||||
@ -1,51 +0,0 @@
|
||||
#/** @file
|
||||
#
|
||||
# Copyright (c) 2008 - 2010, Apple Inc. All rights reserved.
|
||||
# All rights reserved. This program and the accompanying materials
|
||||
# are licensed and made available under the terms and conditions of the BSD License
|
||||
# which accompanies this distribution. The full text of the license may be found at
|
||||
# http://opensource.org/licenses/bsd-license.php
|
||||
#
|
||||
# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
|
||||
# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
|
||||
#
|
||||
#**/
|
||||
|
||||
[Defines]
|
||||
INF_VERSION = 0x00010005
|
||||
BASE_NAME = MMCHS
|
||||
FILE_GUID = 100c2cfa-b586-4198-9b4c-1683d195b1da
|
||||
MODULE_TYPE = DXE_DRIVER
|
||||
VERSION_STRING = 1.0
|
||||
|
||||
ENTRY_POINT = MMCHSInitialize
|
||||
|
||||
|
||||
[Sources.common]
|
||||
MMCHS.c
|
||||
|
||||
[Packages]
|
||||
MdePkg/MdePkg.dec
|
||||
EmbeddedPkg/EmbeddedPkg.dec
|
||||
BeagleBoardPkg/BeagleBoardPkg.dec
|
||||
|
||||
[LibraryClasses]
|
||||
PcdLib
|
||||
UefiLib
|
||||
UefiDriverEntryPoint
|
||||
MemoryAllocationLib
|
||||
IoLib
|
||||
|
||||
[Guids]
|
||||
|
||||
[Protocols]
|
||||
gEfiBlockIoProtocolGuid
|
||||
gEfiCpuArchProtocolGuid
|
||||
gEfiDevicePathProtocolGuid
|
||||
gEmbeddedExternalDeviceProtocolGuid
|
||||
|
||||
[Pcd]
|
||||
gBeagleBoardTokenSpaceGuid.PcdBeagleMMCHS1Base
|
||||
|
||||
[depex]
|
||||
gEmbeddedExternalDeviceProtocolGuid
|
||||
@ -1,578 +0,0 @@
|
||||
/** @file
|
||||
|
||||
Copyright (c) 2008-2009, Apple Inc. All rights reserved.
|
||||
|
||||
All rights reserved. This program and the accompanying materials
|
||||
are licensed and made available under the terms and conditions of the BSD License
|
||||
which accompanies this distribution. The full text of the license may be found at
|
||||
http://opensource.org/licenses/bsd-license.php
|
||||
|
||||
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
|
||||
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
|
||||
|
||||
**/
|
||||
|
||||
#include "PciEmulation.h"
|
||||
#include <Omap3530/Omap3530.h>
|
||||
|
||||
EFI_CPU_ARCH_PROTOCOL *gCpu;
|
||||
EMBEDDED_EXTERNAL_DEVICE *gTPS65950;
|
||||
|
||||
#define HOST_CONTROLLER_OPERATION_REG_SIZE 0x44
|
||||
|
||||
typedef struct {
|
||||
ACPI_HID_DEVICE_PATH AcpiDevicePath;
|
||||
PCI_DEVICE_PATH PciDevicePath;
|
||||
EFI_DEVICE_PATH_PROTOCOL EndDevicePath;
|
||||
} EFI_PCI_IO_DEVICE_PATH;
|
||||
|
||||
typedef struct {
|
||||
UINT32 Signature;
|
||||
EFI_PCI_IO_DEVICE_PATH DevicePath;
|
||||
EFI_PCI_IO_PROTOCOL PciIoProtocol;
|
||||
PCI_TYPE00 *ConfigSpace;
|
||||
PCI_ROOT_BRIDGE RootBridge;
|
||||
UINTN Segment;
|
||||
} EFI_PCI_IO_PRIVATE_DATA;
|
||||
|
||||
#define EFI_PCI_IO_PRIVATE_DATA_SIGNATURE SIGNATURE_32('p', 'c', 'i', 'o')
|
||||
#define EFI_PCI_IO_PRIVATE_DATA_FROM_THIS(a) CR(a, EFI_PCI_IO_PRIVATE_DATA, PciIoProtocol, EFI_PCI_IO_PRIVATE_DATA_SIGNATURE)
|
||||
|
||||
EFI_PCI_IO_DEVICE_PATH PciIoDevicePathTemplate =
|
||||
{
|
||||
{
|
||||
{ ACPI_DEVICE_PATH, ACPI_DP, sizeof (ACPI_HID_DEVICE_PATH), 0},
|
||||
EISA_PNP_ID(0x0A03), // HID
|
||||
0 // UID
|
||||
},
|
||||
{
|
||||
{ HARDWARE_DEVICE_PATH, HW_PCI_DP, sizeof (PCI_DEVICE_PATH), 0},
|
||||
0,
|
||||
0
|
||||
},
|
||||
{ END_DEVICE_PATH_TYPE, END_ENTIRE_DEVICE_PATH_SUBTYPE, sizeof (EFI_DEVICE_PATH_PROTOCOL), 0}
|
||||
};
|
||||
|
||||
STATIC
|
||||
VOID
|
||||
ConfigureUSBHost (
|
||||
VOID
|
||||
)
|
||||
{
|
||||
EFI_STATUS Status;
|
||||
UINT8 Data = 0;
|
||||
|
||||
// Take USB host out of force-standby mode
|
||||
MmioWrite32(UHH_SYSCONFIG, UHH_SYSCONFIG_MIDLEMODE_NO_STANDBY
|
||||
| UHH_SYSCONFIG_CLOCKACTIVITY_ON
|
||||
| UHH_SYSCONFIG_SIDLEMODE_NO_STANDBY
|
||||
| UHH_SYSCONFIG_ENAWAKEUP_ENABLE
|
||||
| UHH_SYSCONFIG_AUTOIDLE_ALWAYS_RUN);
|
||||
MmioWrite32(UHH_HOSTCONFIG, UHH_HOSTCONFIG_P3_CONNECT_STATUS_DISCONNECT
|
||||
| UHH_HOSTCONFIG_P2_CONNECT_STATUS_DISCONNECT
|
||||
| UHH_HOSTCONFIG_P1_CONNECT_STATUS_DISCONNECT
|
||||
| UHH_HOSTCONFIG_ENA_INCR_ALIGN_DISABLE
|
||||
| UHH_HOSTCONFIG_ENA_INCR16_ENABLE
|
||||
| UHH_HOSTCONFIG_ENA_INCR8_ENABLE
|
||||
| UHH_HOSTCONFIG_ENA_INCR4_ENABLE
|
||||
| UHH_HOSTCONFIG_AUTOPPD_ON_OVERCUR_EN_ON
|
||||
| UHH_HOSTCONFIG_P1_ULPI_BYPASS_ULPI_MODE);
|
||||
|
||||
// USB reset (GPIO 147 - Port 5 pin 19) output high
|
||||
MmioAnd32(GPIO5_BASE + GPIO_OE, ~BIT19);
|
||||
MmioWrite32(GPIO5_BASE + GPIO_SETDATAOUT, BIT19);
|
||||
|
||||
// Get the Power IC protocol.
|
||||
Status = gBS->LocateProtocol(&gEmbeddedExternalDeviceProtocolGuid, NULL, (VOID **)&gTPS65950);
|
||||
ASSERT_EFI_ERROR(Status);
|
||||
|
||||
//Enable power to the USB host.
|
||||
Status = gTPS65950->Read(gTPS65950, EXTERNAL_DEVICE_REGISTER(I2C_ADDR_GRP_ID3, LEDEN), 1, &Data);
|
||||
ASSERT_EFI_ERROR(Status);
|
||||
|
||||
//LEDAON & LEDAPWM control the power to the USB host so enable those bits.
|
||||
Data |= (LEDAON | LEDAPWM);
|
||||
|
||||
Status = gTPS65950->Write(gTPS65950, EXTERNAL_DEVICE_REGISTER(I2C_ADDR_GRP_ID3, LEDEN), 1, &Data);
|
||||
ASSERT_EFI_ERROR(Status);
|
||||
}
|
||||
|
||||
EFI_STATUS
|
||||
PciIoPollMem (
|
||||
IN EFI_PCI_IO_PROTOCOL *This,
|
||||
IN EFI_PCI_IO_PROTOCOL_WIDTH Width,
|
||||
IN UINT8 BarIndex,
|
||||
IN UINT64 Offset,
|
||||
IN UINT64 Mask,
|
||||
IN UINT64 Value,
|
||||
IN UINT64 Delay,
|
||||
OUT UINT64 *Result
|
||||
)
|
||||
{
|
||||
ASSERT (FALSE);
|
||||
return EFI_UNSUPPORTED;
|
||||
}
|
||||
|
||||
EFI_STATUS
|
||||
PciIoPollIo (
|
||||
IN EFI_PCI_IO_PROTOCOL *This,
|
||||
IN EFI_PCI_IO_PROTOCOL_WIDTH Width,
|
||||
IN UINT8 BarIndex,
|
||||
IN UINT64 Offset,
|
||||
IN UINT64 Mask,
|
||||
IN UINT64 Value,
|
||||
IN UINT64 Delay,
|
||||
OUT UINT64 *Result
|
||||
)
|
||||
{
|
||||
ASSERT (FALSE);
|
||||
return EFI_UNSUPPORTED;
|
||||
}
|
||||
|
||||
EFI_STATUS
|
||||
PciIoMemRead (
|
||||
IN EFI_PCI_IO_PROTOCOL *This,
|
||||
IN EFI_PCI_IO_PROTOCOL_WIDTH Width,
|
||||
IN UINT8 BarIndex,
|
||||
IN UINT64 Offset,
|
||||
IN UINTN Count,
|
||||
IN OUT VOID *Buffer
|
||||
)
|
||||
{
|
||||
EFI_PCI_IO_PRIVATE_DATA *Private = EFI_PCI_IO_PRIVATE_DATA_FROM_THIS(This);
|
||||
|
||||
return PciRootBridgeIoMemRead (&Private->RootBridge.Io,
|
||||
(EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH) Width,
|
||||
Private->ConfigSpace->Device.Bar[BarIndex] + Offset,
|
||||
Count,
|
||||
Buffer
|
||||
);
|
||||
}
|
||||
|
||||
EFI_STATUS
|
||||
PciIoMemWrite (
|
||||
IN EFI_PCI_IO_PROTOCOL *This,
|
||||
IN EFI_PCI_IO_PROTOCOL_WIDTH Width,
|
||||
IN UINT8 BarIndex,
|
||||
IN UINT64 Offset,
|
||||
IN UINTN Count,
|
||||
IN OUT VOID *Buffer
|
||||
)
|
||||
{
|
||||
EFI_PCI_IO_PRIVATE_DATA *Private = EFI_PCI_IO_PRIVATE_DATA_FROM_THIS(This);
|
||||
|
||||
return PciRootBridgeIoMemWrite (&Private->RootBridge.Io,
|
||||
(EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH) Width,
|
||||
Private->ConfigSpace->Device.Bar[BarIndex] + Offset,
|
||||
Count,
|
||||
Buffer
|
||||
);
|
||||
}
|
||||
|
||||
EFI_STATUS
|
||||
PciIoIoRead (
|
||||
IN EFI_PCI_IO_PROTOCOL *This,
|
||||
IN EFI_PCI_IO_PROTOCOL_WIDTH Width,
|
||||
IN UINT8 BarIndex,
|
||||
IN UINT64 Offset,
|
||||
IN UINTN Count,
|
||||
IN OUT VOID *Buffer
|
||||
)
|
||||
{
|
||||
ASSERT (FALSE);
|
||||
return EFI_UNSUPPORTED;
|
||||
}
|
||||
|
||||
EFI_STATUS
|
||||
PciIoIoWrite (
|
||||
IN EFI_PCI_IO_PROTOCOL *This,
|
||||
IN EFI_PCI_IO_PROTOCOL_WIDTH Width,
|
||||
IN UINT8 BarIndex,
|
||||
IN UINT64 Offset,
|
||||
IN UINTN Count,
|
||||
IN OUT VOID *Buffer
|
||||
)
|
||||
{
|
||||
ASSERT (FALSE);
|
||||
return EFI_UNSUPPORTED;
|
||||
}
|
||||
|
||||
EFI_STATUS
|
||||
PciIoPciRead (
|
||||
IN EFI_PCI_IO_PROTOCOL *This,
|
||||
IN EFI_PCI_IO_PROTOCOL_WIDTH Width,
|
||||
IN UINT32 Offset,
|
||||
IN UINTN Count,
|
||||
IN OUT VOID *Buffer
|
||||
)
|
||||
{
|
||||
EFI_PCI_IO_PRIVATE_DATA *Private = EFI_PCI_IO_PRIVATE_DATA_FROM_THIS(This);
|
||||
|
||||
return PciRootBridgeIoMemRW ((EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH)Width,
|
||||
Count,
|
||||
TRUE,
|
||||
(PTR)(UINTN)Buffer,
|
||||
TRUE,
|
||||
(PTR)(UINTN)(((UINT8 *)Private->ConfigSpace) + Offset)
|
||||
);
|
||||
}
|
||||
|
||||
EFI_STATUS
|
||||
PciIoPciWrite (
|
||||
IN EFI_PCI_IO_PROTOCOL *This,
|
||||
IN EFI_PCI_IO_PROTOCOL_WIDTH Width,
|
||||
IN UINT32 Offset,
|
||||
IN UINTN Count,
|
||||
IN OUT VOID *Buffer
|
||||
)
|
||||
{
|
||||
EFI_PCI_IO_PRIVATE_DATA *Private = EFI_PCI_IO_PRIVATE_DATA_FROM_THIS(This);
|
||||
|
||||
return PciRootBridgeIoMemRW ((EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH) Width,
|
||||
Count,
|
||||
TRUE,
|
||||
(PTR)(UINTN)(((UINT8 *)Private->ConfigSpace) + Offset),
|
||||
TRUE,
|
||||
(PTR)(UINTN)Buffer
|
||||
);
|
||||
}
|
||||
|
||||
EFI_STATUS
|
||||
PciIoCopyMem (
|
||||
IN EFI_PCI_IO_PROTOCOL *This,
|
||||
IN EFI_PCI_IO_PROTOCOL_WIDTH Width,
|
||||
IN UINT8 DestBarIndex,
|
||||
IN UINT64 DestOffset,
|
||||
IN UINT8 SrcBarIndex,
|
||||
IN UINT64 SrcOffset,
|
||||
IN UINTN Count
|
||||
)
|
||||
{
|
||||
ASSERT (FALSE);
|
||||
return EFI_UNSUPPORTED;
|
||||
}
|
||||
|
||||
EFI_STATUS
|
||||
PciIoMap (
|
||||
IN EFI_PCI_IO_PROTOCOL *This,
|
||||
IN EFI_PCI_IO_PROTOCOL_OPERATION Operation,
|
||||
IN VOID *HostAddress,
|
||||
IN OUT UINTN *NumberOfBytes,
|
||||
OUT EFI_PHYSICAL_ADDRESS *DeviceAddress,
|
||||
OUT VOID **Mapping
|
||||
)
|
||||
{
|
||||
MAP_INFO_INSTANCE *Map;
|
||||
EFI_STATUS Status;
|
||||
|
||||
if ( HostAddress == NULL || NumberOfBytes == NULL ||
|
||||
DeviceAddress == NULL || Mapping == NULL ) {
|
||||
|
||||
return EFI_INVALID_PARAMETER;
|
||||
}
|
||||
|
||||
|
||||
if (Operation >= EfiPciOperationMaximum) {
|
||||
return EFI_INVALID_PARAMETER;
|
||||
}
|
||||
|
||||
*DeviceAddress = ConvertToPhysicalAddress (HostAddress);
|
||||
|
||||
// Data cache flush (HostAddress, NumberOfBytes);
|
||||
|
||||
// Remember range so we can flush on the other side
|
||||
Status = gBS->AllocatePool (EfiBootServicesData, sizeof (PCI_DMA_MAP), (VOID **) &Map);
|
||||
if (EFI_ERROR(Status)) {
|
||||
return EFI_OUT_OF_RESOURCES;
|
||||
}
|
||||
|
||||
*Mapping = Map;
|
||||
|
||||
Map->HostAddress = (UINTN)HostAddress;
|
||||
Map->DeviceAddress = *DeviceAddress;
|
||||
Map->NumberOfBytes = *NumberOfBytes;
|
||||
Map->Operation = Operation;
|
||||
|
||||
// EfiCpuFlushTypeWriteBack, EfiCpuFlushTypeInvalidate
|
||||
gCpu->FlushDataCache (gCpu, (EFI_PHYSICAL_ADDRESS)(UINTN)HostAddress, *NumberOfBytes, EfiCpuFlushTypeWriteBackInvalidate);
|
||||
|
||||
return EFI_SUCCESS;
|
||||
}
|
||||
|
||||
EFI_STATUS
|
||||
PciIoUnmap (
|
||||
IN EFI_PCI_IO_PROTOCOL *This,
|
||||
IN VOID *Mapping
|
||||
)
|
||||
{
|
||||
PCI_DMA_MAP *Map;
|
||||
|
||||
if (Mapping == NULL) {
|
||||
ASSERT (FALSE);
|
||||
return EFI_INVALID_PARAMETER;
|
||||
}
|
||||
|
||||
Map = (PCI_DMA_MAP *)Mapping;
|
||||
if (Map->Operation == EfiPciOperationBusMasterWrite) {
|
||||
//
|
||||
// Make sure we read buffer from uncached memory and not the cache
|
||||
//
|
||||
gCpu->FlushDataCache (gCpu, Map->HostAddress, Map->NumberOfBytes, EfiCpuFlushTypeInvalidate);
|
||||
}
|
||||
|
||||
FreePool (Map);
|
||||
|
||||
return EFI_SUCCESS;
|
||||
}
|
||||
|
||||
EFI_STATUS
|
||||
PciIoAllocateBuffer (
|
||||
IN EFI_PCI_IO_PROTOCOL *This,
|
||||
IN EFI_ALLOCATE_TYPE Type,
|
||||
IN EFI_MEMORY_TYPE MemoryType,
|
||||
IN UINTN Pages,
|
||||
OUT VOID **HostAddress,
|
||||
IN UINT64 Attributes
|
||||
)
|
||||
{
|
||||
if (Attributes & EFI_PCI_ATTRIBUTE_INVALID_FOR_ALLOCATE_BUFFER) {
|
||||
return EFI_UNSUPPORTED;
|
||||
}
|
||||
|
||||
if (HostAddress == NULL) {
|
||||
return EFI_INVALID_PARAMETER;
|
||||
}
|
||||
|
||||
//
|
||||
// The only valid memory types are EfiBootServicesData and EfiRuntimeServicesData
|
||||
//
|
||||
// We used uncached memory to keep coherency
|
||||
//
|
||||
if (MemoryType == EfiBootServicesData) {
|
||||
*HostAddress = UncachedAllocatePages (Pages);
|
||||
} else if (MemoryType != EfiRuntimeServicesData) {
|
||||
*HostAddress = UncachedAllocateRuntimePages (Pages);
|
||||
} else {
|
||||
return EFI_INVALID_PARAMETER;
|
||||
}
|
||||
|
||||
return EFI_SUCCESS;
|
||||
}
|
||||
|
||||
EFI_STATUS
|
||||
PciIoFreeBuffer (
|
||||
IN EFI_PCI_IO_PROTOCOL *This,
|
||||
IN UINTN Pages,
|
||||
IN VOID *HostAddress
|
||||
)
|
||||
{
|
||||
if (HostAddress == NULL) {
|
||||
return EFI_INVALID_PARAMETER;
|
||||
}
|
||||
|
||||
UncachedFreePages (HostAddress, Pages);
|
||||
return EFI_SUCCESS;
|
||||
}
|
||||
|
||||
|
||||
EFI_STATUS
|
||||
PciIoFlush (
|
||||
IN EFI_PCI_IO_PROTOCOL *This
|
||||
)
|
||||
{
|
||||
return EFI_SUCCESS;
|
||||
}
|
||||
|
||||
EFI_STATUS
|
||||
PciIoGetLocation (
|
||||
IN EFI_PCI_IO_PROTOCOL *This,
|
||||
OUT UINTN *SegmentNumber,
|
||||
OUT UINTN *BusNumber,
|
||||
OUT UINTN *DeviceNumber,
|
||||
OUT UINTN *FunctionNumber
|
||||
)
|
||||
{
|
||||
EFI_PCI_IO_PRIVATE_DATA *Private = EFI_PCI_IO_PRIVATE_DATA_FROM_THIS(This);
|
||||
|
||||
if (SegmentNumber != NULL) {
|
||||
*SegmentNumber = Private->Segment;
|
||||
}
|
||||
|
||||
if (BusNumber != NULL) {
|
||||
*BusNumber = 0xff;
|
||||
}
|
||||
|
||||
if (DeviceNumber != NULL) {
|
||||
*DeviceNumber = 0;
|
||||
}
|
||||
|
||||
if (FunctionNumber != NULL) {
|
||||
*FunctionNumber = 0;
|
||||
}
|
||||
|
||||
return EFI_SUCCESS;
|
||||
}
|
||||
|
||||
EFI_STATUS
|
||||
PciIoAttributes (
|
||||
IN EFI_PCI_IO_PROTOCOL *This,
|
||||
IN EFI_PCI_IO_PROTOCOL_ATTRIBUTE_OPERATION Operation,
|
||||
IN UINT64 Attributes,
|
||||
OUT UINT64 *Result OPTIONAL
|
||||
)
|
||||
{
|
||||
switch (Operation) {
|
||||
case EfiPciIoAttributeOperationGet:
|
||||
case EfiPciIoAttributeOperationSupported:
|
||||
if (Result == NULL) {
|
||||
return EFI_INVALID_PARAMETER;
|
||||
}
|
||||
// We are not a real PCI device so just say things we kind of do
|
||||
*Result = EFI_PCI_IO_ATTRIBUTE_MEMORY | EFI_PCI_IO_ATTRIBUTE_BUS_MASTER | EFI_PCI_DEVICE_ENABLE;
|
||||
break;
|
||||
|
||||
case EfiPciIoAttributeOperationSet:
|
||||
case EfiPciIoAttributeOperationEnable:
|
||||
case EfiPciIoAttributeOperationDisable:
|
||||
// Since we are not a real PCI device no enable/set or disable operations exist.
|
||||
return EFI_SUCCESS;
|
||||
|
||||
default:
|
||||
ASSERT (FALSE);
|
||||
return EFI_INVALID_PARAMETER;
|
||||
};
|
||||
return EFI_SUCCESS;
|
||||
}
|
||||
|
||||
EFI_STATUS
|
||||
PciIoGetBarAttributes (
|
||||
IN EFI_PCI_IO_PROTOCOL *This,
|
||||
IN UINT8 BarIndex,
|
||||
OUT UINT64 *Supports, OPTIONAL
|
||||
OUT VOID **Resources OPTIONAL
|
||||
)
|
||||
{
|
||||
ASSERT (FALSE);
|
||||
return EFI_UNSUPPORTED;
|
||||
}
|
||||
|
||||
EFI_STATUS
|
||||
PciIoSetBarAttributes (
|
||||
IN EFI_PCI_IO_PROTOCOL *This,
|
||||
IN UINT64 Attributes,
|
||||
IN UINT8 BarIndex,
|
||||
IN OUT UINT64 *Offset,
|
||||
IN OUT UINT64 *Length
|
||||
)
|
||||
{
|
||||
ASSERT (FALSE);
|
||||
return EFI_UNSUPPORTED;
|
||||
}
|
||||
|
||||
EFI_PCI_IO_PROTOCOL PciIoTemplate =
|
||||
{
|
||||
PciIoPollMem,
|
||||
PciIoPollIo,
|
||||
PciIoMemRead,
|
||||
PciIoMemWrite,
|
||||
PciIoIoRead,
|
||||
PciIoIoWrite,
|
||||
PciIoPciRead,
|
||||
PciIoPciWrite,
|
||||
PciIoCopyMem,
|
||||
PciIoMap,
|
||||
PciIoUnmap,
|
||||
PciIoAllocateBuffer,
|
||||
PciIoFreeBuffer,
|
||||
PciIoFlush,
|
||||
PciIoGetLocation,
|
||||
PciIoAttributes,
|
||||
PciIoGetBarAttributes,
|
||||
PciIoSetBarAttributes,
|
||||
0,
|
||||
0
|
||||
};
|
||||
|
||||
EFI_STATUS
|
||||
EFIAPI
|
||||
PciEmulationEntryPoint (
|
||||
IN EFI_HANDLE ImageHandle,
|
||||
IN EFI_SYSTEM_TABLE *SystemTable
|
||||
)
|
||||
{
|
||||
EFI_STATUS Status;
|
||||
EFI_HANDLE Handle;
|
||||
EFI_PCI_IO_PRIVATE_DATA *Private;
|
||||
UINT8 CapabilityLength;
|
||||
UINT8 PhysicalPorts;
|
||||
UINTN Count;
|
||||
|
||||
// Get the Cpu protocol for later use
|
||||
Status = gBS->LocateProtocol(&gEfiCpuArchProtocolGuid, NULL, (VOID **)&gCpu);
|
||||
ASSERT_EFI_ERROR(Status);
|
||||
|
||||
//Configure USB host for OMAP3530.
|
||||
ConfigureUSBHost();
|
||||
|
||||
// Create a private structure
|
||||
Private = AllocatePool(sizeof(EFI_PCI_IO_PRIVATE_DATA));
|
||||
if (Private == NULL) {
|
||||
Status = EFI_OUT_OF_RESOURCES;
|
||||
return Status;
|
||||
}
|
||||
|
||||
Private->Signature = EFI_PCI_IO_PRIVATE_DATA_SIGNATURE; // Fill in signature
|
||||
Private->RootBridge.Signature = PCI_ROOT_BRIDGE_SIGNATURE; // Fake Root Bridge structure needs a signature too
|
||||
Private->RootBridge.MemoryStart = USB_EHCI_HCCAPBASE; // Get the USB capability register base
|
||||
Private->Segment = 0; // Default to segment zero
|
||||
|
||||
// Find out the capability register length and number of physical ports.
|
||||
CapabilityLength = MmioRead8(Private->RootBridge.MemoryStart);
|
||||
PhysicalPorts = (MmioRead32(Private->RootBridge.MemoryStart + 0x4)) & 0x0000000F;
|
||||
|
||||
// Calculate the total size of the USB registers.
|
||||
Private->RootBridge.MemorySize = CapabilityLength + (HOST_CONTROLLER_OPERATION_REG_SIZE + ((4 * PhysicalPorts) - 1));
|
||||
|
||||
// Enable Port Power bit in Port status and control registers in EHCI register space.
|
||||
// Port Power Control (PPC) bit in the HCSPARAMS register is already set which indicates
|
||||
// host controller implementation includes port power control.
|
||||
for (Count = 0; Count < PhysicalPorts; Count++) {
|
||||
MmioOr32((Private->RootBridge.MemoryStart + CapabilityLength + HOST_CONTROLLER_OPERATION_REG_SIZE + 4*Count), 0x00001000);
|
||||
}
|
||||
|
||||
// Create fake PCI config space.
|
||||
Private->ConfigSpace = AllocateZeroPool(sizeof(PCI_TYPE00));
|
||||
if (Private->ConfigSpace == NULL) {
|
||||
Status = EFI_OUT_OF_RESOURCES;
|
||||
FreePool(Private);
|
||||
return Status;
|
||||
}
|
||||
|
||||
// Configure PCI config space
|
||||
Private->ConfigSpace->Hdr.VendorId = 0x3530;
|
||||
Private->ConfigSpace->Hdr.DeviceId = 0x3530;
|
||||
Private->ConfigSpace->Hdr.ClassCode[0] = 0x20;
|
||||
Private->ConfigSpace->Hdr.ClassCode[1] = 0x03;
|
||||
Private->ConfigSpace->Hdr.ClassCode[2] = 0x0C;
|
||||
Private->ConfigSpace->Device.Bar[0] = Private->RootBridge.MemoryStart;
|
||||
|
||||
Handle = NULL;
|
||||
|
||||
// Unique device path.
|
||||
CopyMem(&Private->DevicePath, &PciIoDevicePathTemplate, sizeof(PciIoDevicePathTemplate));
|
||||
Private->DevicePath.AcpiDevicePath.UID = 0;
|
||||
|
||||
// Copy protocol structure
|
||||
CopyMem(&Private->PciIoProtocol, &PciIoTemplate, sizeof(PciIoTemplate));
|
||||
|
||||
Status = gBS->InstallMultipleProtocolInterfaces(&Handle,
|
||||
&gEfiPciIoProtocolGuid, &Private->PciIoProtocol,
|
||||
&gEfiDevicePathProtocolGuid, &Private->DevicePath,
|
||||
NULL);
|
||||
if (EFI_ERROR(Status)) {
|
||||
DEBUG((EFI_D_ERROR, "PciEmulationEntryPoint InstallMultipleProtocolInterfaces() failed.\n"));
|
||||
}
|
||||
|
||||
return Status;
|
||||
}
|
||||
|
||||
@ -1,305 +0,0 @@
|
||||
/** @file
|
||||
|
||||
Copyright (c) 2008-2009 Apple Inc. All rights reserved.<BR>
|
||||
|
||||
All rights reserved. This program and the accompanying materials
|
||||
are licensed and made available under the terms and conditions of the BSD License
|
||||
which accompanies this distribution. The full text of the license may be found at
|
||||
http://opensource.org/licenses/bsd-license.php
|
||||
|
||||
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
|
||||
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
|
||||
|
||||
**/
|
||||
|
||||
#ifndef _PCI_ROOT_BRIDGE_H_
|
||||
#define _PCI_ROOT_BRIDGE_H_
|
||||
|
||||
#include <PiDxe.h>
|
||||
|
||||
#include <TPS65950.h>
|
||||
|
||||
#include <Library/BaseLib.h>
|
||||
#include <Library/BaseMemoryLib.h>
|
||||
#include <Library/DebugLib.h>
|
||||
#include <Library/DxeServicesTableLib.h>
|
||||
#include <Library/IoLib.h>
|
||||
#include <Library/MemoryAllocationLib.h>
|
||||
#include <Library/PciLib.h>
|
||||
#include <Library/UefiLib.h>
|
||||
#include <Library/UefiBootServicesTableLib.h>
|
||||
#include <Library/UncachedMemoryAllocationLib.h>
|
||||
|
||||
#include <Protocol/EmbeddedExternalDevice.h>
|
||||
#include <Protocol/Cpu.h>
|
||||
#include <Protocol/DevicePath.h>
|
||||
#include <Protocol/PciIo.h>
|
||||
#include <Protocol/PciRootBridgeIo.h>
|
||||
#include <Protocol/PciHostBridgeResourceAllocation.h>
|
||||
|
||||
#include <IndustryStandard/Pci22.h>
|
||||
#include <IndustryStandard/Acpi.h>
|
||||
|
||||
extern EFI_CPU_ARCH_PROTOCOL *gCpu;
|
||||
|
||||
#define EFI_RESOURCE_NONEXISTENT 0xFFFFFFFFFFFFFFFFULL
|
||||
#define EFI_RESOURCE_LESS 0xFFFFFFFFFFFFFFFEULL
|
||||
#define EFI_RESOURCE_SATISFIED 0x0000000000000000ULL
|
||||
|
||||
|
||||
typedef struct {
|
||||
ACPI_HID_DEVICE_PATH AcpiDevicePath;
|
||||
EFI_DEVICE_PATH_PROTOCOL EndDevicePath;
|
||||
} EFI_PCI_ROOT_BRIDGE_DEVICE_PATH;
|
||||
|
||||
|
||||
#define ACPI_CONFIG_IO 0
|
||||
#define ACPI_CONFIG_MMIO 1
|
||||
#define ACPI_CONFIG_BUS 2
|
||||
|
||||
typedef struct {
|
||||
EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR Desc[3];
|
||||
EFI_ACPI_END_TAG_DESCRIPTOR EndDesc;
|
||||
} ACPI_CONFIG_INFO;
|
||||
|
||||
|
||||
#define PCI_ROOT_BRIDGE_SIGNATURE SIGNATURE_32 ('P', 'c', 'i', 'F')
|
||||
|
||||
typedef struct {
|
||||
UINT32 Signature;
|
||||
EFI_HANDLE Handle;
|
||||
EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL Io;
|
||||
EFI_PCI_ROOT_BRIDGE_DEVICE_PATH DevicePath;
|
||||
|
||||
UINT8 StartBus;
|
||||
UINT8 EndBus;
|
||||
UINT16 Type;
|
||||
UINT32 MemoryStart;
|
||||
UINT32 MemorySize;
|
||||
UINTN IoOffset;
|
||||
UINT32 IoStart;
|
||||
UINT32 IoSize;
|
||||
UINT64 PciAttributes;
|
||||
|
||||
ACPI_CONFIG_INFO *Config;
|
||||
|
||||
} PCI_ROOT_BRIDGE;
|
||||
|
||||
|
||||
#define INSTANCE_FROM_PCI_ROOT_BRIDGE_IO_THIS(a) CR (a, PCI_ROOT_BRIDGE, Io, PCI_ROOT_BRIDGE_SIGNATURE)
|
||||
|
||||
|
||||
typedef union {
|
||||
UINT8 volatile *buf;
|
||||
UINT8 volatile *ui8;
|
||||
UINT16 volatile *ui16;
|
||||
UINT32 volatile *ui32;
|
||||
UINT64 volatile *ui64;
|
||||
UINTN volatile ui;
|
||||
} PTR;
|
||||
|
||||
|
||||
typedef struct {
|
||||
EFI_PHYSICAL_ADDRESS HostAddress;
|
||||
EFI_PHYSICAL_ADDRESS DeviceAddress;
|
||||
UINTN NumberOfBytes;
|
||||
EFI_PCI_IO_PROTOCOL_OPERATION Operation;
|
||||
|
||||
} MAP_INFO_INSTANCE;
|
||||
|
||||
|
||||
typedef struct {
|
||||
EFI_PHYSICAL_ADDRESS HostAddress;
|
||||
EFI_PHYSICAL_ADDRESS DeviceAddress;
|
||||
UINTN NumberOfBytes;
|
||||
EFI_PCI_IO_PROTOCOL_OPERATION Operation;
|
||||
} PCI_DMA_MAP;
|
||||
|
||||
EFI_STATUS
|
||||
EFIAPI
|
||||
PciRootBridgeIoPollMem (
|
||||
IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,
|
||||
IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width,
|
||||
IN UINT64 Address,
|
||||
IN UINT64 Mask,
|
||||
IN UINT64 Value,
|
||||
IN UINT64 Delay,
|
||||
OUT UINT64 *Result
|
||||
);
|
||||
|
||||
EFI_STATUS
|
||||
EFIAPI
|
||||
PciRootBridgeIoPollIo (
|
||||
IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,
|
||||
IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width,
|
||||
IN UINT64 Address,
|
||||
IN UINT64 Mask,
|
||||
IN UINT64 Value,
|
||||
IN UINT64 Delay,
|
||||
OUT UINT64 *Result
|
||||
);
|
||||
|
||||
EFI_STATUS
|
||||
EFIAPI
|
||||
PciRootBridgeIoMemRead (
|
||||
IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,
|
||||
IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width,
|
||||
IN UINT64 Address,
|
||||
IN UINTN Count,
|
||||
IN OUT VOID *Buffer
|
||||
);
|
||||
|
||||
EFI_STATUS
|
||||
EFIAPI
|
||||
PciRootBridgeIoMemWrite (
|
||||
IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,
|
||||
IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width,
|
||||
IN UINT64 Address,
|
||||
IN UINTN Count,
|
||||
IN OUT VOID *Buffer
|
||||
);
|
||||
|
||||
EFI_STATUS
|
||||
EFIAPI
|
||||
PciRootBridgeIoIoRead (
|
||||
IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,
|
||||
IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width,
|
||||
IN UINT64 UserAddress,
|
||||
IN UINTN Count,
|
||||
IN OUT VOID *UserBuffer
|
||||
);
|
||||
|
||||
EFI_STATUS
|
||||
EFIAPI
|
||||
PciRootBridgeIoIoWrite (
|
||||
IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,
|
||||
IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width,
|
||||
IN UINT64 UserAddress,
|
||||
IN UINTN Count,
|
||||
IN OUT VOID *UserBuffer
|
||||
);
|
||||
|
||||
EFI_STATUS
|
||||
EFIAPI
|
||||
PciRootBridgeIoCopyMem (
|
||||
IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,
|
||||
IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width,
|
||||
IN UINT64 DestAddress,
|
||||
IN UINT64 SrcAddress,
|
||||
IN UINTN Count
|
||||
);
|
||||
|
||||
EFI_STATUS
|
||||
EFIAPI
|
||||
PciRootBridgeIoPciRead (
|
||||
IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,
|
||||
IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width,
|
||||
IN UINT64 Address,
|
||||
IN UINTN Count,
|
||||
IN OUT VOID *Buffer
|
||||
);
|
||||
|
||||
EFI_STATUS
|
||||
EFIAPI
|
||||
PciRootBridgeIoPciWrite (
|
||||
IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,
|
||||
IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width,
|
||||
IN UINT64 Address,
|
||||
IN UINTN Count,
|
||||
IN OUT VOID *Buffer
|
||||
);
|
||||
|
||||
EFI_STATUS
|
||||
EFIAPI
|
||||
PciRootBridgeIoMap (
|
||||
IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,
|
||||
IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_OPERATION Operation,
|
||||
IN VOID *HostAddress,
|
||||
IN OUT UINTN *NumberOfBytes,
|
||||
OUT EFI_PHYSICAL_ADDRESS *DeviceAddress,
|
||||
OUT VOID **Mapping
|
||||
);
|
||||
|
||||
EFI_STATUS
|
||||
EFIAPI
|
||||
PciRootBridgeIoUnmap (
|
||||
IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,
|
||||
IN VOID *Mapping
|
||||
);
|
||||
|
||||
EFI_STATUS
|
||||
EFIAPI
|
||||
PciRootBridgeIoAllocateBuffer (
|
||||
IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,
|
||||
IN EFI_ALLOCATE_TYPE Type,
|
||||
IN EFI_MEMORY_TYPE MemoryType,
|
||||
IN UINTN Pages,
|
||||
OUT VOID **HostAddress,
|
||||
IN UINT64 Attributes
|
||||
);
|
||||
|
||||
EFI_STATUS
|
||||
EFIAPI
|
||||
PciRootBridgeIoFreeBuffer (
|
||||
IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,
|
||||
IN UINTN Pages,
|
||||
OUT VOID *HostAddress
|
||||
);
|
||||
|
||||
EFI_STATUS
|
||||
EFIAPI
|
||||
PciRootBridgeIoFlush (
|
||||
IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This
|
||||
);
|
||||
|
||||
EFI_STATUS
|
||||
EFIAPI
|
||||
PciRootBridgeIoGetAttributes (
|
||||
IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,
|
||||
OUT UINT64 *Supported,
|
||||
OUT UINT64 *Attributes
|
||||
);
|
||||
|
||||
EFI_STATUS
|
||||
EFIAPI
|
||||
PciRootBridgeIoSetAttributes (
|
||||
IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,
|
||||
IN UINT64 Attributes,
|
||||
IN OUT UINT64 *ResourceBase,
|
||||
IN OUT UINT64 *ResourceLength
|
||||
);
|
||||
|
||||
EFI_STATUS
|
||||
EFIAPI
|
||||
PciRootBridgeIoConfiguration (
|
||||
IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,
|
||||
OUT VOID **Resources
|
||||
);
|
||||
|
||||
//
|
||||
// Private Function Prototypes
|
||||
//
|
||||
EFI_STATUS
|
||||
EFIAPI
|
||||
PciRootBridgeIoMemRW (
|
||||
IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width,
|
||||
IN UINTN Count,
|
||||
IN BOOLEAN InStrideFlag,
|
||||
IN PTR In,
|
||||
IN BOOLEAN OutStrideFlag,
|
||||
OUT PTR Out
|
||||
);
|
||||
|
||||
BOOLEAN
|
||||
PciIoMemAddressValid (
|
||||
IN EFI_PCI_IO_PROTOCOL *This,
|
||||
IN UINT64 Address
|
||||
);
|
||||
|
||||
EFI_STATUS
|
||||
EmulatePciIoForEhci (
|
||||
INTN MvPciIfMaxIf
|
||||
);
|
||||
|
||||
#endif
|
||||
|
||||
@ -1,58 +0,0 @@
|
||||
/** @file
|
||||
|
||||
Copyright (c) 2009 Apple, Inc. All rights reserved.
|
||||
|
||||
All rights reserved. This program and the accompanying materials
|
||||
are licensed and made available under the terms and conditions of the BSD License
|
||||
which accompanies this distribution. The full text of the license may be found at
|
||||
http://opensource.org/licenses/bsd-license.php
|
||||
|
||||
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
|
||||
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
|
||||
|
||||
**/
|
||||
|
||||
[Defines]
|
||||
INF_VERSION = 0x00010005
|
||||
BASE_NAME = BeagleBoardPciEmulation
|
||||
FILE_GUID = feaa2e2b-53ac-4d5e-ae10-1efd5da4a2ba
|
||||
MODULE_TYPE = DXE_DRIVER
|
||||
VERSION_STRING = 1.0
|
||||
|
||||
ENTRY_POINT = PciEmulationEntryPoint
|
||||
|
||||
[Sources.common]
|
||||
PciRootBridgeIo.c
|
||||
PciEmulation.c
|
||||
|
||||
[Packages]
|
||||
MdePkg/MdePkg.dec
|
||||
MdeModulePkg/MdeModulePkg.dec
|
||||
IntelFrameworkPkg/IntelFrameworkPkg.dec
|
||||
ArmPkg/ArmPkg.dec
|
||||
EmbeddedPkg/EmbeddedPkg.dec
|
||||
BeagleBoardPkg/BeagleBoardPkg.dec
|
||||
|
||||
[LibraryClasses]
|
||||
BaseLib
|
||||
DxeServicesTableLib
|
||||
UefiLib
|
||||
UefiBootServicesTableLib
|
||||
UefiDriverEntryPoint
|
||||
UefiRuntimeServicesTableLib
|
||||
UncachedMemoryAllocationLib
|
||||
IoLib
|
||||
|
||||
[Protocols]
|
||||
gEfiPciRootBridgeIoProtocolGuid
|
||||
gEfiDevicePathProtocolGuid
|
||||
gEfiPciHostBridgeResourceAllocationProtocolGuid
|
||||
gEfiCpuArchProtocolGuid
|
||||
gEfiPciIoProtocolGuid
|
||||
gEmbeddedExternalDeviceProtocolGuid
|
||||
|
||||
[Depex]
|
||||
gEfiMetronomeArchProtocolGuid AND
|
||||
gEfiCpuArchProtocolGuid AND
|
||||
gEmbeddedExternalDeviceProtocolGuid
|
||||
|
||||
@ -1,306 +0,0 @@
|
||||
/** @file
|
||||
|
||||
Copyright (c) 2008-2009, Apple Inc. All rights reserved.
|
||||
|
||||
All rights reserved. This program and the accompanying materials
|
||||
are licensed and made available under the terms and conditions of the BSD License
|
||||
which accompanies this distribution. The full text of the license may be found at
|
||||
http://opensource.org/licenses/bsd-license.php
|
||||
|
||||
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
|
||||
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
|
||||
|
||||
**/
|
||||
|
||||
#include "PciEmulation.h"
|
||||
|
||||
BOOLEAN
|
||||
PciRootBridgeMemAddressValid (
|
||||
IN PCI_ROOT_BRIDGE *Private,
|
||||
IN UINT64 Address
|
||||
)
|
||||
{
|
||||
if ((Address >= Private->MemoryStart) && (Address < (Private->MemoryStart + Private->MemorySize))) {
|
||||
return TRUE;
|
||||
}
|
||||
|
||||
return FALSE;
|
||||
}
|
||||
|
||||
|
||||
EFI_STATUS
|
||||
PciRootBridgeIoMemRW (
|
||||
IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width,
|
||||
IN UINTN Count,
|
||||
IN BOOLEAN InStrideFlag,
|
||||
IN PTR In,
|
||||
IN BOOLEAN OutStrideFlag,
|
||||
OUT PTR Out
|
||||
)
|
||||
{
|
||||
UINTN Stride;
|
||||
UINTN InStride;
|
||||
UINTN OutStride;
|
||||
|
||||
|
||||
Width = (EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH) (Width & 0x03);
|
||||
Stride = (UINTN)1 << Width;
|
||||
InStride = InStrideFlag ? Stride : 0;
|
||||
OutStride = OutStrideFlag ? Stride : 0;
|
||||
|
||||
//
|
||||
// Loop for each iteration and move the data
|
||||
//
|
||||
switch (Width) {
|
||||
case EfiPciWidthUint8:
|
||||
for (;Count > 0; Count--, In.buf += InStride, Out.buf += OutStride) {
|
||||
*In.ui8 = *Out.ui8;
|
||||
}
|
||||
break;
|
||||
case EfiPciWidthUint16:
|
||||
for (;Count > 0; Count--, In.buf += InStride, Out.buf += OutStride) {
|
||||
*In.ui16 = *Out.ui16;
|
||||
}
|
||||
break;
|
||||
case EfiPciWidthUint32:
|
||||
for (;Count > 0; Count--, In.buf += InStride, Out.buf += OutStride) {
|
||||
*In.ui32 = *Out.ui32;
|
||||
}
|
||||
break;
|
||||
default:
|
||||
return EFI_INVALID_PARAMETER;
|
||||
}
|
||||
|
||||
return EFI_SUCCESS;
|
||||
}
|
||||
|
||||
EFI_STATUS
|
||||
PciRootBridgeIoPciRW (
|
||||
IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,
|
||||
IN BOOLEAN Write,
|
||||
IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width,
|
||||
IN UINT64 UserAddress,
|
||||
IN UINTN Count,
|
||||
IN OUT VOID *UserBuffer
|
||||
)
|
||||
{
|
||||
return EFI_SUCCESS;
|
||||
}
|
||||
|
||||
/**
|
||||
Enables a PCI driver to access PCI controller registers in the PCI root bridge memory space.
|
||||
|
||||
@param This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
|
||||
@param Width Signifies the width of the memory operations.
|
||||
@param Address The base address of the memory operations.
|
||||
@param Count The number of memory operations to perform.
|
||||
@param Buffer For read operations, the destination buffer to store the results. For write
|
||||
operations, the source buffer to write data from.
|
||||
|
||||
@retval EFI_SUCCESS The data was read from or written to the PCI root bridge.
|
||||
@retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.
|
||||
@retval EFI_INVALID_PARAMETER One or more parameters are invalid.
|
||||
|
||||
**/
|
||||
EFI_STATUS
|
||||
EFIAPI
|
||||
PciRootBridgeIoMemRead (
|
||||
IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,
|
||||
IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width,
|
||||
IN UINT64 Address,
|
||||
IN UINTN Count,
|
||||
IN OUT VOID *Buffer
|
||||
)
|
||||
{
|
||||
PCI_ROOT_BRIDGE *Private;
|
||||
UINTN AlignMask;
|
||||
PTR In;
|
||||
PTR Out;
|
||||
|
||||
if ( Buffer == NULL ) {
|
||||
return EFI_INVALID_PARAMETER;
|
||||
}
|
||||
|
||||
Private = INSTANCE_FROM_PCI_ROOT_BRIDGE_IO_THIS (This);
|
||||
|
||||
if (!PciRootBridgeMemAddressValid (Private, Address)) {
|
||||
return EFI_INVALID_PARAMETER;
|
||||
}
|
||||
|
||||
AlignMask = (1 << (Width & 0x03)) - 1;
|
||||
if (Address & AlignMask) {
|
||||
return EFI_INVALID_PARAMETER;
|
||||
}
|
||||
|
||||
In.buf = Buffer;
|
||||
Out.buf = (VOID *)(UINTN) Address;
|
||||
|
||||
switch (Width) {
|
||||
case EfiPciWidthUint8:
|
||||
case EfiPciWidthUint16:
|
||||
case EfiPciWidthUint32:
|
||||
case EfiPciWidthUint64:
|
||||
return PciRootBridgeIoMemRW (Width, Count, TRUE, In, TRUE, Out);
|
||||
|
||||
case EfiPciWidthFifoUint8:
|
||||
case EfiPciWidthFifoUint16:
|
||||
case EfiPciWidthFifoUint32:
|
||||
case EfiPciWidthFifoUint64:
|
||||
return PciRootBridgeIoMemRW (Width, Count, TRUE, In, FALSE, Out);
|
||||
|
||||
case EfiPciWidthFillUint8:
|
||||
case EfiPciWidthFillUint16:
|
||||
case EfiPciWidthFillUint32:
|
||||
case EfiPciWidthFillUint64:
|
||||
return PciRootBridgeIoMemRW (Width, Count, FALSE, In, TRUE, Out);
|
||||
|
||||
default:
|
||||
break;
|
||||
}
|
||||
|
||||
return EFI_INVALID_PARAMETER;
|
||||
}
|
||||
|
||||
|
||||
|
||||
/**
|
||||
Enables a PCI driver to access PCI controller registers in the PCI root bridge memory space.
|
||||
|
||||
@param This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
|
||||
@param Width Signifies the width of the memory operations.
|
||||
@param Address The base address of the memory operations.
|
||||
@param Count The number of memory operations to perform.
|
||||
@param Buffer For read operations, the destination buffer to store the results. For write
|
||||
operations, the source buffer to write data from.
|
||||
|
||||
@retval EFI_SUCCESS The data was read from or written to the PCI root bridge.
|
||||
@retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.
|
||||
@retval EFI_INVALID_PARAMETER One or more parameters are invalid.
|
||||
|
||||
**/
|
||||
EFI_STATUS
|
||||
EFIAPI
|
||||
PciRootBridgeIoMemWrite (
|
||||
IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,
|
||||
IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width,
|
||||
IN UINT64 Address,
|
||||
IN UINTN Count,
|
||||
IN OUT VOID *Buffer
|
||||
)
|
||||
{
|
||||
PCI_ROOT_BRIDGE *Private;
|
||||
UINTN AlignMask;
|
||||
PTR In;
|
||||
PTR Out;
|
||||
|
||||
if ( Buffer == NULL ) {
|
||||
return EFI_INVALID_PARAMETER;
|
||||
}
|
||||
|
||||
Private = INSTANCE_FROM_PCI_ROOT_BRIDGE_IO_THIS (This);
|
||||
|
||||
if (!PciRootBridgeMemAddressValid (Private, Address)) {
|
||||
return EFI_INVALID_PARAMETER;
|
||||
}
|
||||
|
||||
AlignMask = (1 << (Width & 0x03)) - 1;
|
||||
if (Address & AlignMask) {
|
||||
return EFI_INVALID_PARAMETER;
|
||||
}
|
||||
|
||||
In.buf = (VOID *)(UINTN) Address;
|
||||
Out.buf = Buffer;
|
||||
|
||||
switch (Width) {
|
||||
case EfiPciWidthUint8:
|
||||
case EfiPciWidthUint16:
|
||||
case EfiPciWidthUint32:
|
||||
case EfiPciWidthUint64:
|
||||
return PciRootBridgeIoMemRW (Width, Count, TRUE, In, TRUE, Out);
|
||||
|
||||
case EfiPciWidthFifoUint8:
|
||||
case EfiPciWidthFifoUint16:
|
||||
case EfiPciWidthFifoUint32:
|
||||
case EfiPciWidthFifoUint64:
|
||||
return PciRootBridgeIoMemRW (Width, Count, FALSE, In, TRUE, Out);
|
||||
|
||||
case EfiPciWidthFillUint8:
|
||||
case EfiPciWidthFillUint16:
|
||||
case EfiPciWidthFillUint32:
|
||||
case EfiPciWidthFillUint64:
|
||||
return PciRootBridgeIoMemRW (Width, Count, TRUE, In, FALSE, Out);
|
||||
|
||||
default:
|
||||
break;
|
||||
}
|
||||
|
||||
return EFI_INVALID_PARAMETER;
|
||||
}
|
||||
|
||||
/**
|
||||
Enables a PCI driver to access PCI controller registers in the PCI root bridge memory space.
|
||||
|
||||
@param This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
|
||||
@param Width Signifies the width of the memory operations.
|
||||
@param Address The base address of the memory operations.
|
||||
@param Count The number of memory operations to perform.
|
||||
@param Buffer For read operations, the destination buffer to store the results. For write
|
||||
operations, the source buffer to write data from.
|
||||
|
||||
@retval EFI_SUCCESS The data was read from or written to the PCI root bridge.
|
||||
@retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.
|
||||
@retval EFI_INVALID_PARAMETER One or more parameters are invalid.
|
||||
|
||||
**/
|
||||
EFI_STATUS
|
||||
EFIAPI
|
||||
PciRootBridgeIoPciRead (
|
||||
IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,
|
||||
IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width,
|
||||
IN UINT64 Address,
|
||||
IN UINTN Count,
|
||||
IN OUT VOID *Buffer
|
||||
)
|
||||
{
|
||||
if (Buffer == NULL) {
|
||||
return EFI_INVALID_PARAMETER;
|
||||
}
|
||||
|
||||
return PciRootBridgeIoPciRW (This, FALSE, Width, Address, Count, Buffer);
|
||||
}
|
||||
|
||||
|
||||
|
||||
/**
|
||||
Enables a PCI driver to access PCI controller registers in the PCI root bridge memory space.
|
||||
|
||||
@param This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
|
||||
@param Width Signifies the width of the memory operations.
|
||||
@param Address The base address of the memory operations.
|
||||
@param Count The number of memory operations to perform.
|
||||
@param Buffer For read operations, the destination buffer to store the results. For write
|
||||
operations, the source buffer to write data from.
|
||||
|
||||
@retval EFI_SUCCESS The data was read from or written to the PCI root bridge.
|
||||
@retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.
|
||||
@retval EFI_INVALID_PARAMETER One or more parameters are invalid.
|
||||
|
||||
**/
|
||||
EFI_STATUS
|
||||
EFIAPI
|
||||
PciRootBridgeIoPciWrite (
|
||||
IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,
|
||||
IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width,
|
||||
IN UINT64 Address,
|
||||
IN UINTN Count,
|
||||
IN OUT VOID *Buffer
|
||||
)
|
||||
{
|
||||
if (Buffer == NULL) {
|
||||
return EFI_INVALID_PARAMETER;
|
||||
}
|
||||
|
||||
return PciRootBridgeIoPciRW (This, TRUE, Width, Address, Count, Buffer);
|
||||
}
|
||||
|
||||
|
||||
@ -36,7 +36,7 @@
|
||||
MdeModulePkg/MdeModulePkg.dec
|
||||
EmbeddedPkg/EmbeddedPkg.dec
|
||||
ArmPkg/ArmPkg.dec
|
||||
BeagleBoardPkg/BeagleBoardPkg.dec
|
||||
Omap35xxPkg/Omap35xxPkg.dec
|
||||
|
||||
[LibraryClasses]
|
||||
BaseLib
|
||||
@ -59,7 +59,7 @@
|
||||
gEmbeddedTokenSpaceGuid.PcdPrePiStackSize
|
||||
gEmbeddedTokenSpaceGuid.PcdPrePiStackBase
|
||||
|
||||
gBeagleBoardTokenSpaceGuid.PcdBeagleConsoleUart
|
||||
gBeagleBoardTokenSpaceGuid.PcdBeagleFreeTimer
|
||||
gBeagleBoardTokenSpaceGuid.PcdBeagleBoardIRAMFullSize
|
||||
gOmap35xxTokenSpaceGuid.PcdBeagleConsoleUart
|
||||
gOmap35xxTokenSpaceGuid.PcdBeagleFreeTimer
|
||||
gOmap35xxTokenSpaceGuid.PcdBeagleBoardIRAMFullSize
|
||||
|
||||
|
||||
@ -1,325 +0,0 @@
|
||||
/** @file
|
||||
|
||||
Copyright (c) 2008-2009, Apple Inc. All rights reserved.
|
||||
|
||||
All rights reserved. This program and the accompanying materials
|
||||
are licensed and made available under the terms and conditions of the BSD License
|
||||
which accompanies this distribution. The full text of the license may be found at
|
||||
http://opensource.org/licenses/bsd-license.php
|
||||
|
||||
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
|
||||
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
|
||||
|
||||
**/
|
||||
|
||||
#include <Uefi.h>
|
||||
#include <Omap3530/Omap3530.h>
|
||||
|
||||
#include <Library/DebugLib.h>
|
||||
#include <Library/IoLib.h>
|
||||
#include <Library/UefiBootServicesTableLib.h>
|
||||
|
||||
#include <Protocol/SmbusHc.h>
|
||||
|
||||
#define MAX_RETRY 1000
|
||||
|
||||
//
|
||||
// Internal Functions
|
||||
//
|
||||
STATIC
|
||||
EFI_STATUS
|
||||
WaitForBusBusy (
|
||||
VOID
|
||||
)
|
||||
{
|
||||
UINTN Retry = 0;
|
||||
|
||||
while (++Retry < MAX_RETRY && (MmioRead16(I2C_STAT) & BB) == 0x1);
|
||||
|
||||
if (Retry == MAX_RETRY) {
|
||||
return EFI_TIMEOUT;
|
||||
}
|
||||
|
||||
return EFI_SUCCESS;
|
||||
}
|
||||
|
||||
STATIC
|
||||
EFI_STATUS
|
||||
PollForStatus(
|
||||
UINT16 StatusBit
|
||||
)
|
||||
{
|
||||
UINTN Retry = 0;
|
||||
|
||||
while(Retry < MAX_RETRY) {
|
||||
if (MmioRead16(I2C_STAT) & StatusBit) {
|
||||
//Clear particular status bit from Status register.
|
||||
MmioOr16(I2C_STAT, StatusBit);
|
||||
break;
|
||||
}
|
||||
Retry++;
|
||||
}
|
||||
|
||||
if (Retry == MAX_RETRY) {
|
||||
return EFI_TIMEOUT;
|
||||
}
|
||||
|
||||
return EFI_SUCCESS;
|
||||
}
|
||||
|
||||
STATIC
|
||||
EFI_STATUS
|
||||
ConfigureI2c (
|
||||
VOID
|
||||
)
|
||||
{
|
||||
//Program prescaler to obtain 12-MHz clock
|
||||
MmioWrite16(I2C_PSC, 0x0000);
|
||||
|
||||
//Program SCLL and SCLH
|
||||
//NOTE: Following values are the register dump after U-Boot code executed.
|
||||
//We need to figure out how its calculated based on the I2C functional clock and I2C_PSC.
|
||||
MmioWrite16(I2C_SCLL, 0x0035);
|
||||
MmioWrite16(I2C_SCLH, 0x0035);
|
||||
|
||||
//Take the I2C controller out of reset.
|
||||
MmioOr16(I2C_CON, I2C_EN);
|
||||
|
||||
//Initialize the I2C controller.
|
||||
|
||||
//Set I2C controller in Master mode.
|
||||
MmioOr16(I2C_CON, MST);
|
||||
|
||||
//Enable interrupts for receive/transmit mode.
|
||||
MmioOr16(I2C_IE, (XRDY_IE | RRDY_IE | ARDY_IE | NACK_IE));
|
||||
|
||||
return EFI_SUCCESS;
|
||||
}
|
||||
|
||||
STATIC
|
||||
EFI_STATUS
|
||||
I2CReadOneByte (
|
||||
UINT8 *Data
|
||||
)
|
||||
{
|
||||
EFI_STATUS Status;
|
||||
|
||||
//I2C bus status checking
|
||||
Status = WaitForBusBusy();
|
||||
if (EFI_ERROR(Status)) {
|
||||
return Status;
|
||||
}
|
||||
|
||||
//Poll till Receive ready bit is set.
|
||||
Status = PollForStatus(RRDY);
|
||||
if (EFI_ERROR(Status)) {
|
||||
return Status;
|
||||
}
|
||||
|
||||
*Data = MmioRead8(I2C_DATA);
|
||||
|
||||
return EFI_SUCCESS;
|
||||
}
|
||||
|
||||
STATIC
|
||||
EFI_STATUS
|
||||
I2CWriteOneByte (
|
||||
UINT8 Data
|
||||
)
|
||||
{
|
||||
EFI_STATUS Status;
|
||||
|
||||
//I2C bus status checking
|
||||
Status = WaitForBusBusy();
|
||||
if (EFI_ERROR(Status)) {
|
||||
return Status;
|
||||
}
|
||||
|
||||
//Data transfer
|
||||
//Poll till Transmit ready bit is set
|
||||
Status = PollForStatus(XRDY);
|
||||
if (EFI_ERROR(Status)) {
|
||||
return Status;
|
||||
}
|
||||
|
||||
MmioWrite8(I2C_DATA, Data);
|
||||
|
||||
//Wait and check if the NACK is not set.
|
||||
gBS->Stall(1000);
|
||||
if (MmioRead16(I2C_STAT) & NACK) {
|
||||
return EFI_DEVICE_ERROR;
|
||||
}
|
||||
|
||||
return EFI_SUCCESS;
|
||||
}
|
||||
|
||||
STATIC
|
||||
EFI_STATUS
|
||||
SmbusBlockRead (
|
||||
OUT UINT8 *Buffer,
|
||||
IN UINTN Length
|
||||
)
|
||||
{
|
||||
UINTN Index = 0;
|
||||
EFI_STATUS Status = EFI_SUCCESS;
|
||||
|
||||
//Transfer configuration for receiving data.
|
||||
MmioWrite16(I2C_CNT, Length);
|
||||
//Need stop bit before sending data.
|
||||
MmioWrite16(I2C_CON, (I2C_EN | MST | STP | STT));
|
||||
|
||||
while (Index < Length) {
|
||||
//Read a byte
|
||||
Status = I2CReadOneByte(&Buffer[Index++]);
|
||||
if (EFI_ERROR(Status)) {
|
||||
return Status;
|
||||
}
|
||||
}
|
||||
|
||||
//Transfer completion
|
||||
Status = PollForStatus(ARDY);
|
||||
if (EFI_ERROR(Status)) {
|
||||
return Status;
|
||||
}
|
||||
|
||||
return Status;
|
||||
}
|
||||
|
||||
STATIC
|
||||
EFI_STATUS
|
||||
SmbusBlockWrite (
|
||||
IN UINT8 *Buffer,
|
||||
IN UINTN Length
|
||||
)
|
||||
{
|
||||
UINTN Index = 0;
|
||||
EFI_STATUS Status = EFI_SUCCESS;
|
||||
|
||||
//Transfer configuration for transmitting data
|
||||
MmioWrite16(I2C_CNT, Length);
|
||||
MmioWrite16(I2C_CON, (I2C_EN | TRX | MST | STT | STP));
|
||||
|
||||
while (Index < Length) {
|
||||
//Send a byte
|
||||
Status = I2CWriteOneByte(Buffer[Index++]);
|
||||
if (EFI_ERROR(Status)) {
|
||||
return Status;
|
||||
}
|
||||
}
|
||||
|
||||
//Transfer completion
|
||||
Status = PollForStatus(ARDY);
|
||||
if (EFI_ERROR(Status)) {
|
||||
return Status;
|
||||
}
|
||||
|
||||
return Status;
|
||||
}
|
||||
|
||||
//
|
||||
// Public Functions.
|
||||
//
|
||||
EFI_STATUS
|
||||
EFIAPI
|
||||
SmbusExecute (
|
||||
IN CONST EFI_SMBUS_HC_PROTOCOL *This,
|
||||
IN CONST EFI_SMBUS_DEVICE_ADDRESS SlaveAddress,
|
||||
IN CONST EFI_SMBUS_DEVICE_COMMAND Command,
|
||||
IN CONST EFI_SMBUS_OPERATION Operation,
|
||||
IN CONST BOOLEAN PecCheck,
|
||||
IN OUT UINTN *Length,
|
||||
IN OUT VOID *Buffer
|
||||
)
|
||||
{
|
||||
UINT8 *ByteBuffer = Buffer;
|
||||
EFI_STATUS Status = EFI_SUCCESS;
|
||||
UINT8 SlaveAddr = (UINT8)(SlaveAddress.SmbusDeviceAddress);
|
||||
|
||||
if (PecCheck) {
|
||||
return EFI_UNSUPPORTED;
|
||||
}
|
||||
|
||||
if ((Operation != EfiSmbusWriteBlock) && (Operation != EfiSmbusReadBlock)) {
|
||||
return EFI_UNSUPPORTED;
|
||||
}
|
||||
|
||||
//Set the Slave address.
|
||||
MmioWrite16(I2C_SA, SlaveAddr);
|
||||
|
||||
if (Operation == EfiSmbusReadBlock) {
|
||||
Status = SmbusBlockRead(ByteBuffer, *Length);
|
||||
} else if (Operation == EfiSmbusWriteBlock) {
|
||||
Status = SmbusBlockWrite(ByteBuffer, *Length);
|
||||
}
|
||||
|
||||
return Status;
|
||||
}
|
||||
|
||||
EFI_STATUS
|
||||
EFIAPI
|
||||
SmbusArpDevice (
|
||||
IN CONST EFI_SMBUS_HC_PROTOCOL *This,
|
||||
IN CONST BOOLEAN ArpAll,
|
||||
IN CONST EFI_SMBUS_UDID *SmbusUdid OPTIONAL,
|
||||
IN OUT EFI_SMBUS_DEVICE_ADDRESS *SlaveAddress OPTIONAL
|
||||
)
|
||||
{
|
||||
return EFI_UNSUPPORTED;
|
||||
}
|
||||
|
||||
|
||||
EFI_STATUS
|
||||
EFIAPI
|
||||
SmbusGetArpMap (
|
||||
IN CONST EFI_SMBUS_HC_PROTOCOL *This,
|
||||
IN OUT UINTN *Length,
|
||||
IN OUT EFI_SMBUS_DEVICE_MAP **SmbusDeviceMap
|
||||
)
|
||||
{
|
||||
return EFI_UNSUPPORTED;
|
||||
}
|
||||
|
||||
|
||||
EFI_STATUS
|
||||
EFIAPI
|
||||
SmbusNotify (
|
||||
IN CONST EFI_SMBUS_HC_PROTOCOL *This,
|
||||
IN CONST EFI_SMBUS_DEVICE_ADDRESS SlaveAddress,
|
||||
IN CONST UINTN Data,
|
||||
IN CONST EFI_SMBUS_NOTIFY_FUNCTION NotifyFunction
|
||||
)
|
||||
{
|
||||
return EFI_UNSUPPORTED;
|
||||
}
|
||||
|
||||
EFI_SMBUS_HC_PROTOCOL SmbusProtocol =
|
||||
{
|
||||
SmbusExecute,
|
||||
SmbusArpDevice,
|
||||
SmbusGetArpMap,
|
||||
SmbusNotify
|
||||
};
|
||||
|
||||
EFI_STATUS
|
||||
InitializeSmbus (
|
||||
IN EFI_HANDLE ImageHandle,
|
||||
IN EFI_SYSTEM_TABLE *SystemTable
|
||||
)
|
||||
{
|
||||
EFI_HANDLE Handle = NULL;
|
||||
EFI_STATUS Status;
|
||||
|
||||
//Configure I2C controller.
|
||||
Status = ConfigureI2c();
|
||||
if (EFI_ERROR(Status)) {
|
||||
DEBUG ((EFI_D_ERROR, "InitializeI2c fails.\n"));
|
||||
return Status;
|
||||
}
|
||||
|
||||
// Install the SMBUS interface
|
||||
Status = gBS->InstallMultipleProtocolInterfaces(&Handle, &gEfiSmbusHcProtocolGuid, &SmbusProtocol, NULL);
|
||||
ASSERT_EFI_ERROR(Status);
|
||||
|
||||
return Status;
|
||||
}
|
||||
|
||||
@ -1,45 +0,0 @@
|
||||
#/** @file
|
||||
#
|
||||
# Copyright (c) 2008 - 2010, Apple Inc. All rights reserved.
|
||||
# All rights reserved. This program and the accompanying materials
|
||||
# are licensed and made available under the terms and conditions of the BSD License
|
||||
# which accompanies this distribution. The full text of the license may be found at
|
||||
# http://opensource.org/licenses/bsd-license.php
|
||||
#
|
||||
# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
|
||||
# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
|
||||
#
|
||||
#**/
|
||||
|
||||
[Defines]
|
||||
INF_VERSION = 0x00010005
|
||||
BASE_NAME = Smbus
|
||||
FILE_GUID = d5125e0f-1226-444f-a218-0085996ed5da
|
||||
MODULE_TYPE = DXE_DRIVER
|
||||
VERSION_STRING = 1.0
|
||||
|
||||
ENTRY_POINT = InitializeSmbus
|
||||
|
||||
[Sources.common]
|
||||
Smbus.c
|
||||
|
||||
[Packages]
|
||||
MdePkg/MdePkg.dec
|
||||
BeagleBoardPkg/BeagleBoardPkg.dec
|
||||
|
||||
[LibraryClasses]
|
||||
PcdLib
|
||||
UefiLib
|
||||
UefiDriverEntryPoint
|
||||
MemoryAllocationLib
|
||||
IoLib
|
||||
|
||||
[Guids]
|
||||
|
||||
[Protocols]
|
||||
gEfiSmbusHcProtocolGuid
|
||||
|
||||
[Pcd]
|
||||
|
||||
[depex]
|
||||
TRUE
|
||||
@ -1,116 +0,0 @@
|
||||
/** @file
|
||||
|
||||
Copyright (c) 2008-2009, Apple Inc. All rights reserved.
|
||||
|
||||
All rights reserved. This program and the accompanying materials
|
||||
are licensed and made available under the terms and conditions of the BSD License
|
||||
which accompanies this distribution. The full text of the license may be found at
|
||||
http://opensource.org/licenses/bsd-license.php
|
||||
|
||||
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
|
||||
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
|
||||
|
||||
**/
|
||||
|
||||
#include <Uefi.h>
|
||||
|
||||
#include <TPS65950.h>
|
||||
|
||||
#include <Library/BaseMemoryLib.h>
|
||||
#include <Library/DebugLib.h>
|
||||
#include <Library/MemoryAllocationLib.h>
|
||||
#include <Library/UefiBootServicesTableLib.h>
|
||||
|
||||
#include <Protocol/EmbeddedExternalDevice.h>
|
||||
#include <Protocol/SmbusHc.h>
|
||||
|
||||
EFI_SMBUS_HC_PROTOCOL *Smbus;
|
||||
|
||||
EFI_STATUS
|
||||
Read (
|
||||
IN EMBEDDED_EXTERNAL_DEVICE *This,
|
||||
IN UINTN Register,
|
||||
IN UINTN Length,
|
||||
OUT VOID *Buffer
|
||||
)
|
||||
{
|
||||
EFI_STATUS Status;
|
||||
EFI_SMBUS_DEVICE_ADDRESS SlaveAddress;
|
||||
UINT8 DeviceRegister;
|
||||
UINTN DeviceRegisterLength = 1;
|
||||
|
||||
SlaveAddress.SmbusDeviceAddress = EXTERNAL_DEVICE_REGISTER_TO_SLAVE_ADDRESS(Register);
|
||||
DeviceRegister = (UINT8)EXTERNAL_DEVICE_REGISTER_TO_REGISTER(Register);
|
||||
|
||||
//Write DeviceRegister.
|
||||
Status = Smbus->Execute(Smbus, SlaveAddress, 0, EfiSmbusWriteBlock, FALSE, &DeviceRegisterLength, &DeviceRegister);
|
||||
if (EFI_ERROR(Status)) {
|
||||
return Status;
|
||||
}
|
||||
|
||||
//Read Data
|
||||
Status = Smbus->Execute(Smbus, SlaveAddress, 0, EfiSmbusReadBlock, FALSE, &Length, Buffer);
|
||||
return Status;
|
||||
}
|
||||
|
||||
EFI_STATUS
|
||||
Write (
|
||||
IN EMBEDDED_EXTERNAL_DEVICE *This,
|
||||
IN UINTN Register,
|
||||
IN UINTN Length,
|
||||
IN VOID *Buffer
|
||||
)
|
||||
{
|
||||
EFI_STATUS Status;
|
||||
EFI_SMBUS_DEVICE_ADDRESS SlaveAddress;
|
||||
UINT8 DeviceRegister;
|
||||
UINTN DeviceBufferLength = Length + 1;
|
||||
UINT8 *DeviceBuffer;
|
||||
|
||||
SlaveAddress.SmbusDeviceAddress = EXTERNAL_DEVICE_REGISTER_TO_SLAVE_ADDRESS(Register);
|
||||
DeviceRegister = (UINT8)EXTERNAL_DEVICE_REGISTER_TO_REGISTER(Register);
|
||||
|
||||
//Prepare buffer for writing
|
||||
DeviceBuffer = (UINT8 *)AllocatePool(DeviceBufferLength);
|
||||
if (DeviceBuffer == NULL) {
|
||||
Status = EFI_OUT_OF_RESOURCES;
|
||||
goto exit;
|
||||
}
|
||||
|
||||
//Set Device register followed by data to write.
|
||||
DeviceBuffer[0] = DeviceRegister;
|
||||
CopyMem(&DeviceBuffer[1], Buffer, Length);
|
||||
|
||||
//Write Data
|
||||
Status = Smbus->Execute(Smbus, SlaveAddress, 0, EfiSmbusWriteBlock, FALSE, &DeviceBufferLength, DeviceBuffer);
|
||||
if (EFI_ERROR(Status)) {
|
||||
goto exit;
|
||||
}
|
||||
|
||||
exit:
|
||||
if (DeviceBuffer) {
|
||||
FreePool(DeviceBuffer);
|
||||
}
|
||||
|
||||
return Status;
|
||||
}
|
||||
|
||||
EMBEDDED_EXTERNAL_DEVICE ExternalDevice = {
|
||||
Read,
|
||||
Write
|
||||
};
|
||||
|
||||
EFI_STATUS
|
||||
TPS65950Initialize (
|
||||
IN EFI_HANDLE ImageHandle,
|
||||
IN EFI_SYSTEM_TABLE *SystemTable
|
||||
)
|
||||
{
|
||||
EFI_STATUS Status;
|
||||
|
||||
Status = gBS->LocateProtocol(&gEfiSmbusHcProtocolGuid, NULL, (VOID **)&Smbus);
|
||||
ASSERT_EFI_ERROR(Status);
|
||||
|
||||
Status = gBS->InstallMultipleProtocolInterfaces(&ImageHandle, &gEmbeddedExternalDeviceProtocolGuid, &ExternalDevice, NULL);
|
||||
return Status;
|
||||
}
|
||||
@ -1,48 +0,0 @@
|
||||
#/** @file
|
||||
#
|
||||
# Copyright (c) 2008 - 2010, Apple Inc. All rights reserved.
|
||||
# All rights reserved. This program and the accompanying materials
|
||||
# are licensed and made available under the terms and conditions of the BSD License
|
||||
# which accompanies this distribution. The full text of the license may be found at
|
||||
# http://opensource.org/licenses/bsd-license.php
|
||||
#
|
||||
# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
|
||||
# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
|
||||
#
|
||||
#**/
|
||||
|
||||
[Defines]
|
||||
INF_VERSION = 0x00010005
|
||||
BASE_NAME = TPS65950
|
||||
FILE_GUID = 71fe861a-5450-48b6-bfb0-b93522616f99
|
||||
MODULE_TYPE = DXE_DRIVER
|
||||
VERSION_STRING = 1.0
|
||||
|
||||
ENTRY_POINT = TPS65950Initialize
|
||||
|
||||
|
||||
[Sources.common]
|
||||
TPS65950.c
|
||||
|
||||
[Packages]
|
||||
MdePkg/MdePkg.dec
|
||||
EmbeddedPkg/EmbeddedPkg.dec
|
||||
BeagleBoardPkg/BeagleBoardPkg.dec
|
||||
|
||||
[LibraryClasses]
|
||||
BaseMemoryLib
|
||||
PcdLib
|
||||
UefiLib
|
||||
UefiDriverEntryPoint
|
||||
MemoryAllocationLib
|
||||
|
||||
[Guids]
|
||||
|
||||
[Protocols]
|
||||
gEfiSmbusHcProtocolGuid
|
||||
gEmbeddedExternalDeviceProtocolGuid
|
||||
|
||||
[Pcd]
|
||||
|
||||
[depex]
|
||||
gEfiSmbusHcProtocolGuid
|
||||
@ -1,396 +0,0 @@
|
||||
/** @file
|
||||
Template for Timer Architecture Protocol driver of the ARM flavor
|
||||
|
||||
Copyright (c) 2008-2009, Apple Inc. All rights reserved.
|
||||
|
||||
All rights reserved. This program and the accompanying materials
|
||||
are licensed and made available under the terms and conditions of the BSD License
|
||||
which accompanies this distribution. The full text of the license may be found at
|
||||
http://opensource.org/licenses/bsd-license.php
|
||||
|
||||
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
|
||||
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
|
||||
|
||||
**/
|
||||
|
||||
|
||||
#include <PiDxe.h>
|
||||
|
||||
#include <Library/BaseLib.h>
|
||||
#include <Library/DebugLib.h>
|
||||
#include <Library/BaseMemoryLib.h>
|
||||
#include <Library/UefiBootServicesTableLib.h>
|
||||
#include <Library/UefiLib.h>
|
||||
#include <Library/PcdLib.h>
|
||||
#include <Library/IoLib.h>
|
||||
#include <Library/OmapLib.h>
|
||||
|
||||
#include <Protocol/Timer.h>
|
||||
#include <Protocol/HardwareInterrupt.h>
|
||||
#include <Protocol/TimerDebugSupport.h>
|
||||
|
||||
#include <Omap3530/Omap3530.h>
|
||||
|
||||
|
||||
// The notification function to call on every timer interrupt.
|
||||
volatile EFI_TIMER_NOTIFY mTimerNotifyFunction = (EFI_TIMER_NOTIFY)NULL;
|
||||
volatile EFI_PERIODIC_CALLBACK mTimerPeriodicCallback = (EFI_PERIODIC_CALLBACK)NULL;
|
||||
|
||||
|
||||
// The current period of the timer interrupt
|
||||
volatile UINT64 mTimerPeriod = 0;
|
||||
|
||||
// Cached copy of the Hardware Interrupt protocol instance
|
||||
EFI_HARDWARE_INTERRUPT_PROTOCOL *gInterrupt = NULL;
|
||||
|
||||
// Cached registers
|
||||
volatile UINT32 TISR;
|
||||
volatile UINT32 TCLR;
|
||||
volatile UINT32 TLDR;
|
||||
volatile UINT32 TCRR;
|
||||
volatile UINT32 TIER;
|
||||
|
||||
// Cached interrupt vector
|
||||
volatile UINTN gVector;
|
||||
|
||||
|
||||
/**
|
||||
C Interrupt Handler calledin the interrupt context when Source interrupt is active.
|
||||
|
||||
@param Source Source of the interrupt. Hardware routing off a specific platform defines
|
||||
what source means.
|
||||
@param SystemContext Pointer to system register context. Mostly used by debuggers and will
|
||||
update the system context after the return from the interrupt if
|
||||
modified. Don't change these values unless you know what you are doing
|
||||
|
||||
**/
|
||||
VOID
|
||||
EFIAPI
|
||||
TimerInterruptHandler (
|
||||
IN HARDWARE_INTERRUPT_SOURCE Source,
|
||||
IN EFI_SYSTEM_CONTEXT SystemContext
|
||||
)
|
||||
{
|
||||
EFI_TPL OriginalTPL;
|
||||
|
||||
//
|
||||
// DXE core uses this callback for the EFI timer tick. The DXE core uses locks
|
||||
// that raise to TPL_HIGH and then restore back to current level. Thus we need
|
||||
// to make sure TPL level is set to TPL_HIGH while we are handling the timer tick.
|
||||
//
|
||||
OriginalTPL = gBS->RaiseTPL (TPL_HIGH_LEVEL);
|
||||
|
||||
if (mTimerPeriodicCallback) {
|
||||
mTimerPeriodicCallback(SystemContext);
|
||||
}
|
||||
|
||||
if (mTimerNotifyFunction) {
|
||||
mTimerNotifyFunction(mTimerPeriod);
|
||||
}
|
||||
|
||||
// Clear all timer interrupts
|
||||
MmioWrite32(TISR, TISR_CLEAR_ALL);
|
||||
|
||||
// Poll interrupt status bits to ensure clearing
|
||||
while ((MmioRead32(TISR) & TISR_ALL_INTERRUPT_MASK) != TISR_NO_INTERRUPTS_PENDING);
|
||||
|
||||
gBS->RestoreTPL (OriginalTPL);
|
||||
}
|
||||
|
||||
/**
|
||||
This function registers the handler NotifyFunction so it is called every time
|
||||
the timer interrupt fires. It also passes the amount of time since the last
|
||||
handler call to the NotifyFunction. If NotifyFunction is NULL, then the
|
||||
handler is unregistered. If the handler is registered, then EFI_SUCCESS is
|
||||
returned. If the CPU does not support registering a timer interrupt handler,
|
||||
then EFI_UNSUPPORTED is returned. If an attempt is made to register a handler
|
||||
when a handler is already registered, then EFI_ALREADY_STARTED is returned.
|
||||
If an attempt is made to unregister a handler when a handler is not registered,
|
||||
then EFI_INVALID_PARAMETER is returned. If an error occurs attempting to
|
||||
register the NotifyFunction with the timer interrupt, then EFI_DEVICE_ERROR
|
||||
is returned.
|
||||
|
||||
@param This The EFI_TIMER_ARCH_PROTOCOL instance.
|
||||
@param NotifyFunction The function to call when a timer interrupt fires. This
|
||||
function executes at TPL_HIGH_LEVEL. The DXE Core will
|
||||
register a handler for the timer interrupt, so it can know
|
||||
how much time has passed. This information is used to
|
||||
signal timer based events. NULL will unregister the handler.
|
||||
|
||||
@retval EFI_SUCCESS The timer handler was registered.
|
||||
@retval EFI_UNSUPPORTED The platform does not support timer interrupts.
|
||||
@retval EFI_ALREADY_STARTED NotifyFunction is not NULL, and a handler is already
|
||||
registered.
|
||||
@retval EFI_INVALID_PARAMETER NotifyFunction is NULL, and a handler was not
|
||||
previously registered.
|
||||
@retval EFI_DEVICE_ERROR The timer handler could not be registered.
|
||||
|
||||
**/
|
||||
EFI_STATUS
|
||||
EFIAPI
|
||||
TimerDriverRegisterHandler (
|
||||
IN EFI_TIMER_ARCH_PROTOCOL *This,
|
||||
IN EFI_TIMER_NOTIFY NotifyFunction
|
||||
)
|
||||
{
|
||||
if ((NotifyFunction == NULL) && (mTimerNotifyFunction == NULL)) {
|
||||
return EFI_INVALID_PARAMETER;
|
||||
}
|
||||
|
||||
if ((NotifyFunction != NULL) && (mTimerNotifyFunction != NULL)) {
|
||||
return EFI_ALREADY_STARTED;
|
||||
}
|
||||
|
||||
mTimerNotifyFunction = NotifyFunction;
|
||||
|
||||
return EFI_SUCCESS;
|
||||
}
|
||||
|
||||
/**
|
||||
This function adjusts the period of timer interrupts to the value specified
|
||||
by TimerPeriod. If the timer period is updated, then the selected timer
|
||||
period is stored in EFI_TIMER.TimerPeriod, and EFI_SUCCESS is returned. If
|
||||
the timer hardware is not programmable, then EFI_UNSUPPORTED is returned.
|
||||
If an error occurs while attempting to update the timer period, then the
|
||||
timer hardware will be put back in its state prior to this call, and
|
||||
EFI_DEVICE_ERROR is returned. If TimerPeriod is 0, then the timer interrupt
|
||||
is disabled. This is not the same as disabling the CPU's interrupts.
|
||||
Instead, it must either turn off the timer hardware, or it must adjust the
|
||||
interrupt controller so that a CPU interrupt is not generated when the timer
|
||||
interrupt fires.
|
||||
|
||||
@param This The EFI_TIMER_ARCH_PROTOCOL instance.
|
||||
@param TimerPeriod The rate to program the timer interrupt in 100 nS units. If
|
||||
the timer hardware is not programmable, then EFI_UNSUPPORTED is
|
||||
returned. If the timer is programmable, then the timer period
|
||||
will be rounded up to the nearest timer period that is supported
|
||||
by the timer hardware. If TimerPeriod is set to 0, then the
|
||||
timer interrupts will be disabled.
|
||||
|
||||
@retval EFI_SUCCESS The timer period was changed.
|
||||
@retval EFI_UNSUPPORTED The platform cannot change the period of the timer interrupt.
|
||||
@retval EFI_DEVICE_ERROR The timer period could not be changed due to a device error.
|
||||
|
||||
**/
|
||||
EFI_STATUS
|
||||
EFIAPI
|
||||
TimerDriverSetTimerPeriod (
|
||||
IN EFI_TIMER_ARCH_PROTOCOL *This,
|
||||
IN UINT64 TimerPeriod
|
||||
)
|
||||
{
|
||||
EFI_STATUS Status;
|
||||
UINT64 TimerCount;
|
||||
INT32 LoadValue;
|
||||
|
||||
if (TimerPeriod == 0) {
|
||||
// Turn off GPTIMER3
|
||||
MmioWrite32(TCLR, TCLR_ST_OFF);
|
||||
|
||||
Status = gInterrupt->DisableInterruptSource(gInterrupt, gVector);
|
||||
} else {
|
||||
// Calculate required timer count
|
||||
TimerCount = DivU64x32(TimerPeriod * 100, PcdGet32(PcdEmbeddedFdPerformanceCounterPeriodInNanoseconds));
|
||||
|
||||
// Set GPTIMER3 Load register
|
||||
LoadValue = (INT32) -TimerCount;
|
||||
MmioWrite32(TLDR, LoadValue);
|
||||
MmioWrite32(TCRR, LoadValue);
|
||||
|
||||
// Enable Overflow interrupt
|
||||
MmioWrite32(TIER, TIER_TCAR_IT_DISABLE | TIER_OVF_IT_ENABLE | TIER_MAT_IT_DISABLE);
|
||||
|
||||
// Turn on GPTIMER3, it will reload at overflow
|
||||
MmioWrite32(TCLR, TCLR_AR_AUTORELOAD | TCLR_ST_ON);
|
||||
|
||||
Status = gInterrupt->EnableInterruptSource(gInterrupt, gVector);
|
||||
}
|
||||
|
||||
//
|
||||
// Save the new timer period
|
||||
//
|
||||
mTimerPeriod = TimerPeriod;
|
||||
return Status;
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
This function retrieves the period of timer interrupts in 100 ns units,
|
||||
returns that value in TimerPeriod, and returns EFI_SUCCESS. If TimerPeriod
|
||||
is NULL, then EFI_INVALID_PARAMETER is returned. If a TimerPeriod of 0 is
|
||||
returned, then the timer is currently disabled.
|
||||
|
||||
@param This The EFI_TIMER_ARCH_PROTOCOL instance.
|
||||
@param TimerPeriod A pointer to the timer period to retrieve in 100 ns units. If
|
||||
0 is returned, then the timer is currently disabled.
|
||||
|
||||
@retval EFI_SUCCESS The timer period was returned in TimerPeriod.
|
||||
@retval EFI_INVALID_PARAMETER TimerPeriod is NULL.
|
||||
|
||||
**/
|
||||
EFI_STATUS
|
||||
EFIAPI
|
||||
TimerDriverGetTimerPeriod (
|
||||
IN EFI_TIMER_ARCH_PROTOCOL *This,
|
||||
OUT UINT64 *TimerPeriod
|
||||
)
|
||||
{
|
||||
if (TimerPeriod == NULL) {
|
||||
return EFI_INVALID_PARAMETER;
|
||||
}
|
||||
|
||||
*TimerPeriod = mTimerPeriod;
|
||||
return EFI_SUCCESS;
|
||||
}
|
||||
|
||||
/**
|
||||
This function generates a soft timer interrupt. If the platform does not support soft
|
||||
timer interrupts, then EFI_UNSUPPORTED is returned. Otherwise, EFI_SUCCESS is returned.
|
||||
If a handler has been registered through the EFI_TIMER_ARCH_PROTOCOL.RegisterHandler()
|
||||
service, then a soft timer interrupt will be generated. If the timer interrupt is
|
||||
enabled when this service is called, then the registered handler will be invoked. The
|
||||
registered handler should not be able to distinguish a hardware-generated timer
|
||||
interrupt from a software-generated timer interrupt.
|
||||
|
||||
@param This The EFI_TIMER_ARCH_PROTOCOL instance.
|
||||
|
||||
@retval EFI_SUCCESS The soft timer interrupt was generated.
|
||||
@retval EFI_UNSUPPORTED The platform does not support the generation of soft timer interrupts.
|
||||
|
||||
**/
|
||||
EFI_STATUS
|
||||
EFIAPI
|
||||
TimerDriverGenerateSoftInterrupt (
|
||||
IN EFI_TIMER_ARCH_PROTOCOL *This
|
||||
)
|
||||
{
|
||||
return EFI_UNSUPPORTED;
|
||||
}
|
||||
|
||||
|
||||
EFI_STATUS
|
||||
EFIAPI
|
||||
TimerDriverRegisterPeriodicCallback (
|
||||
IN TIMER_DEBUG_SUPPORT_PROTOCOL *This,
|
||||
IN EFI_PERIODIC_CALLBACK PeriodicCallback
|
||||
)
|
||||
{
|
||||
if ((PeriodicCallback == NULL) && (mTimerPeriodicCallback == NULL)) {
|
||||
return EFI_INVALID_PARAMETER;
|
||||
}
|
||||
|
||||
if ((PeriodicCallback != NULL) && (mTimerPeriodicCallback != NULL)) {
|
||||
return EFI_ALREADY_STARTED;
|
||||
}
|
||||
|
||||
mTimerPeriodicCallback = PeriodicCallback;
|
||||
|
||||
return EFI_SUCCESS;
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
Interface stucture for the Timer Architectural Protocol.
|
||||
|
||||
@par Protocol Description:
|
||||
This protocol provides the services to initialize a periodic timer
|
||||
interrupt, and to register a handler that is called each time the timer
|
||||
interrupt fires. It may also provide a service to adjust the rate of the
|
||||
periodic timer interrupt. When a timer interrupt occurs, the handler is
|
||||
passed the amount of time that has passed since the previous timer
|
||||
interrupt.
|
||||
|
||||
@param RegisterHandler
|
||||
Registers a handler that will be called each time the
|
||||
timer interrupt fires. TimerPeriod defines the minimum
|
||||
time between timer interrupts, so TimerPeriod will also
|
||||
be the minimum time between calls to the registered
|
||||
handler.
|
||||
|
||||
@param SetTimerPeriod
|
||||
Sets the period of the timer interrupt in 100 nS units.
|
||||
This function is optional, and may return EFI_UNSUPPORTED.
|
||||
If this function is supported, then the timer period will
|
||||
be rounded up to the nearest supported timer period.
|
||||
|
||||
@param GetTimerPeriod
|
||||
Retrieves the period of the timer interrupt in 100 nS units.
|
||||
|
||||
@param GenerateSoftInterrupt
|
||||
Generates a soft timer interrupt that simulates the firing of
|
||||
the timer interrupt. This service can be used to invoke the
|
||||
registered handler if the timer interrupt has been masked for
|
||||
a period of time.
|
||||
|
||||
**/
|
||||
EFI_TIMER_ARCH_PROTOCOL gTimer = {
|
||||
TimerDriverRegisterHandler,
|
||||
TimerDriverSetTimerPeriod,
|
||||
TimerDriverGetTimerPeriod,
|
||||
TimerDriverGenerateSoftInterrupt
|
||||
};
|
||||
|
||||
TIMER_DEBUG_SUPPORT_PROTOCOL gTimerDebugSupport = {
|
||||
TimerDriverRegisterPeriodicCallback
|
||||
};
|
||||
|
||||
|
||||
/**
|
||||
Initialize the state information for the Timer Architectural Protocol and
|
||||
the Timer Debug support protocol that allows the debugger to break into a
|
||||
running program.
|
||||
|
||||
@param ImageHandle of the loaded driver
|
||||
@param SystemTable Pointer to the System Table
|
||||
|
||||
@retval EFI_SUCCESS Protocol registered
|
||||
@retval EFI_OUT_OF_RESOURCES Cannot allocate protocol data structure
|
||||
@retval EFI_DEVICE_ERROR Hardware problems
|
||||
|
||||
**/
|
||||
EFI_STATUS
|
||||
EFIAPI
|
||||
TimerInitialize (
|
||||
IN EFI_HANDLE ImageHandle,
|
||||
IN EFI_SYSTEM_TABLE *SystemTable
|
||||
)
|
||||
{
|
||||
EFI_HANDLE Handle = NULL;
|
||||
EFI_STATUS Status;
|
||||
UINT32 TimerBaseAddress;
|
||||
|
||||
// Find the interrupt controller protocol. ASSERT if not found.
|
||||
Status = gBS->LocateProtocol(&gHardwareInterruptProtocolGuid, NULL, (VOID **)&gInterrupt);
|
||||
ASSERT_EFI_ERROR (Status);
|
||||
|
||||
// Set up the timer registers
|
||||
TimerBaseAddress = TimerBase(FixedPcdGet32(PcdBeagleArchTimer));
|
||||
TISR = TimerBaseAddress + GPTIMER_TISR;
|
||||
TCLR = TimerBaseAddress + GPTIMER_TCLR;
|
||||
TLDR = TimerBaseAddress + GPTIMER_TLDR;
|
||||
TCRR = TimerBaseAddress + GPTIMER_TCRR;
|
||||
TIER = TimerBaseAddress + GPTIMER_TIER;
|
||||
|
||||
// Disable the timer
|
||||
Status = TimerDriverSetTimerPeriod(&gTimer, 0);
|
||||
ASSERT_EFI_ERROR (Status);
|
||||
|
||||
// Install interrupt handler
|
||||
gVector = InterruptVectorForTimer(FixedPcdGet32(PcdBeagleArchTimer));
|
||||
Status = gInterrupt->RegisterInterruptSource(gInterrupt, gVector, TimerInterruptHandler);
|
||||
ASSERT_EFI_ERROR (Status);
|
||||
|
||||
// Set up default timer
|
||||
Status = TimerDriverSetTimerPeriod(&gTimer, FixedPcdGet32(PcdTimerPeriod));
|
||||
ASSERT_EFI_ERROR (Status);
|
||||
|
||||
// Install the Timer Architectural Protocol onto a new handle
|
||||
Status = gBS->InstallMultipleProtocolInterfaces(&Handle,
|
||||
&gEfiTimerArchProtocolGuid, &gTimer,
|
||||
&gTimerDebugSupportProtocolGuid, &gTimerDebugSupport,
|
||||
NULL);
|
||||
ASSERT_EFI_ERROR(Status);
|
||||
|
||||
return Status;
|
||||
}
|
||||
|
||||
@ -1,59 +0,0 @@
|
||||
#/** @file
|
||||
#
|
||||
# Component discription file for Timer module
|
||||
#
|
||||
# Copyright (c) 2009, Apple Inc. <BR>
|
||||
# All rights reserved. This program and the accompanying materials
|
||||
# are licensed and made available under the terms and conditions of the BSD License
|
||||
# which accompanies this distribution. The full text of the license may be found at
|
||||
# http://opensource.org/licenses/bsd-license.php
|
||||
#
|
||||
# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
|
||||
# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
|
||||
#
|
||||
#**/
|
||||
|
||||
[Defines]
|
||||
INF_VERSION = 0x00010005
|
||||
BASE_NAME = BeagleBoardTimerDxe
|
||||
FILE_GUID = 6ddbf08b-cfc9-43cc-9e81-0784ba312ca0
|
||||
MODULE_TYPE = DXE_DRIVER
|
||||
VERSION_STRING = 1.0
|
||||
|
||||
ENTRY_POINT = TimerInitialize
|
||||
|
||||
[Sources.common]
|
||||
Timer.c
|
||||
|
||||
[Packages]
|
||||
BeagleBoardPkg/BeagleBoardPkg.dec
|
||||
MdePkg/MdePkg.dec
|
||||
EmbeddedPkg/EmbeddedPkg.dec
|
||||
ArmPkg/ArmPkg.dec
|
||||
|
||||
[LibraryClasses]
|
||||
BaseLib
|
||||
UefiRuntimeServicesTableLib
|
||||
PerformanceLib
|
||||
UefiLib
|
||||
UefiBootServicesTableLib
|
||||
BaseMemoryLib
|
||||
DebugLib
|
||||
UefiDriverEntryPoint
|
||||
IoLib
|
||||
OmapLib
|
||||
|
||||
[Guids]
|
||||
|
||||
[Protocols]
|
||||
gEfiTimerArchProtocolGuid
|
||||
gHardwareInterruptProtocolGuid
|
||||
gTimerDebugSupportProtocolGuid
|
||||
|
||||
[Pcd.common]
|
||||
gEmbeddedTokenSpaceGuid.PcdTimerPeriod
|
||||
gEmbeddedTokenSpaceGuid.PcdEmbeddedFdPerformanceCounterPeriodInNanoseconds
|
||||
gBeagleBoardTokenSpaceGuid.PcdBeagleArchTimer
|
||||
|
||||
[Depex]
|
||||
gHardwareInterruptProtocolGuid
|
||||
Loading…
x
Reference in New Issue
Block a user