mirror of https://github.com/acidanthera/audk.git
SecurityPkg: OpalPasswordSmm: Add Opal password Smm driver.
This driver used to unlock device in S3 resume phase. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Eric Dong <eric.dong@intel.com> Reviewed-by: Feng Tian <feng.tian@intel.com>
This commit is contained in:
Eric Dong
Feng Tian
parent
a06875e1f0
commit
cb274a2703
File diff suppressed because it is too large
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/** @file
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Header file for AHCI mode of ATA host controller.
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Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>
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This program and the accompanying materials
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are licensed and made available under the terms and conditions of the BSD License
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which accompanies this distribution. The full text of the license may be found at
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http://opensource.org/licenses/bsd-license.php
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THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
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WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
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**/
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#ifndef __OPAL_PASSWORD_AHCI_MODE_H__
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#define __OPAL_PASSWORD_AHCI_MODE_H__
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//
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// OPAL LIBRARY CALLBACKS
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//
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#define ATA_COMMAND_TRUSTED_RECEIVE 0x5C
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#define ATA_COMMAND_TRUSTED_SEND 0x5E
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//
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// ATA TRUSTED commands express transfer Length in 512 byte multiple
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//
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#define ATA_TRUSTED_TRANSFER_LENGTH_MULTIPLE 512
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#define ATA_DEVICE_LBA 0x40 ///< Set for commands with LBA (rather than CHS) addresses
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#define EFI_AHCI_BAR_INDEX 0x05
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#define EFI_AHCI_CAPABILITY_OFFSET 0x0000
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#define EFI_AHCI_CAP_SAM BIT18
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#define EFI_AHCI_GHC_OFFSET 0x0004
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#define EFI_AHCI_GHC_RESET BIT0
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#define EFI_AHCI_GHC_IE BIT1
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#define EFI_AHCI_GHC_ENABLE BIT31
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#define EFI_AHCI_IS_OFFSET 0x0008
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#define EFI_AHCI_PI_OFFSET 0x000C
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typedef struct {
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UINT32 Lower32;
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UINT32 Upper32;
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} DATA_32;
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typedef union {
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DATA_32 Uint32;
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UINT64 Uint64;
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} DATA_64;
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//
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// Each PRDT entry can point to a memory block up to 4M byte
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//
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#define EFI_AHCI_MAX_DATA_PER_PRDT 0x400000
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#define EFI_AHCI_FIS_REGISTER_H2D 0x27 //Register FIS - Host to Device
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#define EFI_AHCI_FIS_REGISTER_H2D_LENGTH 20
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#define EFI_AHCI_FIS_REGISTER_D2H 0x34 //Register FIS - Device to Host
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#define EFI_AHCI_FIS_REGISTER_D2H_LENGTH 20
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#define EFI_AHCI_FIS_DMA_ACTIVATE 0x39 //DMA Activate FIS - Device to Host
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#define EFI_AHCI_FIS_DMA_ACTIVATE_LENGTH 4
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#define EFI_AHCI_FIS_DMA_SETUP 0x41 //DMA Setup FIS - Bi-directional
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#define EFI_AHCI_FIS_DMA_SETUP_LENGTH 28
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#define EFI_AHCI_FIS_DATA 0x46 //Data FIS - Bi-directional
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#define EFI_AHCI_FIS_BIST 0x58 //BIST Activate FIS - Bi-directional
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#define EFI_AHCI_FIS_BIST_LENGTH 12
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#define EFI_AHCI_FIS_PIO_SETUP 0x5F //PIO Setup FIS - Device to Host
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#define EFI_AHCI_FIS_PIO_SETUP_LENGTH 20
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#define EFI_AHCI_FIS_SET_DEVICE 0xA1 //Set Device Bits FIS - Device to Host
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#define EFI_AHCI_FIS_SET_DEVICE_LENGTH 8
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#define EFI_AHCI_D2H_FIS_OFFSET 0x40
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#define EFI_AHCI_DMA_FIS_OFFSET 0x00
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#define EFI_AHCI_PIO_FIS_OFFSET 0x20
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#define EFI_AHCI_SDB_FIS_OFFSET 0x58
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#define EFI_AHCI_FIS_TYPE_MASK 0xFF
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#define EFI_AHCI_U_FIS_OFFSET 0x60
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//
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// Port register
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//
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#define EFI_AHCI_PORT_START 0x0100
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#define EFI_AHCI_PORT_REG_WIDTH 0x0080
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#define EFI_AHCI_PORT_CLB 0x0000
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#define EFI_AHCI_PORT_CLBU 0x0004
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#define EFI_AHCI_PORT_FB 0x0008
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#define EFI_AHCI_PORT_FBU 0x000C
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#define EFI_AHCI_PORT_IS 0x0010
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#define EFI_AHCI_PORT_IS_DHRS BIT0
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#define EFI_AHCI_PORT_IS_PSS BIT1
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#define EFI_AHCI_PORT_IS_SSS BIT2
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#define EFI_AHCI_PORT_IS_SDBS BIT3
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#define EFI_AHCI_PORT_IS_UFS BIT4
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#define EFI_AHCI_PORT_IS_DPS BIT5
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#define EFI_AHCI_PORT_IS_PCS BIT6
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#define EFI_AHCI_PORT_IS_DIS BIT7
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#define EFI_AHCI_PORT_IS_PRCS BIT22
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#define EFI_AHCI_PORT_IS_IPMS BIT23
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#define EFI_AHCI_PORT_IS_OFS BIT24
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#define EFI_AHCI_PORT_IS_INFS BIT26
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#define EFI_AHCI_PORT_IS_IFS BIT27
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#define EFI_AHCI_PORT_IS_HBDS BIT28
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#define EFI_AHCI_PORT_IS_HBFS BIT29
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#define EFI_AHCI_PORT_IS_TFES BIT30
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#define EFI_AHCI_PORT_IS_CPDS BIT31
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#define EFI_AHCI_PORT_IS_CLEAR 0xFFFFFFFF
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#define EFI_AHCI_PORT_IS_FIS_CLEAR 0x0000000F
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#define EFI_AHCI_PORT_IE 0x0014
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#define EFI_AHCI_PORT_CMD 0x0018
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#define EFI_AHCI_PORT_CMD_ST_MASK 0xFFFFFFFE
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#define EFI_AHCI_PORT_CMD_ST BIT0
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#define EFI_AHCI_PORT_CMD_SUD BIT1
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#define EFI_AHCI_PORT_CMD_POD BIT2
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#define EFI_AHCI_PORT_CMD_COL BIT3
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#define EFI_AHCI_PORT_CMD_CR BIT15
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#define EFI_AHCI_PORT_CMD_FRE BIT4
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#define EFI_AHCI_PORT_CMD_FR BIT14
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#define EFI_AHCI_PORT_CMD_MASK ~(EFI_AHCI_PORT_CMD_ST | EFI_AHCI_PORT_CMD_FRE | EFI_AHCI_PORT_CMD_COL)
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#define EFI_AHCI_PORT_CMD_PMA BIT17
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#define EFI_AHCI_PORT_CMD_HPCP BIT18
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#define EFI_AHCI_PORT_CMD_MPSP BIT19
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#define EFI_AHCI_PORT_CMD_CPD BIT20
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#define EFI_AHCI_PORT_CMD_ESP BIT21
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#define EFI_AHCI_PORT_CMD_ATAPI BIT24
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#define EFI_AHCI_PORT_CMD_DLAE BIT25
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#define EFI_AHCI_PORT_CMD_ALPE BIT26
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#define EFI_AHCI_PORT_CMD_ASP BIT27
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#define EFI_AHCI_PORT_CMD_ICC_MASK (BIT28 | BIT29 | BIT30 | BIT31)
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#define EFI_AHCI_PORT_CMD_ACTIVE (1 << 28 )
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#define EFI_AHCI_PORT_TFD 0x0020
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#define EFI_AHCI_PORT_TFD_MASK (BIT7 | BIT3 | BIT0)
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#define EFI_AHCI_PORT_TFD_BSY BIT7
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#define EFI_AHCI_PORT_TFD_DRQ BIT3
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#define EFI_AHCI_PORT_TFD_ERR BIT0
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#define EFI_AHCI_PORT_TFD_ERR_MASK 0x00FF00
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#define EFI_AHCI_PORT_SIG 0x0024
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#define EFI_AHCI_PORT_SSTS 0x0028
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#define EFI_AHCI_PORT_SSTS_DET_MASK 0x000F
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#define EFI_AHCI_PORT_SSTS_DET 0x0001
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#define EFI_AHCI_PORT_SSTS_DET_PCE 0x0003
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#define EFI_AHCI_PORT_SSTS_SPD_MASK 0x00F0
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#define EFI_AHCI_PORT_SCTL 0x002C
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#define EFI_AHCI_PORT_SCTL_DET_MASK 0x000F
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#define EFI_AHCI_PORT_SCTL_MASK (~EFI_AHCI_PORT_SCTL_DET_MASK)
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#define EFI_AHCI_PORT_SCTL_DET_INIT 0x0001
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#define EFI_AHCI_PORT_SCTL_DET_PHYCOMM 0x0003
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#define EFI_AHCI_PORT_SCTL_SPD_MASK 0x00F0
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#define EFI_AHCI_PORT_SCTL_IPM_MASK 0x0F00
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#define EFI_AHCI_PORT_SCTL_IPM_INIT 0x0300
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#define EFI_AHCI_PORT_SCTL_IPM_PSD 0x0100
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#define EFI_AHCI_PORT_SCTL_IPM_SSD 0x0200
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#define EFI_AHCI_PORT_SERR 0x0030
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#define EFI_AHCI_PORT_SERR_RDIE BIT0
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#define EFI_AHCI_PORT_SERR_RCE BIT1
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#define EFI_AHCI_PORT_SERR_TDIE BIT8
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#define EFI_AHCI_PORT_SERR_PCDIE BIT9
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#define EFI_AHCI_PORT_SERR_PE BIT10
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#define EFI_AHCI_PORT_SERR_IE BIT11
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#define EFI_AHCI_PORT_SERR_PRC BIT16
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#define EFI_AHCI_PORT_SERR_PIE BIT17
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#define EFI_AHCI_PORT_SERR_CW BIT18
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#define EFI_AHCI_PORT_SERR_BDE BIT19
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#define EFI_AHCI_PORT_SERR_DE BIT20
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#define EFI_AHCI_PORT_SERR_CRCE BIT21
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#define EFI_AHCI_PORT_SERR_HE BIT22
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#define EFI_AHCI_PORT_SERR_LSE BIT23
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#define EFI_AHCI_PORT_SERR_TSTE BIT24
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#define EFI_AHCI_PORT_SERR_UFT BIT25
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#define EFI_AHCI_PORT_SERR_EX BIT26
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#define EFI_AHCI_PORT_ERR_CLEAR 0xFFFFFFFF
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#define EFI_AHCI_PORT_SACT 0x0034
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#define EFI_AHCI_PORT_CI 0x0038
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#define EFI_AHCI_PORT_SNTF 0x003C
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#pragma pack(1)
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//
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// Command List structure includes total 32 entries.
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// The entry Data structure is listed at the following.
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//
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typedef struct {
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UINT32 AhciCmdCfl:5; //Command FIS Length
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UINT32 AhciCmdA:1; //ATAPI
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UINT32 AhciCmdW:1; //Write
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UINT32 AhciCmdP:1; //Prefetchable
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UINT32 AhciCmdR:1; //Reset
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UINT32 AhciCmdB:1; //BIST
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UINT32 AhciCmdC:1; //Clear Busy upon R_OK
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UINT32 AhciCmdRsvd:1;
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UINT32 AhciCmdPmp:4; //Port Multiplier Port
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UINT32 AhciCmdPrdtl:16; //Physical Region Descriptor Table Length
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UINT32 AhciCmdPrdbc; //Physical Region Descriptor Byte Count
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UINT32 AhciCmdCtba; //Command Table Descriptor Base Address
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UINT32 AhciCmdCtbau; //Command Table Descriptor Base Address Upper 32-BITs
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UINT32 AhciCmdRsvd1[4];
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} EFI_AHCI_COMMAND_LIST;
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//
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// This is a software constructed FIS.
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// For Data transfer operations, this is the H2D Register FIS format as
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// specified in the Serial ATA Revision 2.6 specification.
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//
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typedef struct {
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UINT8 AhciCFisType;
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UINT8 AhciCFisPmNum:4;
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UINT8 AhciCFisRsvd:1;
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UINT8 AhciCFisRsvd1:1;
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UINT8 AhciCFisRsvd2:1;
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UINT8 AhciCFisCmdInd:1;
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UINT8 AhciCFisCmd;
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UINT8 AhciCFisFeature;
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UINT8 AhciCFisSecNum;
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UINT8 AhciCFisClyLow;
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UINT8 AhciCFisClyHigh;
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UINT8 AhciCFisDevHead;
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UINT8 AhciCFisSecNumExp;
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UINT8 AhciCFisClyLowExp;
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UINT8 AhciCFisClyHighExp;
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UINT8 AhciCFisFeatureExp;
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UINT8 AhciCFisSecCount;
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UINT8 AhciCFisSecCountExp;
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UINT8 AhciCFisRsvd3;
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UINT8 AhciCFisControl;
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UINT8 AhciCFisRsvd4[4];
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UINT8 AhciCFisRsvd5[44];
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} EFI_AHCI_COMMAND_FIS;
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//
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// ACMD: ATAPI command (12 or 16 bytes)
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//
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typedef struct {
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UINT8 AtapiCmd[0x10];
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} EFI_AHCI_ATAPI_COMMAND;
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//
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// Physical Region Descriptor Table includes up to 65535 entries
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// The entry Data structure is listed at the following.
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// the actual entry number comes from the PRDTL field in the command
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// list entry for this command slot.
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//
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typedef struct {
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UINT32 AhciPrdtDba; //Data Base Address
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UINT32 AhciPrdtDbau; //Data Base Address Upper 32-BITs
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UINT32 AhciPrdtRsvd;
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UINT32 AhciPrdtDbc:22; //Data Byte Count
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UINT32 AhciPrdtRsvd1:9;
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UINT32 AhciPrdtIoc:1; //Interrupt on Completion
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} EFI_AHCI_COMMAND_PRDT;
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//
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// Command table Data strucute which is pointed to by the entry in the command list
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//
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typedef struct {
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EFI_AHCI_COMMAND_FIS CommandFis; // A software constructed FIS.
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EFI_AHCI_ATAPI_COMMAND AtapiCmd; // 12 or 16 bytes ATAPI cmd.
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UINT8 Reserved[0x30];
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EFI_AHCI_COMMAND_PRDT PrdtTable; // The scatter/gather list for Data transfer
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} EFI_AHCI_COMMAND_TABLE;
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//
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// Received FIS structure
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//
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typedef struct {
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UINT8 AhciDmaSetupFis[0x1C]; // Dma Setup Fis: offset 0x00
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UINT8 AhciDmaSetupFisRsvd[0x04];
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UINT8 AhciPioSetupFis[0x14]; // Pio Setup Fis: offset 0x20
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UINT8 AhciPioSetupFisRsvd[0x0C];
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UINT8 AhciD2HRegisterFis[0x14]; // D2H Register Fis: offset 0x40
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UINT8 AhciD2HRegisterFisRsvd[0x04];
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UINT64 AhciSetDeviceBitsFis; // Set Device Bits Fix: offset 0x58
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UINT8 AhciUnknownFis[0x40]; // Unkonwn Fis: offset 0x60
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UINT8 AhciUnknownFisRsvd[0x60];
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} EFI_AHCI_RECEIVED_FIS;
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#pragma pack()
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typedef struct {
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EFI_AHCI_RECEIVED_FIS *AhciRFis;
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EFI_AHCI_COMMAND_LIST *AhciCmdList;
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EFI_AHCI_COMMAND_TABLE *AhciCommandTable;
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} EFI_AHCI_REGISTERS;
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extern EFI_AHCI_REGISTERS mAhciRegisters;
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extern UINT32 mAhciBar;
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/**
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Send Buffer cmd to specific device.
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@param AhciRegisters The pointer to the EFI_AHCI_REGISTERS.
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@param Port The number of port.
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@param PortMultiplier The timeout Value of stop.
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@param Buffer The Data Buffer to store IDENTIFY PACKET Data.
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@retval EFI_DEVICE_ERROR The cmd abort with error occurs.
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@retval EFI_TIMEOUT The operation is time out.
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@retval EFI_UNSUPPORTED The device is not ready for executing.
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@retval EFI_SUCCESS The cmd executes successfully.
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**/
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EFI_STATUS
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EFIAPI
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AhciIdentify (
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IN EFI_AHCI_REGISTERS *AhciRegisters,
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IN UINT8 Port,
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IN UINT8 PortMultiplier,
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IN OUT ATA_IDENTIFY_DATA *Buffer
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);
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/**
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Get AHCI mode base address registers' Value.
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@param[in] Bus The bus number of ata host controller.
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@param[in] Device The device number of ata host controller.
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@param[in] Function The function number of ata host controller.
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@retval EFI_UNSUPPORTED Return this Value when the BARs is not IO type
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@retval EFI_SUCCESS Get the Base address successfully
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@retval Other Read the pci configureation Data error
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**/
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EFI_STATUS
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EFIAPI
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GetAhciBaseAddress (
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IN UINTN Bus,
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IN UINTN Device,
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IN UINTN Function
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);
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/**
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Allocate transfer-related Data struct which is used at AHCI mode.
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@retval EFI_OUT_OF_RESOURCE The allocation is failure.
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@retval EFI_SUCCESS Successful to allocate memory.
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**/
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EFI_STATUS
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EFIAPI
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AhciAllocateResource (
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VOID
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);
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/**
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Free allocated transfer-related Data struct which is used at AHCI mode.
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**/
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VOID
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EFIAPI
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AhciFreeResource (
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VOID
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);
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/**
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Initialize ATA host controller at AHCI mode.
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The function is designed to initialize ATA host controller.
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@param[in] Port The port number to do initialization.
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**/
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EFI_STATUS
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EFIAPI
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AhciModeInitialize (
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UINT8 Port
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);
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/**
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Start a PIO Data transfer on specific port.
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@param AhciRegisters The pointer to the EFI_AHCI_REGISTERS.
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@param Port The number of port.
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@param PortMultiplier The timeout Value of stop.
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@param AtapiCommand The atapi command will be used for the transfer.
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@param AtapiCommandLength The Length of the atapi command.
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@param Read The transfer direction.
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@param AtaCommandBlock The EFI_ATA_COMMAND_BLOCK Data.
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@param AtaStatusBlock The EFI_ATA_STATUS_BLOCK Data.
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@param MemoryAddr The pointer to the Data Buffer.
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@param DataCount The Data count to be transferred.
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@param Timeout The timeout Value of non Data transfer.
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@retval EFI_DEVICE_ERROR The PIO Data transfer abort with error occurs.
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@retval EFI_TIMEOUT The operation is time out.
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@retval EFI_UNSUPPORTED The device is not ready for transfer.
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@retval EFI_SUCCESS The PIO Data transfer executes successfully.
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**/
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EFI_STATUS
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EFIAPI
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AhciPioTransfer (
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IN EFI_AHCI_REGISTERS *AhciRegisters,
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IN UINT8 Port,
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IN UINT8 PortMultiplier,
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IN EFI_AHCI_ATAPI_COMMAND *AtapiCommand OPTIONAL,
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IN UINT8 AtapiCommandLength,
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IN BOOLEAN Read,
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IN EFI_ATA_COMMAND_BLOCK *AtaCommandBlock,
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IN OUT EFI_ATA_STATUS_BLOCK *AtaStatusBlock,
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IN OUT VOID *MemoryAddr,
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IN UINT32 DataCount,
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IN UINT64 Timeout
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||||
);
|
||||
|
||||
|
||||
#endif
|
||||
|
||||
|
|
@ -0,0 +1,767 @@
|
|||
/** @file
|
||||
This driver is used for Opal Password Feature support at IDE mode.
|
||||
|
||||
Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>
|
||||
This program and the accompanying materials
|
||||
are licensed and made available under the terms and conditions of the BSD License
|
||||
which accompanies this distribution. The full text of the license may be found at
|
||||
http://opensource.org/licenses/bsd-license.php
|
||||
|
||||
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
|
||||
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
|
||||
|
||||
**/
|
||||
|
||||
#include "OpalPasswordSmm.h"
|
||||
|
||||
/**
|
||||
Write multiple words of Data to the IDE Data port.
|
||||
Call the IO abstraction once to do the complete read,
|
||||
not one word at a time
|
||||
|
||||
@param Port IO port to read
|
||||
@param Count No. of UINT16's to read
|
||||
@param Buffer Pointer to the Data Buffer for read
|
||||
|
||||
**/
|
||||
VOID
|
||||
EFIAPI
|
||||
IdeWritePortWMultiple (
|
||||
IN UINT16 Port,
|
||||
IN UINTN Count,
|
||||
IN UINT16 *Buffer
|
||||
)
|
||||
{
|
||||
UINTN Index;
|
||||
|
||||
for (Index = 0; Index < Count; Index++) {
|
||||
IoWrite16 (Port, Buffer[Index]);
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
Reads multiple words of Data from the IDE Data port.
|
||||
Call the IO abstraction once to do the complete read,
|
||||
not one word at a time
|
||||
|
||||
@param Port IO port to read
|
||||
@param Count Number of UINT16's to read
|
||||
@param Buffer Pointer to the Data Buffer for read
|
||||
|
||||
**/
|
||||
VOID
|
||||
EFIAPI
|
||||
IdeReadPortWMultiple (
|
||||
IN UINT16 Port,
|
||||
IN UINTN Count,
|
||||
IN UINT16 *Buffer
|
||||
)
|
||||
{
|
||||
UINTN Index;
|
||||
|
||||
for (Index = 0; Index < Count; Index++) {
|
||||
Buffer[Count] = IoRead16 (Port);
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
This function is used to analyze the Status Register and print out
|
||||
some debug information and if there is ERR bit set in the Status
|
||||
Register, the Error Register's Value is also be parsed and print out.
|
||||
|
||||
@param IdeRegisters A pointer to EFI_IDE_REGISTERS Data structure.
|
||||
|
||||
**/
|
||||
VOID
|
||||
EFIAPI
|
||||
DumpAllIdeRegisters (
|
||||
IN EFI_IDE_REGISTERS *IdeRegisters
|
||||
)
|
||||
{
|
||||
ASSERT (IdeRegisters != NULL);
|
||||
|
||||
DEBUG_CODE_BEGIN ();
|
||||
if ((IoRead8 (IdeRegisters->CmdOrStatus) & ATA_STSREG_DWF) != 0) {
|
||||
DEBUG ((EFI_D_ERROR, "CheckRegisterStatus()-- %02x : Error : Write Fault\n", IoRead8 (IdeRegisters->CmdOrStatus)));
|
||||
}
|
||||
|
||||
if ((IoRead8 (IdeRegisters->CmdOrStatus) & ATA_STSREG_CORR) != 0) {
|
||||
DEBUG ((EFI_D_ERROR, "CheckRegisterStatus()-- %02x : Error : Corrected Data\n", IoRead8 (IdeRegisters->CmdOrStatus)));
|
||||
}
|
||||
|
||||
if ((IoRead8 (IdeRegisters->CmdOrStatus) & ATA_STSREG_ERR) != 0) {
|
||||
if ((IoRead8 (IdeRegisters->ErrOrFeature) & ATA_ERRREG_BBK) != 0) {
|
||||
DEBUG ((EFI_D_ERROR, "CheckRegisterStatus()-- %02x : Error : Bad Block Detected\n", IoRead8 (IdeRegisters->ErrOrFeature)));
|
||||
}
|
||||
|
||||
if ((IoRead8 (IdeRegisters->ErrOrFeature) & ATA_ERRREG_UNC) != 0) {
|
||||
DEBUG ((EFI_D_ERROR, "CheckRegisterStatus()-- %02x : Error : Uncorrectable Data\n", IoRead8 (IdeRegisters->ErrOrFeature)));
|
||||
}
|
||||
|
||||
if ((IoRead8 (IdeRegisters->ErrOrFeature) & ATA_ERRREG_MC) != 0) {
|
||||
DEBUG ((EFI_D_ERROR, "CheckRegisterStatus()-- %02x : Error : Media Change\n", IoRead8 (IdeRegisters->ErrOrFeature)));
|
||||
}
|
||||
|
||||
if ((IoRead8 (IdeRegisters->ErrOrFeature) & ATA_ERRREG_ABRT) != 0) {
|
||||
DEBUG ((EFI_D_ERROR, "CheckRegisterStatus()-- %02x : Error : Abort\n", IoRead8 (IdeRegisters->ErrOrFeature)));
|
||||
}
|
||||
|
||||
if ((IoRead8 (IdeRegisters->ErrOrFeature) & ATA_ERRREG_TK0NF) != 0) {
|
||||
DEBUG ((EFI_D_ERROR, "CheckRegisterStatus()-- %02x : Error : Track 0 Not Found\n", IoRead8 (IdeRegisters->ErrOrFeature)));
|
||||
}
|
||||
|
||||
if ((IoRead8 (IdeRegisters->ErrOrFeature) & ATA_ERRREG_AMNF) != 0) {
|
||||
DEBUG ((EFI_D_ERROR, "CheckRegisterStatus()-- %02x : Error : Address Mark Not Found\n", IoRead8 (IdeRegisters->ErrOrFeature)));
|
||||
}
|
||||
}
|
||||
DEBUG_CODE_END ();
|
||||
}
|
||||
|
||||
/**
|
||||
This function is used to analyze the Status Register and print out
|
||||
some debug information and if there is ERR bit set in the Status
|
||||
Register, the Error Register's Value is also be parsed and print out.
|
||||
|
||||
@param IdeRegisters A pointer to EFI_IDE_REGISTERS Data structure.
|
||||
|
||||
@retval EFI_SUCCESS No err information in the Status Register.
|
||||
@retval EFI_DEVICE_ERROR Any err information in the Status Register.
|
||||
|
||||
**/
|
||||
EFI_STATUS
|
||||
EFIAPI
|
||||
CheckStatusRegister (
|
||||
IN EFI_IDE_REGISTERS *IdeRegisters
|
||||
)
|
||||
{
|
||||
EFI_STATUS Status;
|
||||
UINT8 StatusRegister;
|
||||
|
||||
ASSERT (IdeRegisters != NULL);
|
||||
|
||||
StatusRegister = IoRead8 (IdeRegisters->CmdOrStatus);
|
||||
|
||||
if ((StatusRegister & (ATA_STSREG_ERR | ATA_STSREG_DWF | ATA_STSREG_CORR)) == 0) {
|
||||
Status = EFI_SUCCESS;
|
||||
} else {
|
||||
Status = EFI_DEVICE_ERROR;
|
||||
}
|
||||
|
||||
return Status;
|
||||
}
|
||||
|
||||
/**
|
||||
This function is used to poll for the DRQ bit clear in the Status
|
||||
Register. DRQ is cleared when the device is finished transferring Data.
|
||||
So this function is called after Data transfer is finished.
|
||||
|
||||
@param IdeRegisters A pointer to EFI_IDE_REGISTERS Data structure.
|
||||
@param Timeout The time to complete the command.
|
||||
|
||||
@retval EFI_SUCCESS DRQ bit clear within the time out.
|
||||
@retval EFI_TIMEOUT DRQ bit not clear within the time out.
|
||||
|
||||
@note
|
||||
Read Status Register will clear interrupt status.
|
||||
|
||||
**/
|
||||
EFI_STATUS
|
||||
EFIAPI
|
||||
DRQClear (
|
||||
IN EFI_IDE_REGISTERS *IdeRegisters,
|
||||
IN UINT64 Timeout
|
||||
)
|
||||
{
|
||||
UINT32 Delay;
|
||||
UINT8 StatusRegister;
|
||||
|
||||
ASSERT (IdeRegisters != NULL);
|
||||
|
||||
Delay = (UINT32) (DivU64x32(Timeout, 1000) + 1);
|
||||
do {
|
||||
StatusRegister = IoRead8 (IdeRegisters->CmdOrStatus);
|
||||
|
||||
//
|
||||
// wait for BSY == 0 and DRQ == 0
|
||||
//
|
||||
if ((StatusRegister & ATA_STSREG_BSY) == 0) {
|
||||
|
||||
if ((StatusRegister & ATA_STSREG_DRQ) == ATA_STSREG_DRQ) {
|
||||
return EFI_DEVICE_ERROR;
|
||||
} else {
|
||||
return EFI_SUCCESS;
|
||||
}
|
||||
}
|
||||
|
||||
//
|
||||
// Stall for 100 microseconds.
|
||||
//
|
||||
MicroSecondDelay (100);
|
||||
|
||||
Delay--;
|
||||
|
||||
} while (Delay > 0);
|
||||
|
||||
return EFI_TIMEOUT;
|
||||
}
|
||||
/**
|
||||
This function is used to poll for the DRQ bit clear in the Alternate
|
||||
Status Register. DRQ is cleared when the device is finished
|
||||
transferring Data. So this function is called after Data transfer
|
||||
is finished.
|
||||
|
||||
@param IdeRegisters A pointer to EFI_IDE_REGISTERS Data structure.
|
||||
@param Timeout The time to complete the command.
|
||||
|
||||
@retval EFI_SUCCESS DRQ bit clear within the time out.
|
||||
|
||||
@retval EFI_TIMEOUT DRQ bit not clear within the time out.
|
||||
@note Read Alternate Status Register will not clear interrupt status.
|
||||
|
||||
**/
|
||||
EFI_STATUS
|
||||
EFIAPI
|
||||
DRQClear2 (
|
||||
IN EFI_IDE_REGISTERS *IdeRegisters,
|
||||
IN UINT64 Timeout
|
||||
)
|
||||
{
|
||||
UINT32 Delay;
|
||||
UINT8 AltRegister;
|
||||
|
||||
ASSERT (IdeRegisters != NULL);
|
||||
|
||||
Delay = (UINT32) (DivU64x32(Timeout, 1000) + 1);
|
||||
do {
|
||||
AltRegister = IoRead8 (IdeRegisters->AltOrDev);
|
||||
|
||||
//
|
||||
// wait for BSY == 0 and DRQ == 0
|
||||
//
|
||||
if ((AltRegister & ATA_STSREG_BSY) == 0) {
|
||||
if ((AltRegister & ATA_STSREG_DRQ) == ATA_STSREG_DRQ) {
|
||||
return EFI_DEVICE_ERROR;
|
||||
} else {
|
||||
return EFI_SUCCESS;
|
||||
}
|
||||
}
|
||||
|
||||
//
|
||||
// Stall for 100 microseconds.
|
||||
//
|
||||
MicroSecondDelay (100);
|
||||
|
||||
Delay--;
|
||||
|
||||
} while (Delay > 0);
|
||||
|
||||
return EFI_TIMEOUT;
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
This function is used to poll for the DRQ bit set in the Alternate Status Register.
|
||||
DRQ is set when the device is ready to transfer Data. So this function is called after
|
||||
the command is sent to the device and before required Data is transferred.
|
||||
|
||||
@param IdeRegisters A pointer to EFI_IDE_REGISTERS Data structure.
|
||||
@param Timeout The time to complete the command.
|
||||
|
||||
@retval EFI_SUCCESS DRQ bit set within the time out.
|
||||
@retval EFI_TIMEOUT DRQ bit not set within the time out.
|
||||
@retval EFI_ABORTED DRQ bit not set caused by the command abort.
|
||||
@note Read Alternate Status Register will not clear interrupt status.
|
||||
|
||||
**/
|
||||
EFI_STATUS
|
||||
EFIAPI
|
||||
DRQReady2 (
|
||||
IN EFI_IDE_REGISTERS *IdeRegisters,
|
||||
IN UINT64 Timeout
|
||||
)
|
||||
{
|
||||
UINT32 Delay;
|
||||
UINT8 AltRegister;
|
||||
UINT8 ErrorRegister;
|
||||
|
||||
ASSERT (IdeRegisters != NULL);
|
||||
|
||||
Delay = (UINT32) (DivU64x32(Timeout, 1000) + 1);
|
||||
|
||||
do {
|
||||
//
|
||||
// Read Alternate Status Register will not clear interrupt status
|
||||
//
|
||||
AltRegister = IoRead8 (IdeRegisters->AltOrDev);
|
||||
//
|
||||
// BSY == 0 , DRQ == 1
|
||||
//
|
||||
if ((AltRegister & ATA_STSREG_BSY) == 0) {
|
||||
if ((AltRegister & ATA_STSREG_ERR) == ATA_STSREG_ERR) {
|
||||
ErrorRegister = IoRead8 (IdeRegisters->ErrOrFeature);
|
||||
|
||||
if ((ErrorRegister & ATA_ERRREG_ABRT) == ATA_ERRREG_ABRT) {
|
||||
return EFI_ABORTED;
|
||||
}
|
||||
return EFI_DEVICE_ERROR;
|
||||
}
|
||||
|
||||
if ((AltRegister & ATA_STSREG_DRQ) == ATA_STSREG_DRQ) {
|
||||
return EFI_SUCCESS;
|
||||
} else {
|
||||
return EFI_NOT_READY;
|
||||
}
|
||||
}
|
||||
|
||||
//
|
||||
// Stall for 100 microseconds.
|
||||
//
|
||||
MicroSecondDelay (100);
|
||||
|
||||
Delay--;
|
||||
} while (Delay > 0);
|
||||
|
||||
return EFI_TIMEOUT;
|
||||
}
|
||||
|
||||
/**
|
||||
This function is used to poll for the BSY bit clear in the Status Register. BSY
|
||||
is clear when the device is not busy. Every command must be sent after device is not busy.
|
||||
|
||||
@param IdeRegisters A pointer to EFI_IDE_REGISTERS Data structure.
|
||||
@param Timeout The time to complete the command.
|
||||
|
||||
@retval EFI_SUCCESS BSY bit clear within the time out.
|
||||
@retval EFI_TIMEOUT BSY bit not clear within the time out.
|
||||
|
||||
@note Read Status Register will clear interrupt status.
|
||||
**/
|
||||
EFI_STATUS
|
||||
EFIAPI
|
||||
WaitForBSYClear (
|
||||
IN EFI_IDE_REGISTERS *IdeRegisters,
|
||||
IN UINT64 Timeout
|
||||
)
|
||||
{
|
||||
UINT32 Delay;
|
||||
UINT8 StatusRegister;
|
||||
|
||||
ASSERT (IdeRegisters != NULL);
|
||||
|
||||
Delay = (UINT32) (DivU64x32(Timeout, 1000) + 1);
|
||||
do {
|
||||
StatusRegister = IoRead8 (IdeRegisters->CmdOrStatus);
|
||||
|
||||
if ((StatusRegister & ATA_STSREG_BSY) == 0x00) {
|
||||
return EFI_SUCCESS;
|
||||
}
|
||||
|
||||
//
|
||||
// Stall for 100 microseconds.
|
||||
//
|
||||
MicroSecondDelay (100);
|
||||
|
||||
Delay--;
|
||||
|
||||
} while (Delay > 0);
|
||||
|
||||
return EFI_TIMEOUT;
|
||||
}
|
||||
|
||||
/**
|
||||
Get IDE i/o port registers' base addresses by mode.
|
||||
|
||||
In 'Compatibility' mode, use fixed addresses.
|
||||
In Native-PCI mode, get base addresses from BARs in the PCI IDE controller's
|
||||
Configuration Space.
|
||||
|
||||
The steps to get IDE i/o port registers' base addresses for each channel
|
||||
as follows:
|
||||
|
||||
1. Examine the Programming Interface byte of the Class Code fields in PCI IDE
|
||||
controller's Configuration Space to determine the operating mode.
|
||||
|
||||
2. a) In 'Compatibility' mode, use fixed addresses shown in the Table 1 below.
|
||||
___________________________________________
|
||||
| | Command Block | Control Block |
|
||||
| Channel | Registers | Registers |
|
||||
|___________|_______________|_______________|
|
||||
| Primary | 1F0h - 1F7h | 3F6h - 3F7h |
|
||||
|___________|_______________|_______________|
|
||||
| Secondary | 170h - 177h | 376h - 377h |
|
||||
|___________|_______________|_______________|
|
||||
|
||||
Table 1. Compatibility resource mappings
|
||||
|
||||
b) In Native-PCI mode, IDE registers are mapped into IO space using the BARs
|
||||
in IDE controller's PCI Configuration Space, shown in the Table 2 below.
|
||||
___________________________________________________
|
||||
| | Command Block | Control Block |
|
||||
| Channel | Registers | Registers |
|
||||
|___________|___________________|___________________|
|
||||
| Primary | BAR at offset 0x10| BAR at offset 0x14|
|
||||
|___________|___________________|___________________|
|
||||
| Secondary | BAR at offset 0x18| BAR at offset 0x1C|
|
||||
|___________|___________________|___________________|
|
||||
|
||||
Table 2. BARs for Register Mapping
|
||||
|
||||
@param[in] Bus The bus number of ata host controller.
|
||||
@param[in] Device The device number of ata host controller.
|
||||
@param[in] Function The function number of ata host controller.
|
||||
@param[in, out] IdeRegisters Pointer to EFI_IDE_REGISTERS which is used to
|
||||
store the IDE i/o port registers' base addresses
|
||||
|
||||
@retval EFI_UNSUPPORTED Return this Value when the BARs is not IO type
|
||||
@retval EFI_SUCCESS Get the Base address successfully
|
||||
@retval Other Read the pci configureation Data error
|
||||
|
||||
**/
|
||||
EFI_STATUS
|
||||
EFIAPI
|
||||
GetIdeRegisterIoAddr (
|
||||
IN UINTN Bus,
|
||||
IN UINTN Device,
|
||||
IN UINTN Function,
|
||||
IN OUT EFI_IDE_REGISTERS *IdeRegisters
|
||||
)
|
||||
{
|
||||
UINT16 CommandBlockBaseAddr;
|
||||
UINT16 ControlBlockBaseAddr;
|
||||
UINT8 ClassCode;
|
||||
UINT32 BaseAddress[4];
|
||||
|
||||
if (IdeRegisters == NULL) {
|
||||
return EFI_INVALID_PARAMETER;
|
||||
}
|
||||
|
||||
ClassCode = PciRead8 (PCI_LIB_ADDRESS (Bus, Device, Function, 0x9));
|
||||
BaseAddress[0] = PciRead32 (PCI_LIB_ADDRESS (Bus, Device, Function, 0x10));
|
||||
BaseAddress[1] = PciRead32 (PCI_LIB_ADDRESS (Bus, Device, Function, 0x14));
|
||||
BaseAddress[2] = PciRead32 (PCI_LIB_ADDRESS (Bus, Device, Function, 0x18));
|
||||
BaseAddress[3] = PciRead32 (PCI_LIB_ADDRESS (Bus, Device, Function, 0x1C));
|
||||
|
||||
if ((ClassCode & IDE_PRIMARY_OPERATING_MODE) == 0) {
|
||||
CommandBlockBaseAddr = 0x1f0;
|
||||
ControlBlockBaseAddr = 0x3f6;
|
||||
} else {
|
||||
//
|
||||
// The BARs should be of IO type
|
||||
//
|
||||
if ((BaseAddress[0] & BIT0) == 0 ||
|
||||
(BaseAddress[1] & BIT0) == 0) {
|
||||
return EFI_UNSUPPORTED;
|
||||
}
|
||||
|
||||
CommandBlockBaseAddr = (UINT16) (BaseAddress[0] & 0x0000fff8);
|
||||
ControlBlockBaseAddr = (UINT16) ((BaseAddress[1] & 0x0000fffc) + 2);
|
||||
}
|
||||
|
||||
//
|
||||
// Calculate IDE primary channel I/O register base address.
|
||||
//
|
||||
IdeRegisters[EfiIdePrimary].Data = CommandBlockBaseAddr;
|
||||
IdeRegisters[EfiIdePrimary].ErrOrFeature = (UINT16) (CommandBlockBaseAddr + 0x01);
|
||||
IdeRegisters[EfiIdePrimary].SectorCount = (UINT16) (CommandBlockBaseAddr + 0x02);
|
||||
IdeRegisters[EfiIdePrimary].SectorNumber = (UINT16) (CommandBlockBaseAddr + 0x03);
|
||||
IdeRegisters[EfiIdePrimary].CylinderLsb = (UINT16) (CommandBlockBaseAddr + 0x04);
|
||||
IdeRegisters[EfiIdePrimary].CylinderMsb = (UINT16) (CommandBlockBaseAddr + 0x05);
|
||||
IdeRegisters[EfiIdePrimary].Head = (UINT16) (CommandBlockBaseAddr + 0x06);
|
||||
IdeRegisters[EfiIdePrimary].CmdOrStatus = (UINT16) (CommandBlockBaseAddr + 0x07);
|
||||
IdeRegisters[EfiIdePrimary].AltOrDev = ControlBlockBaseAddr;
|
||||
|
||||
if ((ClassCode & IDE_SECONDARY_OPERATING_MODE) == 0) {
|
||||
CommandBlockBaseAddr = 0x170;
|
||||
ControlBlockBaseAddr = 0x376;
|
||||
} else {
|
||||
//
|
||||
// The BARs should be of IO type
|
||||
//
|
||||
if ((BaseAddress[2] & BIT0) == 0 ||
|
||||
(BaseAddress[3] & BIT0) == 0) {
|
||||
return EFI_UNSUPPORTED;
|
||||
}
|
||||
|
||||
CommandBlockBaseAddr = (UINT16) (BaseAddress[2] & 0x0000fff8);
|
||||
ControlBlockBaseAddr = (UINT16) ((BaseAddress[3] & 0x0000fffc) + 2);
|
||||
}
|
||||
|
||||
//
|
||||
// Calculate IDE secondary channel I/O register base address.
|
||||
//
|
||||
IdeRegisters[EfiIdeSecondary].Data = CommandBlockBaseAddr;
|
||||
IdeRegisters[EfiIdeSecondary].ErrOrFeature = (UINT16) (CommandBlockBaseAddr + 0x01);
|
||||
IdeRegisters[EfiIdeSecondary].SectorCount = (UINT16) (CommandBlockBaseAddr + 0x02);
|
||||
IdeRegisters[EfiIdeSecondary].SectorNumber = (UINT16) (CommandBlockBaseAddr + 0x03);
|
||||
IdeRegisters[EfiIdeSecondary].CylinderLsb = (UINT16) (CommandBlockBaseAddr + 0x04);
|
||||
IdeRegisters[EfiIdeSecondary].CylinderMsb = (UINT16) (CommandBlockBaseAddr + 0x05);
|
||||
IdeRegisters[EfiIdeSecondary].Head = (UINT16) (CommandBlockBaseAddr + 0x06);
|
||||
IdeRegisters[EfiIdeSecondary].CmdOrStatus = (UINT16) (CommandBlockBaseAddr + 0x07);
|
||||
IdeRegisters[EfiIdeSecondary].AltOrDev = ControlBlockBaseAddr;
|
||||
|
||||
return EFI_SUCCESS;
|
||||
}
|
||||
|
||||
/**
|
||||
Send ATA Ext command into device with NON_DATA protocol.
|
||||
|
||||
@param IdeRegisters A pointer to EFI_IDE_REGISTERS Data structure.
|
||||
@param AtaCommandBlock A pointer to EFI_ATA_COMMAND_BLOCK Data structure.
|
||||
@param Timeout The time to complete the command.
|
||||
|
||||
@retval EFI_SUCCESS Reading succeed
|
||||
@retval EFI_DEVICE_ERROR Error executing commands on this device.
|
||||
|
||||
**/
|
||||
EFI_STATUS
|
||||
EFIAPI
|
||||
AtaIssueCommand (
|
||||
IN EFI_IDE_REGISTERS *IdeRegisters,
|
||||
IN EFI_ATA_COMMAND_BLOCK *AtaCommandBlock,
|
||||
IN UINT64 Timeout
|
||||
)
|
||||
{
|
||||
EFI_STATUS Status;
|
||||
UINT8 DeviceHead;
|
||||
UINT8 AtaCommand;
|
||||
|
||||
ASSERT (IdeRegisters != NULL);
|
||||
ASSERT (AtaCommandBlock != NULL);
|
||||
|
||||
DeviceHead = AtaCommandBlock->AtaDeviceHead;
|
||||
AtaCommand = AtaCommandBlock->AtaCommand;
|
||||
|
||||
Status = WaitForBSYClear (IdeRegisters, Timeout);
|
||||
if (EFI_ERROR (Status)) {
|
||||
return EFI_DEVICE_ERROR;
|
||||
}
|
||||
|
||||
//
|
||||
// Select device (bit4), set LBA mode(bit6) (use 0xe0 for compatibility)
|
||||
//
|
||||
IoWrite8 (IdeRegisters->Head, (UINT8) (0xe0 | DeviceHead));
|
||||
|
||||
//
|
||||
// set all the command parameters
|
||||
// Before write to all the following registers, BSY and DRQ must be 0.
|
||||
//
|
||||
Status = DRQClear2 (IdeRegisters, Timeout);
|
||||
if (EFI_ERROR (Status)) {
|
||||
return EFI_DEVICE_ERROR;
|
||||
}
|
||||
|
||||
//
|
||||
// Fill the feature register, which is a two-byte FIFO. Need write twice.
|
||||
//
|
||||
IoWrite8 (IdeRegisters->ErrOrFeature, AtaCommandBlock->AtaFeaturesExp);
|
||||
IoWrite8 (IdeRegisters->ErrOrFeature, AtaCommandBlock->AtaFeatures);
|
||||
|
||||
//
|
||||
// Fill the sector count register, which is a two-byte FIFO. Need write twice.
|
||||
//
|
||||
IoWrite8 (IdeRegisters->SectorCount, AtaCommandBlock->AtaSectorCountExp);
|
||||
IoWrite8 (IdeRegisters->SectorCount, AtaCommandBlock->AtaSectorCount);
|
||||
|
||||
//
|
||||
// Fill the start LBA registers, which are also two-byte FIFO
|
||||
//
|
||||
IoWrite8 (IdeRegisters->SectorNumber, AtaCommandBlock->AtaSectorNumberExp);
|
||||
IoWrite8 (IdeRegisters->SectorNumber, AtaCommandBlock->AtaSectorNumber);
|
||||
|
||||
IoWrite8 (IdeRegisters->CylinderLsb, AtaCommandBlock->AtaCylinderLowExp);
|
||||
IoWrite8 (IdeRegisters->CylinderLsb, AtaCommandBlock->AtaCylinderLow);
|
||||
|
||||
IoWrite8 (IdeRegisters->CylinderMsb, AtaCommandBlock->AtaCylinderHighExp);
|
||||
IoWrite8 (IdeRegisters->CylinderMsb, AtaCommandBlock->AtaCylinderHigh);
|
||||
|
||||
//
|
||||
// Send command via Command Register
|
||||
//
|
||||
IoWrite8 (IdeRegisters->CmdOrStatus, AtaCommand);
|
||||
|
||||
//
|
||||
// Stall at least 400 microseconds.
|
||||
//
|
||||
MicroSecondDelay (400);
|
||||
|
||||
return EFI_SUCCESS;
|
||||
}
|
||||
|
||||
/**
|
||||
This function is used to send out ATA commands conforms to the PIO Data In Protocol.
|
||||
|
||||
@param IdeRegisters A pointer to EFI_IDE_REGISTERS Data structure.
|
||||
@param Buffer A pointer to the source Buffer for the Data.
|
||||
@param ByteCount The Length of the Data.
|
||||
@param Read Flag used to determine the Data transfer direction.
|
||||
Read equals 1, means Data transferred from device to host;
|
||||
Read equals 0, means Data transferred from host to device.
|
||||
@param AtaCommandBlock A pointer to EFI_ATA_COMMAND_BLOCK Data structure.
|
||||
@param AtaStatusBlock A pointer to EFI_ATA_STATUS_BLOCK Data structure.
|
||||
@param Timeout The time to complete the command.
|
||||
|
||||
@retval EFI_SUCCESS send out the ATA command and device send required Data successfully.
|
||||
@retval EFI_DEVICE_ERROR command sent failed.
|
||||
|
||||
**/
|
||||
EFI_STATUS
|
||||
EFIAPI
|
||||
AtaPioDataInOut (
|
||||
IN EFI_IDE_REGISTERS *IdeRegisters,
|
||||
IN OUT VOID *Buffer,
|
||||
IN UINT64 ByteCount,
|
||||
IN BOOLEAN Read,
|
||||
IN EFI_ATA_COMMAND_BLOCK *AtaCommandBlock,
|
||||
IN OUT EFI_ATA_STATUS_BLOCK *AtaStatusBlock,
|
||||
IN UINT64 Timeout
|
||||
)
|
||||
{
|
||||
UINTN WordCount;
|
||||
UINTN Increment;
|
||||
UINT16 *Buffer16;
|
||||
EFI_STATUS Status;
|
||||
|
||||
if ((IdeRegisters == NULL) || (Buffer == NULL) || (AtaCommandBlock == NULL)) {
|
||||
return EFI_INVALID_PARAMETER;
|
||||
}
|
||||
|
||||
//
|
||||
// Issue ATA command
|
||||
//
|
||||
Status = AtaIssueCommand (IdeRegisters, AtaCommandBlock, Timeout);
|
||||
if (EFI_ERROR (Status)) {
|
||||
Status = EFI_DEVICE_ERROR;
|
||||
goto Exit;
|
||||
}
|
||||
|
||||
Buffer16 = (UINT16 *) Buffer;
|
||||
|
||||
//
|
||||
// According to PIO Data in protocol, host can perform a series of reads to
|
||||
// the Data register after each time device set DRQ ready;
|
||||
// The Data Size of "a series of read" is command specific.
|
||||
// For most ATA command, Data Size received from device will not exceed
|
||||
// 1 sector, hence the Data Size for "a series of read" can be the whole Data
|
||||
// Size of one command request.
|
||||
// For ATA command such as Read Sector command, the Data Size of one ATA
|
||||
// command request is often larger than 1 sector, according to the
|
||||
// Read Sector command, the Data Size of "a series of read" is exactly 1
|
||||
// sector.
|
||||
// Here for simplification reason, we specify the Data Size for
|
||||
// "a series of read" to 1 sector (256 words) if Data Size of one ATA command
|
||||
// request is larger than 256 words.
|
||||
//
|
||||
Increment = 256;
|
||||
|
||||
//
|
||||
// used to record bytes of currently transfered Data
|
||||
//
|
||||
WordCount = 0;
|
||||
|
||||
while (WordCount < RShiftU64(ByteCount, 1)) {
|
||||
//
|
||||
// Poll DRQ bit set, Data transfer can be performed only when DRQ is ready
|
||||
//
|
||||
Status = DRQReady2 (IdeRegisters, Timeout);
|
||||
if (EFI_ERROR (Status)) {
|
||||
Status = EFI_DEVICE_ERROR;
|
||||
goto Exit;
|
||||
}
|
||||
|
||||
//
|
||||
// Get the byte count for one series of read
|
||||
//
|
||||
if ((WordCount + Increment) > RShiftU64(ByteCount, 1)) {
|
||||
Increment = (UINTN)(RShiftU64(ByteCount, 1) - WordCount);
|
||||
}
|
||||
|
||||
if (Read) {
|
||||
IdeReadPortWMultiple (
|
||||
IdeRegisters->Data,
|
||||
Increment,
|
||||
Buffer16
|
||||
);
|
||||
} else {
|
||||
IdeWritePortWMultiple (
|
||||
IdeRegisters->Data,
|
||||
Increment,
|
||||
Buffer16
|
||||
);
|
||||
}
|
||||
|
||||
Status = CheckStatusRegister (IdeRegisters);
|
||||
if (EFI_ERROR (Status)) {
|
||||
Status = EFI_DEVICE_ERROR;
|
||||
goto Exit;
|
||||
}
|
||||
|
||||
WordCount += Increment;
|
||||
Buffer16 += Increment;
|
||||
}
|
||||
|
||||
Status = DRQClear (IdeRegisters, Timeout);
|
||||
if (EFI_ERROR (Status)) {
|
||||
Status = EFI_DEVICE_ERROR;
|
||||
goto Exit;
|
||||
}
|
||||
|
||||
Exit:
|
||||
//
|
||||
// Dump All Ide registers to ATA_STATUS_BLOCK
|
||||
//
|
||||
DumpAllIdeRegisters (IdeRegisters);
|
||||
|
||||
return Status;
|
||||
}
|
||||
|
||||
/**
|
||||
Sends out an ATA Identify Command to the specified device.
|
||||
|
||||
This function sends out the ATA Identify Command to the
|
||||
specified device. Only ATA device responses to this command. If
|
||||
the command succeeds, it returns the Identify Data structure which
|
||||
contains information about the device. This function extracts the
|
||||
information it needs to fill the IDE_BLK_IO_DEV Data structure,
|
||||
including device type, media block Size, media capacity, and etc.
|
||||
|
||||
@param IdeRegisters A pointer to EFI_IDE_REGISTERS Data structure.
|
||||
@param Channel The channel number of device.
|
||||
@param Device The device number of device.
|
||||
@param Buffer A pointer to Data Buffer which is used to contain IDENTIFY Data.
|
||||
|
||||
@retval EFI_SUCCESS Identify ATA device successfully.
|
||||
@retval EFI_DEVICE_ERROR ATA Identify Device Command failed or device is not ATA device.
|
||||
@retval EFI_OUT_OF_RESOURCES Allocate memory failed.
|
||||
**/
|
||||
EFI_STATUS
|
||||
EFIAPI
|
||||
AtaIdentify (
|
||||
IN EFI_IDE_REGISTERS *IdeRegisters,
|
||||
IN UINT8 Channel,
|
||||
IN UINT8 Device,
|
||||
IN OUT ATA_IDENTIFY_DATA *Buffer
|
||||
)
|
||||
{
|
||||
EFI_STATUS Status;
|
||||
EFI_ATA_COMMAND_BLOCK AtaCommandBlock;
|
||||
|
||||
ZeroMem (&AtaCommandBlock, sizeof (EFI_ATA_COMMAND_BLOCK));
|
||||
|
||||
AtaCommandBlock.AtaCommand = ATA_CMD_IDENTIFY_DRIVE;
|
||||
AtaCommandBlock.AtaDeviceHead = (UINT8)(Device << 0x4);
|
||||
|
||||
Status = AtaPioDataInOut (
|
||||
IdeRegisters,
|
||||
Buffer,
|
||||
sizeof (ATA_IDENTIFY_DATA),
|
||||
TRUE,
|
||||
&AtaCommandBlock,
|
||||
NULL,
|
||||
ATA_TIMEOUT
|
||||
);
|
||||
|
||||
return Status;
|
||||
}
|
||||
|
||||
|
||||
|
||||
|
|
@ -0,0 +1,173 @@
|
|||
/** @file
|
||||
Header file for IDE mode of ATA host controller.
|
||||
|
||||
Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>
|
||||
This program and the accompanying materials
|
||||
are licensed and made available under the terms and conditions of the BSD License
|
||||
which accompanies this distribution. The full text of the license may be found at
|
||||
http://opensource.org/licenses/bsd-license.php
|
||||
|
||||
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
|
||||
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
|
||||
|
||||
**/
|
||||
|
||||
|
||||
|
||||
#ifndef __OPAL_PASSWORD_IDE_MODE_H__
|
||||
#define __OPAL_PASSWORD_IDE_MODE_H__
|
||||
|
||||
typedef enum {
|
||||
EfiIdePrimary = 0,
|
||||
EfiIdeSecondary = 1,
|
||||
EfiIdeMaxChannel = 2
|
||||
} EFI_IDE_CHANNEL;
|
||||
|
||||
typedef enum {
|
||||
EfiIdeMaster = 0,
|
||||
EfiIdeSlave = 1,
|
||||
EfiIdeMaxDevice = 2
|
||||
} EFI_IDE_DEVICE;
|
||||
|
||||
//
|
||||
// IDE registers set
|
||||
//
|
||||
typedef struct {
|
||||
UINT16 Data;
|
||||
UINT16 ErrOrFeature;
|
||||
UINT16 SectorCount;
|
||||
UINT16 SectorNumber;
|
||||
UINT16 CylinderLsb;
|
||||
UINT16 CylinderMsb;
|
||||
UINT16 Head;
|
||||
UINT16 CmdOrStatus;
|
||||
UINT16 AltOrDev;
|
||||
} EFI_IDE_REGISTERS;
|
||||
|
||||
//
|
||||
// Bit definitions in Programming Interface byte of the Class Code field
|
||||
// in PCI IDE controller's Configuration Space
|
||||
//
|
||||
#define IDE_PRIMARY_OPERATING_MODE BIT0
|
||||
#define IDE_PRIMARY_PROGRAMMABLE_INDICATOR BIT1
|
||||
#define IDE_SECONDARY_OPERATING_MODE BIT2
|
||||
#define IDE_SECONDARY_PROGRAMMABLE_INDICATOR BIT3
|
||||
|
||||
/**
|
||||
Get IDE i/o port registers' base addresses by mode.
|
||||
|
||||
In 'Compatibility' mode, use fixed addresses.
|
||||
In Native-PCI mode, get base addresses from BARs in the PCI IDE controller's
|
||||
Configuration Space.
|
||||
|
||||
The steps to get IDE i/o port registers' base addresses for each channel
|
||||
as follows:
|
||||
|
||||
1. Examine the Programming Interface byte of the Class Code fields in PCI IDE
|
||||
controller's Configuration Space to determine the operating mode.
|
||||
|
||||
2. a) In 'Compatibility' mode, use fixed addresses shown in the Table 1 below.
|
||||
___________________________________________
|
||||
| | Command Block | Control Block |
|
||||
| Channel | Registers | Registers |
|
||||
|___________|_______________|_______________|
|
||||
| Primary | 1F0h - 1F7h | 3F6h - 3F7h |
|
||||
|___________|_______________|_______________|
|
||||
| Secondary | 170h - 177h | 376h - 377h |
|
||||
|___________|_______________|_______________|
|
||||
|
||||
Table 1. Compatibility resource mappings
|
||||
|
||||
b) In Native-PCI mode, IDE registers are mapped into IO space using the BARs
|
||||
in IDE controller's PCI Configuration Space, shown in the Table 2 below.
|
||||
___________________________________________________
|
||||
| | Command Block | Control Block |
|
||||
| Channel | Registers | Registers |
|
||||
|___________|___________________|___________________|
|
||||
| Primary | BAR at offset 0x10| BAR at offset 0x14|
|
||||
|___________|___________________|___________________|
|
||||
| Secondary | BAR at offset 0x18| BAR at offset 0x1C|
|
||||
|___________|___________________|___________________|
|
||||
|
||||
Table 2. BARs for Register Mapping
|
||||
|
||||
@param[in] Bus The bus number of ata host controller.
|
||||
@param[in] Device The device number of ata host controller.
|
||||
@param[in] Function The function number of ata host controller.
|
||||
@param[in, out] IdeRegisters Pointer to EFI_IDE_REGISTERS which is used to
|
||||
store the IDE i/o port registers' base addresses
|
||||
|
||||
@retval EFI_UNSUPPORTED Return this Value when the BARs is not IO type
|
||||
@retval EFI_SUCCESS Get the Base address successfully
|
||||
@retval Other Read the pci configureation Data error
|
||||
|
||||
**/
|
||||
EFI_STATUS
|
||||
EFIAPI
|
||||
GetIdeRegisterIoAddr (
|
||||
IN UINTN Bus,
|
||||
IN UINTN Device,
|
||||
IN UINTN Function,
|
||||
IN OUT EFI_IDE_REGISTERS *IdeRegisters
|
||||
);
|
||||
|
||||
/**
|
||||
Sends out an ATA Identify Command to the specified device.
|
||||
|
||||
This function sends out the ATA Identify Command to the
|
||||
specified device. Only ATA device responses to this command. If
|
||||
the command succeeds, it returns the Identify Data structure which
|
||||
contains information about the device. This function extracts the
|
||||
information it needs to fill the IDE_BLK_IO_DEV Data structure,
|
||||
including device type, media block Size, media capacity, and etc.
|
||||
|
||||
@param IdeRegisters A pointer to EFI_IDE_REGISTERS Data structure.
|
||||
@param Channel The channel number of device.
|
||||
@param Device The device number of device.
|
||||
@param Buffer A pointer to Data Buffer which is used to contain IDENTIFY Data.
|
||||
|
||||
@retval EFI_SUCCESS Identify ATA device successfully.
|
||||
@retval EFI_DEVICE_ERROR ATA Identify Device Command failed or device is not ATA device.
|
||||
@retval EFI_OUT_OF_RESOURCES Allocate memory failed.
|
||||
**/
|
||||
EFI_STATUS
|
||||
EFIAPI
|
||||
AtaIdentify (
|
||||
IN EFI_IDE_REGISTERS *IdeRegisters,
|
||||
IN UINT8 Channel,
|
||||
IN UINT8 Device,
|
||||
IN OUT ATA_IDENTIFY_DATA *Buffer
|
||||
);
|
||||
|
||||
/**
|
||||
This function is used to send out ATA commands conforms to the PIO Data In Protocol.
|
||||
|
||||
@param IdeRegisters A pointer to EFI_IDE_REGISTERS Data structure.
|
||||
@param Buffer A pointer to the source Buffer for the Data.
|
||||
@param ByteCount The Length of the Data.
|
||||
@param Read Flag used to determine the Data transfer direction.
|
||||
Read equals 1, means Data transferred from device to host;
|
||||
Read equals 0, means Data transferred from host to device.
|
||||
@param AtaCommandBlock A pointer to EFI_ATA_COMMAND_BLOCK Data structure.
|
||||
@param AtaStatusBlock A pointer to EFI_ATA_STATUS_BLOCK Data structure.
|
||||
@param Timeout The time to complete the command.
|
||||
|
||||
@retval EFI_SUCCESS send out the ATA command and device send required Data successfully.
|
||||
@retval EFI_DEVICE_ERROR command sent failed.
|
||||
|
||||
**/
|
||||
EFI_STATUS
|
||||
EFIAPI
|
||||
AtaPioDataInOut (
|
||||
IN EFI_IDE_REGISTERS *IdeRegisters,
|
||||
IN OUT VOID *Buffer,
|
||||
IN UINT64 ByteCount,
|
||||
IN BOOLEAN Read,
|
||||
IN EFI_ATA_COMMAND_BLOCK *AtaCommandBlock,
|
||||
IN OUT EFI_ATA_STATUS_BLOCK *AtaStatusBlock,
|
||||
IN UINT64 Timeout
|
||||
);
|
||||
|
||||
|
||||
#endif
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,456 @@
|
|||
/** @file
|
||||
Header file for NVMe function definitions
|
||||
|
||||
Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>
|
||||
This program and the accompanying materials
|
||||
are licensed and made available under the terms and conditions of the BSD License
|
||||
which accompanies this distribution. The full text of the license may be found at
|
||||
http://opensource.org/licenses/bsd-license.php
|
||||
|
||||
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
|
||||
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
|
||||
|
||||
**/
|
||||
|
||||
#ifndef __OPAL_PASSWORD_NVME_MODE_H__
|
||||
#define __OPAL_PASSWORD_NVME_MODE_H__
|
||||
|
||||
|
||||
#include "OpalNvmeReg.h"
|
||||
|
||||
#define NVME_MAX_SECTORS 0x10000
|
||||
//
|
||||
// QueueId
|
||||
//
|
||||
#define NVME_ADMIN_QUEUE 0x00
|
||||
#define NVME_IO_QUEUE 0x01
|
||||
|
||||
typedef struct {
|
||||
UINT8 Opcode;
|
||||
UINT8 FusedOperation;
|
||||
#define NORMAL_CMD 0x00
|
||||
#define FUSED_FIRST_CMD 0x01
|
||||
#define FUSED_SECOND_CMD 0x02
|
||||
UINT16 Cid;
|
||||
} NVME_CDW0;
|
||||
|
||||
typedef struct {
|
||||
NVME_CDW0 Cdw0;
|
||||
UINT8 Flags;
|
||||
#define CDW10_VALID 0x01
|
||||
#define CDW11_VALID 0x02
|
||||
#define CDW12_VALID 0x04
|
||||
#define CDW13_VALID 0x08
|
||||
#define CDW14_VALID 0x10
|
||||
#define CDW15_VALID 0x20
|
||||
UINT32 Nsid;
|
||||
UINT32 Cdw10;
|
||||
UINT32 Cdw11;
|
||||
UINT32 Cdw12;
|
||||
UINT32 Cdw13;
|
||||
UINT32 Cdw14;
|
||||
UINT32 Cdw15;
|
||||
} NVM_EXPRESS_COMMAND;
|
||||
|
||||
typedef struct {
|
||||
UINT32 Cdw0;
|
||||
UINT32 Cdw1;
|
||||
UINT32 Cdw2;
|
||||
UINT32 Cdw3;
|
||||
} NVM_EXPRESS_RESPONSE;
|
||||
|
||||
typedef struct {
|
||||
UINT64 CommandTimeout;
|
||||
UINT64 TransferBuffer;
|
||||
UINT32 TransferLength;
|
||||
UINT64 MetadataBuffer;
|
||||
UINT32 MetadataLength;
|
||||
UINT8 QueueId;
|
||||
NVM_EXPRESS_COMMAND *NvmeCmd;
|
||||
NVM_EXPRESS_RESPONSE *NvmeResponse;
|
||||
} NVM_EXPRESS_PASS_THRU_COMMAND_PACKET;
|
||||
|
||||
|
||||
#pragma pack(1)
|
||||
|
||||
// Internal fields
|
||||
typedef enum {
|
||||
NvmeStatusUnknown,
|
||||
NvmeStatusInit,
|
||||
NvmeStatusInuse,
|
||||
NvmeStatusMax,
|
||||
} NVME_STATUS;
|
||||
|
||||
typedef struct {
|
||||
UINT32 Nbar;
|
||||
UINT32 BaseMem;
|
||||
BOOLEAN PollCancellation;
|
||||
UINT16 NvmeInitWaitTime;
|
||||
|
||||
NVME_STATUS State;
|
||||
UINT8 BusID;
|
||||
UINT8 DeviceID;
|
||||
UINT8 FuncID;
|
||||
UINTN PciBase;
|
||||
|
||||
UINT32 Nsid;
|
||||
UINT64 Nsuuid;
|
||||
UINT32 BlockSize;
|
||||
EFI_LBA LastBlock;
|
||||
|
||||
//
|
||||
// Pointers to 4kB aligned submission & completion queues.
|
||||
//
|
||||
NVME_SQ *SqBuffer[NVME_MAX_IO_QUEUES];
|
||||
NVME_CQ *CqBuffer[NVME_MAX_IO_QUEUES];
|
||||
UINT16 Cid[NVME_MAX_IO_QUEUES];
|
||||
|
||||
//
|
||||
// Submission and completion queue indices.
|
||||
//
|
||||
NVME_SQTDBL SqTdbl[NVME_MAX_IO_QUEUES];
|
||||
NVME_CQHDBL CqHdbl[NVME_MAX_IO_QUEUES];
|
||||
UINT8 Pt[NVME_MAX_IO_QUEUES];
|
||||
|
||||
UINTN SqeCount[NVME_MAX_IO_QUEUES];
|
||||
|
||||
//
|
||||
// Nvme controller capabilities
|
||||
//
|
||||
NVME_CAP Cap;
|
||||
|
||||
//
|
||||
// pointer to identify controller Data
|
||||
//
|
||||
NVME_ADMIN_CONTROLLER_DATA *ControllerData;
|
||||
NVME_ADMIN_NAMESPACE_DATA *NamespaceData;
|
||||
} NVME_CONTEXT;
|
||||
|
||||
#pragma pack()
|
||||
|
||||
/**
|
||||
Transfer MMIO Data to memory.
|
||||
|
||||
@param[in,out] MemBuffer - Destination: Memory address
|
||||
@param[in] MmioAddr - Source: MMIO address
|
||||
@param[in] Size - Size for read
|
||||
|
||||
@retval EFI_SUCCESS - MMIO read sucessfully
|
||||
**/
|
||||
EFI_STATUS
|
||||
NvmeMmioRead (
|
||||
IN OUT VOID *MemBuffer,
|
||||
IN UINTN MmioAddr,
|
||||
IN UINTN Size
|
||||
);
|
||||
|
||||
/**
|
||||
Transfer memory Data to MMIO.
|
||||
|
||||
@param[in,out] MmioAddr - Destination: MMIO address
|
||||
@param[in] MemBuffer - Source: Memory address
|
||||
@param[in] Size - Size for write
|
||||
|
||||
@retval EFI_SUCCESS - MMIO write sucessfully
|
||||
**/
|
||||
EFI_STATUS
|
||||
NvmeMmioWrite (
|
||||
IN OUT UINTN MmioAddr,
|
||||
IN VOID *MemBuffer,
|
||||
IN UINTN Size
|
||||
);
|
||||
|
||||
/**
|
||||
Transfer memory data to MMIO.
|
||||
|
||||
@param[in,out] MmioAddr - Destination: MMIO address
|
||||
@param[in] MemBuffer - Source: Memory address
|
||||
@param[in] Size - Size for write
|
||||
|
||||
@retval EFI_SUCCESS - MMIO write sucessfully
|
||||
**/
|
||||
EFI_STATUS
|
||||
OpalPciWrite (
|
||||
IN OUT UINTN MmioAddr,
|
||||
IN VOID *MemBuffer,
|
||||
IN UINTN Size
|
||||
);
|
||||
|
||||
/**
|
||||
Transfer MMIO data to memory.
|
||||
|
||||
@param[in,out] MemBuffer - Destination: Memory address
|
||||
@param[in] MmioAddr - Source: MMIO address
|
||||
@param[in] Size - Size for read
|
||||
|
||||
@retval EFI_SUCCESS - MMIO read sucessfully
|
||||
**/
|
||||
EFI_STATUS
|
||||
OpalPciRead (
|
||||
IN OUT VOID *MemBuffer,
|
||||
IN UINTN MmioAddr,
|
||||
IN UINTN Size
|
||||
);
|
||||
|
||||
/**
|
||||
Allocate transfer-related Data struct which is used at Nvme.
|
||||
|
||||
@param[in] ImageHandle Image handle for this driver image
|
||||
@param[in] Nvme The pointer to the NVME_CONTEXT Data structure.
|
||||
|
||||
@retval EFI_OUT_OF_RESOURCE The allocation is failure.
|
||||
@retval EFI_SUCCESS Successful to allocate memory.
|
||||
|
||||
**/
|
||||
EFI_STATUS
|
||||
EFIAPI
|
||||
NvmeAllocateResource (
|
||||
IN EFI_HANDLE ImageHandle,
|
||||
IN NVME_CONTEXT *Nvme
|
||||
);
|
||||
|
||||
/**
|
||||
Free allocated transfer-related Data struct which is used at NVMe.
|
||||
|
||||
@param[in] Nvme The pointer to the NVME_CONTEXT Data structure.
|
||||
|
||||
**/
|
||||
VOID
|
||||
EFIAPI
|
||||
NvmeFreeResource (
|
||||
IN NVME_CONTEXT *Nvme
|
||||
);
|
||||
|
||||
/**
|
||||
Sends an NVM Express Command Packet to an NVM Express controller or namespace. This function supports
|
||||
both blocking I/O and nonblocking I/O. The blocking I/O functionality is required, and the nonblocking
|
||||
I/O functionality is optional.
|
||||
|
||||
@param[in] Nvme - The pointer to the NVME_CONTEXT Data structure.
|
||||
@param[in] NamespaceId - Is a 32 bit Namespace ID to which the Express HCI command packet will be sent.
|
||||
A Value of 0 denotes the NVM Express controller, a Value of all 0FFh in the namespace
|
||||
ID specifies that the command packet should be sent to all valid namespaces.
|
||||
@param[in] NamespaceUuid - Is a 64 bit Namespace UUID to which the Express HCI command packet will be sent.
|
||||
A Value of 0 denotes the NVM Express controller, a Value of all 0FFh in the namespace
|
||||
UUID specifies that the command packet should be sent to all valid namespaces.
|
||||
@param[in,out] Packet - A pointer to the NVM Express HCI Command Packet to send to the NVMe namespace specified
|
||||
by NamespaceId.
|
||||
|
||||
@retval EFI_SUCCESS - The NVM Express Command Packet was sent by the host. TransferLength bytes were transferred
|
||||
to, or from DataBuffer.
|
||||
@retval EFI_NOT_READY - The NVM Express Command Packet could not be sent because the controller is not ready. The caller
|
||||
may retry again later.
|
||||
@retval EFI_DEVICE_ERROR - A device error occurred while attempting to send the NVM Express Command Packet.
|
||||
@retval EFI_INVALID_PARAMETER - Namespace, or the contents of NVM_EXPRESS_PASS_THRU_COMMAND_PACKET are invalid. The NVM
|
||||
Express Command Packet was not sent, so no additional status information is available.
|
||||
@retval EFI_UNSUPPORTED - The command described by the NVM Express Command Packet is not supported by the host adapter.
|
||||
The NVM Express Command Packet was not sent, so no additional status information is available.
|
||||
@retval EFI_TIMEOUT - A timeout occurred while waiting for the NVM Express Command Packet to execute.
|
||||
|
||||
**/
|
||||
EFI_STATUS
|
||||
NvmePassThru (
|
||||
IN NVME_CONTEXT *Nvme,
|
||||
IN UINT32 NamespaceId,
|
||||
IN UINT64 NamespaceUuid,
|
||||
IN OUT NVM_EXPRESS_PASS_THRU_COMMAND_PACKET *Packet
|
||||
);
|
||||
|
||||
/**
|
||||
Waits until all NVME commands completed.
|
||||
|
||||
@param[in] Nvme - The pointer to the NVME_CONTEXT Data structure.
|
||||
@param[in] Qid - Queue index
|
||||
|
||||
@retval EFI_SUCCESS - All NVME commands have completed
|
||||
@retval EFI_TIMEOUT - Timeout occured
|
||||
@retval EFI_NOT_READY - Not all NVME commands have completed
|
||||
@retval others - Error occurred on device side.
|
||||
**/
|
||||
EFI_STATUS
|
||||
NvmeWaitAllComplete (
|
||||
IN NVME_CONTEXT *Nvme,
|
||||
IN UINT8 Qid
|
||||
);
|
||||
|
||||
/**
|
||||
Initialize the Nvm Express controller.
|
||||
|
||||
@param[in] Nvme - The pointer to the NVME_CONTEXT Data structure.
|
||||
|
||||
@retval EFI_SUCCESS - The NVM Express Controller is initialized successfully.
|
||||
@retval Others - A device error occurred while initializing the controller.
|
||||
|
||||
**/
|
||||
EFI_STATUS
|
||||
NvmeControllerInit (
|
||||
IN NVME_CONTEXT *Nvme
|
||||
);
|
||||
|
||||
/**
|
||||
Un-initialize the Nvm Express controller.
|
||||
|
||||
@param[in] Nvme - The pointer to the NVME_CONTEXT Data structure.
|
||||
|
||||
@retval EFI_SUCCESS - The NVM Express Controller is un-initialized successfully.
|
||||
@retval Others - A device error occurred while un-initializing the controller.
|
||||
|
||||
**/
|
||||
EFI_STATUS
|
||||
NvmeControllerExit (
|
||||
IN NVME_CONTEXT *Nvme
|
||||
);
|
||||
|
||||
/**
|
||||
Check whether there are available command slots.
|
||||
|
||||
@param[in] Nvme - The pointer to the NVME_CONTEXT Data structure.
|
||||
@param[in] Qid - Queue index
|
||||
|
||||
@retval EFI_SUCCESS - Available command slot is found
|
||||
@retval EFI_NOT_READY - No available command slot is found
|
||||
@retval EFI_DEVICE_ERROR - Error occurred on device side.
|
||||
|
||||
**/
|
||||
EFI_STATUS
|
||||
NvmeHasFreeCmdSlot (
|
||||
IN NVME_CONTEXT *Nvme,
|
||||
IN UINT8 Qid
|
||||
);
|
||||
|
||||
/**
|
||||
Check whether all command slots are clean.
|
||||
|
||||
@param[in] Nvme - The pointer to the NVME_CONTEXT Data structure.
|
||||
@param[in] Qid - Queue index
|
||||
|
||||
@retval EFI_SUCCESS - All command slots are clean
|
||||
@retval EFI_NOT_READY - Not all command slots are clean
|
||||
@retval EFI_DEVICE_ERROR - Error occurred on device side.
|
||||
|
||||
**/
|
||||
EFI_STATUS
|
||||
NvmeIsAllCmdSlotClean (
|
||||
IN NVME_CONTEXT *Nvme,
|
||||
IN UINT8 Qid
|
||||
);
|
||||
|
||||
/**
|
||||
Read sector Data from the NVMe device.
|
||||
|
||||
@param[in] Nvme - The pointer to the NVME_CONTEXT Data structure.
|
||||
@param[in,out] Buffer - The Buffer used to store the Data read from the device.
|
||||
@param[in] Lba - The start block number.
|
||||
@param[in] Blocks - Total block number to be read.
|
||||
|
||||
@retval EFI_SUCCESS - Datum are read from the device.
|
||||
@retval Others - Fail to read all the datum.
|
||||
|
||||
**/
|
||||
EFI_STATUS
|
||||
NvmeReadSectors (
|
||||
IN NVME_CONTEXT *Nvme,
|
||||
IN OUT UINT64 Buffer,
|
||||
IN UINT64 Lba,
|
||||
IN UINT32 Blocks
|
||||
);
|
||||
|
||||
/**
|
||||
Write sector Data to the NVMe device.
|
||||
|
||||
@param[in] Nvme - The pointer to the NVME_CONTEXT Data structure.
|
||||
@param[in] Buffer - The Buffer to be written into the device.
|
||||
@param[in] Lba - The start block number.
|
||||
@param[in] Blocks - Total block number to be written.
|
||||
|
||||
@retval EFI_SUCCESS - Datum are written into the Buffer.
|
||||
@retval Others - Fail to write all the datum.
|
||||
|
||||
**/
|
||||
EFI_STATUS
|
||||
NvmeWriteSectors (
|
||||
IN NVME_CONTEXT *Nvme,
|
||||
IN UINT64 Buffer,
|
||||
IN UINT64 Lba,
|
||||
IN UINT32 Blocks
|
||||
);
|
||||
|
||||
/**
|
||||
Flushes all modified Data to the device.
|
||||
|
||||
@param[in] Nvme - The pointer to the NVME_CONTEXT Data structure.
|
||||
|
||||
@retval EFI_SUCCESS - Datum are written into the Buffer.
|
||||
@retval Others - Fail to write all the datum.
|
||||
|
||||
**/
|
||||
EFI_STATUS
|
||||
NvmeFlush (
|
||||
IN NVME_CONTEXT *Nvme
|
||||
);
|
||||
|
||||
/**
|
||||
Read some blocks from the device.
|
||||
|
||||
@param[in] Nvme - The pointer to the NVME_CONTEXT Data structure.
|
||||
@param[out] Buffer - The Buffer used to store the Data read from the device.
|
||||
@param[in] Lba - The start block number.
|
||||
@param[in] Blocks - Total block number to be read.
|
||||
|
||||
@retval EFI_SUCCESS - Datum are read from the device.
|
||||
@retval Others - Fail to read all the datum.
|
||||
|
||||
**/
|
||||
EFI_STATUS
|
||||
NvmeRead (
|
||||
IN NVME_CONTEXT *Nvme,
|
||||
OUT UINT64 Buffer,
|
||||
IN UINT64 Lba,
|
||||
IN UINTN Blocks
|
||||
);
|
||||
|
||||
/**
|
||||
Write some blocks to the device.
|
||||
|
||||
@param[in] Nvme - The pointer to the NVME_CONTEXT Data structure.
|
||||
@param[in] Buffer - The Buffer to be written into the device.
|
||||
@param[in] Lba - The start block number.
|
||||
@param[in] Blocks - Total block number to be written.
|
||||
|
||||
@retval EFI_SUCCESS - Datum are written into the Buffer.
|
||||
@retval Others - Fail to write all the datum.
|
||||
|
||||
**/
|
||||
EFI_STATUS
|
||||
NvmeWrite (
|
||||
IN NVME_CONTEXT *Nvme,
|
||||
IN UINT64 Buffer,
|
||||
IN UINT64 Lba,
|
||||
IN UINTN Blocks
|
||||
);
|
||||
|
||||
/**
|
||||
Security send and receive commands.
|
||||
|
||||
@param[in] Nvme - The pointer to the NVME_CONTEXT Data structure.
|
||||
@param[in] SendCommand - The flag to indicate the command type, TRUE for Send command and FALSE for receive command
|
||||
@param[in] SecurityProtocol - Security Protocol
|
||||
@param[in] SpSpecific - Security Protocol Specific
|
||||
@param[in] TransferLength - Transfer Length of Buffer (in bytes) - always a multiple of 512
|
||||
@param[in,out] TransferBuffer - Address of Data to transfer
|
||||
|
||||
@return EFI_SUCCESS - Successfully create io submission queue.
|
||||
@return others - Fail to send/receive commands.
|
||||
|
||||
**/
|
||||
EFI_STATUS
|
||||
NvmeSecuritySendReceive (
|
||||
IN NVME_CONTEXT *Nvme,
|
||||
IN BOOLEAN SendCommand,
|
||||
IN UINT8 SecurityProtocol,
|
||||
IN UINT16 SpSpecific,
|
||||
IN UINTN TransferLength,
|
||||
IN OUT VOID *TransferBuffer
|
||||
);
|
||||
|
||||
#endif
|
||||
|
|
@ -0,0 +1,814 @@
|
|||
/** @file
|
||||
Header file for Registers and Structure definitions
|
||||
|
||||
Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>
|
||||
This program and the accompanying materials
|
||||
are licensed and made available under the terms and conditions of the BSD License
|
||||
which accompanies this distribution. The full text of the license may be found at
|
||||
http://opensource.org/licenses/bsd-license.php
|
||||
|
||||
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
|
||||
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
|
||||
|
||||
**/
|
||||
#ifndef __OPAL_PASSWORD_NVME_REG_H__
|
||||
#define __OPAL_PASSWORD_NVME_REG_H__
|
||||
|
||||
//
|
||||
// PCI Header for PCIe root port configuration
|
||||
//
|
||||
#define NVME_PCIE_PCICMD 0x04
|
||||
#define NVME_PCIE_BNUM 0x18
|
||||
#define NVME_PCIE_SEC_BNUM 0x19
|
||||
#define NVME_PCIE_IOBL 0x1C
|
||||
#define NVME_PCIE_MBL 0x20
|
||||
#define NVME_PCIE_PMBL 0x24
|
||||
#define NVME_PCIE_PMBU32 0x28
|
||||
#define NVME_PCIE_PMLU32 0x2C
|
||||
#define NVME_PCIE_INTR 0x3C
|
||||
|
||||
//
|
||||
// NVMe related definitions
|
||||
//
|
||||
#define PCI_CLASS_MASS_STORAGE_NVM 0x08 // mass storage sub-class non-volatile memory.
|
||||
#define PCI_IF_NVMHCI 0x02 // mass storage programming interface NVMHCI.
|
||||
|
||||
#define NVME_ASQ_SIZE 1 // Number of admin submission queue entries, which is 0-based
|
||||
#define NVME_ACQ_SIZE 1 // Number of admin completion queue entries, which is 0-based
|
||||
|
||||
#define NVME_CSQ_SIZE 63 // Number of I/O submission queue entries, which is 0-based
|
||||
#define NVME_CCQ_SIZE 63 // Number of I/O completion queue entries, which is 0-based
|
||||
|
||||
#define NVME_MAX_IO_QUEUES 2 // Number of I/O queues supported by the driver, 1 for AQ, 1 for CQ
|
||||
|
||||
#define NVME_CSQ_DEPTH (NVME_CSQ_SIZE+1)
|
||||
#define NVME_CCQ_DEPTH (NVME_CCQ_SIZE+1)
|
||||
#define NVME_PRP_SIZE (4) // Pages of PRP list
|
||||
|
||||
#define NVME_CONTROLLER_ID 0
|
||||
|
||||
//
|
||||
// Time out Value for Nvme transaction execution
|
||||
//
|
||||
#define NVME_GENERIC_TIMEOUT 5000000 ///< us
|
||||
#define NVME_CMD_WAIT 100 ///< us
|
||||
#define NVME_CMD_TIMEOUT 20000000 ///< us
|
||||
|
||||
|
||||
|
||||
#define NVME_MEM_MAX_SIZE \
|
||||
(( \
|
||||
1 /* Controller Data */ + \
|
||||
1 /* Identify Data */ + \
|
||||
1 /* ASQ */ + \
|
||||
1 /* ACQ */ + \
|
||||
1 /* SQs */ + \
|
||||
1 /* CQs */ + \
|
||||
NVME_PRP_SIZE * NVME_CSQ_DEPTH /* PRPs */ \
|
||||
) * EFI_PAGE_SIZE)
|
||||
|
||||
|
||||
//
|
||||
// controller register offsets
|
||||
//
|
||||
#define NVME_CAP_OFFSET 0x0000 // Controller Capabilities
|
||||
#define NVME_VER_OFFSET 0x0008 // Version
|
||||
#define NVME_INTMS_OFFSET 0x000c // Interrupt Mask Set
|
||||
#define NVME_INTMC_OFFSET 0x0010 // Interrupt Mask Clear
|
||||
#define NVME_CC_OFFSET 0x0014 // Controller Configuration
|
||||
#define NVME_CSTS_OFFSET 0x001c // Controller Status
|
||||
#define NVME_AQA_OFFSET 0x0024 // Admin Queue Attributes
|
||||
#define NVME_ASQ_OFFSET 0x0028 // Admin Submission Queue Base Address
|
||||
#define NVME_ACQ_OFFSET 0x0030 // Admin Completion Queue Base Address
|
||||
#define NVME_SQ0_OFFSET 0x1000 // Submission Queue 0 (admin) Tail Doorbell
|
||||
#define NVME_CQ0_OFFSET 0x1004 // Completion Queue 0 (admin) Head Doorbell
|
||||
|
||||
//
|
||||
// These register offsets are defined as 0x1000 + (N * (4 << CAP.DSTRD))
|
||||
// Get the doorbell stride bit shift Value from the controller capabilities.
|
||||
//
|
||||
#define NVME_SQTDBL_OFFSET(QID, DSTRD) 0x1000 + ((2 * (QID)) * (4 << (DSTRD))) // Submission Queue y (NVM) Tail Doorbell
|
||||
#define NVME_CQHDBL_OFFSET(QID, DSTRD) 0x1000 + (((2 * (QID)) + 1) * (4 << (DSTRD))) // Completion Queue y (NVM) Head Doorbell
|
||||
|
||||
|
||||
#pragma pack(1)
|
||||
|
||||
//
|
||||
// 3.1.1 Offset 00h: CAP - Controller Capabilities
|
||||
//
|
||||
typedef struct {
|
||||
UINT16 Mqes; // Maximum Queue Entries Supported
|
||||
UINT8 Cqr:1; // Contiguous Queues Required
|
||||
UINT8 Ams:2; // Arbitration Mechanism Supported
|
||||
UINT8 Rsvd1:5;
|
||||
UINT8 To; // Timeout
|
||||
UINT16 Dstrd:4;
|
||||
UINT16 Rsvd2:1;
|
||||
UINT16 Css:4; // Command Sets Supported
|
||||
UINT16 Rsvd3:7;
|
||||
UINT8 Mpsmin:4;
|
||||
UINT8 Mpsmax:4;
|
||||
UINT8 Rsvd4;
|
||||
} NVME_CAP;
|
||||
|
||||
//
|
||||
// 3.1.2 Offset 08h: VS - Version
|
||||
//
|
||||
typedef struct {
|
||||
UINT16 Mnr; // Minor version number
|
||||
UINT16 Mjr; // Major version number
|
||||
} NVME_VER;
|
||||
|
||||
//
|
||||
// 3.1.5 Offset 14h: CC - Controller Configuration
|
||||
//
|
||||
typedef struct {
|
||||
UINT16 En:1; // Enable
|
||||
UINT16 Rsvd1:3;
|
||||
UINT16 Css:3; // Command Set Selected
|
||||
UINT16 Mps:4; // Memory Page Size
|
||||
UINT16 Ams:3; // Arbitration Mechanism Selected
|
||||
UINT16 Shn:2; // Shutdown Notification
|
||||
UINT8 Iosqes:4; // I/O Submission Queue Entry Size
|
||||
UINT8 Iocqes:4; // I/O Completion Queue Entry Size
|
||||
UINT8 Rsvd2;
|
||||
} NVME_CC;
|
||||
|
||||
//
|
||||
// 3.1.6 Offset 1Ch: CSTS - Controller Status
|
||||
//
|
||||
typedef struct {
|
||||
UINT32 Rdy:1; // Ready
|
||||
UINT32 Cfs:1; // Controller Fatal Status
|
||||
UINT32 Shst:2; // Shutdown Status
|
||||
UINT32 Nssro:1; // NVM Subsystem Reset Occurred
|
||||
UINT32 Rsvd1:27;
|
||||
} NVME_CSTS;
|
||||
|
||||
//
|
||||
// 3.1.8 Offset 24h: AQA - Admin Queue Attributes
|
||||
//
|
||||
typedef struct {
|
||||
UINT16 Asqs:12; // Submission Queue Size
|
||||
UINT16 Rsvd1:4;
|
||||
UINT16 Acqs:12; // Completion Queue Size
|
||||
UINT16 Rsvd2:4;
|
||||
} NVME_AQA;
|
||||
|
||||
//
|
||||
// 3.1.9 Offset 28h: ASQ - Admin Submission Queue Base Address
|
||||
//
|
||||
#define NVME_ASQ UINT64
|
||||
|
||||
//
|
||||
// 3.1.10 Offset 30h: ACQ - Admin Completion Queue Base Address
|
||||
//
|
||||
#define NVME_ACQ UINT64
|
||||
|
||||
//
|
||||
// 3.1.11 Offset (1000h + ((2y) * (4 << CAP.DSTRD))): SQyTDBL - Submission Queue y Tail Doorbell
|
||||
//
|
||||
typedef struct {
|
||||
UINT16 Sqt;
|
||||
UINT16 Rsvd1;
|
||||
} NVME_SQTDBL;
|
||||
|
||||
//
|
||||
// 3.1.12 Offset (1000h + ((2y + 1) * (4 << CAP.DSTRD))): CQyHDBL - Completion Queue y Head Doorbell
|
||||
//
|
||||
typedef struct {
|
||||
UINT16 Cqh;
|
||||
UINT16 Rsvd1;
|
||||
} NVME_CQHDBL;
|
||||
|
||||
//
|
||||
// NVM command set structures
|
||||
//
|
||||
// Read Command
|
||||
//
|
||||
typedef struct {
|
||||
//
|
||||
// CDW 10, 11
|
||||
//
|
||||
UINT64 Slba; /* Starting Sector Address */
|
||||
//
|
||||
// CDW 12
|
||||
//
|
||||
UINT16 Nlb; /* Number of Sectors */
|
||||
UINT16 Rsvd1:10;
|
||||
UINT16 Prinfo:4; /* Protection Info Check */
|
||||
UINT16 Fua:1; /* Force Unit Access */
|
||||
UINT16 Lr:1; /* Limited Retry */
|
||||
//
|
||||
// CDW 13
|
||||
//
|
||||
UINT32 Af:4; /* Access Frequency */
|
||||
UINT32 Al:2; /* Access Latency */
|
||||
UINT32 Sr:1; /* Sequential Request */
|
||||
UINT32 In:1; /* Incompressible */
|
||||
UINT32 Rsvd2:24;
|
||||
//
|
||||
// CDW 14
|
||||
//
|
||||
UINT32 Eilbrt; /* Expected Initial Logical Block Reference Tag */
|
||||
//
|
||||
// CDW 15
|
||||
//
|
||||
UINT16 Elbat; /* Expected Logical Block Application Tag */
|
||||
UINT16 Elbatm; /* Expected Logical Block Application Tag Mask */
|
||||
} NVME_READ;
|
||||
|
||||
//
|
||||
// Write Command
|
||||
//
|
||||
typedef struct {
|
||||
//
|
||||
// CDW 10, 11
|
||||
//
|
||||
UINT64 Slba; /* Starting Sector Address */
|
||||
//
|
||||
// CDW 12
|
||||
//
|
||||
UINT16 Nlb; /* Number of Sectors */
|
||||
UINT16 Rsvd1:10;
|
||||
UINT16 Prinfo:4; /* Protection Info Check */
|
||||
UINT16 Fua:1; /* Force Unit Access */
|
||||
UINT16 Lr:1; /* Limited Retry */
|
||||
//
|
||||
// CDW 13
|
||||
//
|
||||
UINT32 Af:4; /* Access Frequency */
|
||||
UINT32 Al:2; /* Access Latency */
|
||||
UINT32 Sr:1; /* Sequential Request */
|
||||
UINT32 In:1; /* Incompressible */
|
||||
UINT32 Rsvd2:24;
|
||||
//
|
||||
// CDW 14
|
||||
//
|
||||
UINT32 Ilbrt; /* Initial Logical Block Reference Tag */
|
||||
//
|
||||
// CDW 15
|
||||
//
|
||||
UINT16 Lbat; /* Logical Block Application Tag */
|
||||
UINT16 Lbatm; /* Logical Block Application Tag Mask */
|
||||
} NVME_WRITE;
|
||||
|
||||
//
|
||||
// Flush
|
||||
//
|
||||
typedef struct {
|
||||
//
|
||||
// CDW 10
|
||||
//
|
||||
UINT32 Flush; /* Flush */
|
||||
} NVME_FLUSH;
|
||||
|
||||
//
|
||||
// Write Uncorrectable command
|
||||
//
|
||||
typedef struct {
|
||||
//
|
||||
// CDW 10, 11
|
||||
//
|
||||
UINT64 Slba; /* Starting LBA */
|
||||
//
|
||||
// CDW 12
|
||||
//
|
||||
UINT32 Nlb:16; /* Number of Logical Blocks */
|
||||
UINT32 Rsvd1:16;
|
||||
} NVME_WRITE_UNCORRECTABLE;
|
||||
|
||||
//
|
||||
// Write Zeroes command
|
||||
//
|
||||
typedef struct {
|
||||
//
|
||||
// CDW 10, 11
|
||||
//
|
||||
UINT64 Slba; /* Starting LBA */
|
||||
//
|
||||
// CDW 12
|
||||
//
|
||||
UINT16 Nlb; /* Number of Logical Blocks */
|
||||
UINT16 Rsvd1:10;
|
||||
UINT16 Prinfo:4; /* Protection Info Check */
|
||||
UINT16 Fua:1; /* Force Unit Access */
|
||||
UINT16 Lr:1; /* Limited Retry */
|
||||
//
|
||||
// CDW 13
|
||||
//
|
||||
UINT32 Rsvd2;
|
||||
//
|
||||
// CDW 14
|
||||
//
|
||||
UINT32 Ilbrt; /* Initial Logical Block Reference Tag */
|
||||
//
|
||||
// CDW 15
|
||||
//
|
||||
UINT16 Lbat; /* Logical Block Application Tag */
|
||||
UINT16 Lbatm; /* Logical Block Application Tag Mask */
|
||||
} NVME_WRITE_ZEROES;
|
||||
|
||||
//
|
||||
// Compare command
|
||||
//
|
||||
typedef struct {
|
||||
//
|
||||
// CDW 10, 11
|
||||
//
|
||||
UINT64 Slba; /* Starting LBA */
|
||||
//
|
||||
// CDW 12
|
||||
//
|
||||
UINT16 Nlb; /* Number of Logical Blocks */
|
||||
UINT16 Rsvd1:10;
|
||||
UINT16 Prinfo:4; /* Protection Info Check */
|
||||
UINT16 Fua:1; /* Force Unit Access */
|
||||
UINT16 Lr:1; /* Limited Retry */
|
||||
//
|
||||
// CDW 13
|
||||
//
|
||||
UINT32 Rsvd2;
|
||||
//
|
||||
// CDW 14
|
||||
//
|
||||
UINT32 Eilbrt; /* Expected Initial Logical Block Reference Tag */
|
||||
//
|
||||
// CDW 15
|
||||
//
|
||||
UINT16 Elbat; /* Expected Logical Block Application Tag */
|
||||
UINT16 Elbatm; /* Expected Logical Block Application Tag Mask */
|
||||
} NVME_COMPARE;
|
||||
|
||||
typedef union {
|
||||
NVME_READ Read;
|
||||
NVME_WRITE Write;
|
||||
NVME_FLUSH Flush;
|
||||
NVME_WRITE_UNCORRECTABLE WriteUncorrectable;
|
||||
NVME_WRITE_ZEROES WriteZeros;
|
||||
NVME_COMPARE Compare;
|
||||
} NVME_CMD;
|
||||
|
||||
typedef struct {
|
||||
UINT16 Mp; /* Maximum Power */
|
||||
UINT8 Rsvd1; /* Reserved as of Nvm Express 1.1 Spec */
|
||||
UINT8 Mps:1; /* Max Power Scale */
|
||||
UINT8 Nops:1; /* Non-Operational State */
|
||||
UINT8 Rsvd2:6; /* Reserved as of Nvm Express 1.1 Spec */
|
||||
UINT32 Enlat; /* Entry Latency */
|
||||
UINT32 Exlat; /* Exit Latency */
|
||||
UINT8 Rrt:5; /* Relative Read Throughput */
|
||||
UINT8 Rsvd3:3; /* Reserved as of Nvm Express 1.1 Spec */
|
||||
UINT8 Rrl:5; /* Relative Read Leatency */
|
||||
UINT8 Rsvd4:3; /* Reserved as of Nvm Express 1.1 Spec */
|
||||
UINT8 Rwt:5; /* Relative Write Throughput */
|
||||
UINT8 Rsvd5:3; /* Reserved as of Nvm Express 1.1 Spec */
|
||||
UINT8 Rwl:5; /* Relative Write Leatency */
|
||||
UINT8 Rsvd6:3; /* Reserved as of Nvm Express 1.1 Spec */
|
||||
UINT8 Rsvd7[16]; /* Reserved as of Nvm Express 1.1 Spec */
|
||||
} NVME_PSDESCRIPTOR;
|
||||
|
||||
//
|
||||
// Identify Controller Data
|
||||
//
|
||||
typedef struct {
|
||||
//
|
||||
// Controller Capabilities and Features 0-255
|
||||
//
|
||||
UINT16 Vid; /* PCI Vendor ID */
|
||||
UINT16 Ssvid; /* PCI sub-system vendor ID */
|
||||
UINT8 Sn[20]; /* Produce serial number */
|
||||
|
||||
UINT8 Mn[40]; /* Proeduct model number */
|
||||
UINT8 Fr[8]; /* Firmware Revision */
|
||||
UINT8 Rab; /* Recommended Arbitration Burst */
|
||||
UINT8 Ieee_oiu[3]; /* Organization Unique Identifier */
|
||||
UINT8 Cmic; /* Multi-interface Capabilities */
|
||||
UINT8 Mdts; /* Maximum Data Transfer Size */
|
||||
UINT8 Cntlid[2]; /* Controller ID */
|
||||
UINT8 Rsvd1[176]; /* Reserved as of Nvm Express 1.1 Spec */
|
||||
//
|
||||
// Admin Command Set Attributes
|
||||
//
|
||||
UINT16 Oacs; /* Optional Admin Command Support */
|
||||
UINT8 Acl; /* Abort Command Limit */
|
||||
UINT8 Aerl; /* Async Event Request Limit */
|
||||
UINT8 Frmw; /* Firmware updates */
|
||||
UINT8 Lpa; /* Log Page Attributes */
|
||||
UINT8 Elpe; /* Error Log Page Entries */
|
||||
UINT8 Npss; /* Number of Power States Support */
|
||||
UINT8 Avscc; /* Admin Vendor Specific Command Configuration */
|
||||
UINT8 Apsta; /* Autonomous Power State Transition Attributes */
|
||||
UINT8 Rsvd2[246]; /* Reserved as of Nvm Express 1.1 Spec */
|
||||
//
|
||||
// NVM Command Set Attributes
|
||||
//
|
||||
UINT8 Sqes; /* Submission Queue Entry Size */
|
||||
UINT8 Cqes; /* Completion Queue Entry Size */
|
||||
UINT16 Rsvd3; /* Reserved as of Nvm Express 1.1 Spec */
|
||||
UINT32 Nn; /* Number of Namespaces */
|
||||
UINT16 Oncs; /* Optional NVM Command Support */
|
||||
UINT16 Fuses; /* Fused Operation Support */
|
||||
UINT8 Fna; /* Format NVM Attributes */
|
||||
UINT8 Vwc; /* Volatile Write Cache */
|
||||
UINT16 Awun; /* Atomic Write Unit Normal */
|
||||
UINT16 Awupf; /* Atomic Write Unit Power Fail */
|
||||
UINT8 Nvscc; /* NVM Vendor Specific Command Configuration */
|
||||
UINT8 Rsvd4; /* Reserved as of Nvm Express 1.1 Spec */
|
||||
UINT16 Acwu; /* Atomic Compare & Write Unit */
|
||||
UINT16 Rsvd5; /* Reserved as of Nvm Express 1.1 Spec */
|
||||
UINT32 Sgls; /* SGL Support */
|
||||
UINT8 Rsvd6[164]; /* Reserved as of Nvm Express 1.1 Spec */
|
||||
//
|
||||
// I/O Command set Attributes
|
||||
//
|
||||
UINT8 Rsvd7[1344]; /* Reserved as of Nvm Express 1.1 Spec */
|
||||
//
|
||||
// Power State Descriptors
|
||||
//
|
||||
NVME_PSDESCRIPTOR PsDescriptor[32];
|
||||
|
||||
UINT8 VendorData[1024]; /* Vendor specific Data */
|
||||
} NVME_ADMIN_CONTROLLER_DATA;
|
||||
|
||||
typedef struct {
|
||||
UINT16 Security : 1; /* supports security send/receive commands */
|
||||
UINT16 Format : 1; /* supports format nvm command */
|
||||
UINT16 Firmware : 1; /* supports firmware activate/download commands */
|
||||
UINT16 Oacs_rsvd : 13;
|
||||
} OACS; // optional admin command support: NVME_ADMIN_CONTROLLER_DATA.Oacs
|
||||
|
||||
typedef struct {
|
||||
UINT16 Ms; /* Metadata Size */
|
||||
UINT8 Lbads; /* LBA Data Size */
|
||||
UINT8 Rp:2; /* Relative Performance */
|
||||
#define LBAF_RP_BEST 00b
|
||||
#define LBAF_RP_BETTER 01b
|
||||
#define LBAF_RP_GOOD 10b
|
||||
#define LBAF_RP_DEGRADED 11b
|
||||
UINT8 Rsvd1:6; /* Reserved as of Nvm Express 1.1 Spec */
|
||||
} NVME_LBAFORMAT;
|
||||
|
||||
//
|
||||
// Identify Namespace Data
|
||||
//
|
||||
typedef struct {
|
||||
//
|
||||
// NVM Command Set Specific
|
||||
//
|
||||
UINT64 Nsze; /* Namespace Size (total number of blocks in formatted namespace) */
|
||||
UINT64 Ncap; /* Namespace Capacity (max number of logical blocks) */
|
||||
UINT64 Nuse; /* Namespace Utilization */
|
||||
UINT8 Nsfeat; /* Namespace Features */
|
||||
UINT8 Nlbaf; /* Number of LBA Formats */
|
||||
UINT8 Flbas; /* Formatted LBA Size */
|
||||
UINT8 Mc; /* Metadata Capabilities */
|
||||
UINT8 Dpc; /* End-to-end Data Protection capabilities */
|
||||
UINT8 Dps; /* End-to-end Data Protection Type Settings */
|
||||
UINT8 Nmic; /* Namespace Multi-path I/O and Namespace Sharing Capabilities */
|
||||
UINT8 Rescap; /* Reservation Capabilities */
|
||||
UINT8 Rsvd1[88]; /* Reserved as of Nvm Express 1.1 Spec */
|
||||
UINT64 Eui64; /* IEEE Extended Unique Identifier */
|
||||
//
|
||||
// LBA Format
|
||||
//
|
||||
NVME_LBAFORMAT LbaFormat[16];
|
||||
|
||||
UINT8 Rsvd2[192]; /* Reserved as of Nvm Express 1.1 Spec */
|
||||
UINT8 VendorData[3712]; /* Vendor specific Data */
|
||||
} NVME_ADMIN_NAMESPACE_DATA;
|
||||
|
||||
//
|
||||
// NvmExpress Admin Identify Cmd
|
||||
//
|
||||
typedef struct {
|
||||
//
|
||||
// CDW 10
|
||||
//
|
||||
UINT32 Cns:2;
|
||||
UINT32 Rsvd1:30;
|
||||
} NVME_ADMIN_IDENTIFY;
|
||||
|
||||
//
|
||||
// NvmExpress Admin Create I/O Completion Queue
|
||||
//
|
||||
typedef struct {
|
||||
//
|
||||
// CDW 10
|
||||
//
|
||||
UINT32 Qid:16; /* Queue Identifier */
|
||||
UINT32 Qsize:16; /* Queue Size */
|
||||
|
||||
//
|
||||
// CDW 11
|
||||
//
|
||||
UINT32 Pc:1; /* Physically Contiguous */
|
||||
UINT32 Ien:1; /* Interrupts Enabled */
|
||||
UINT32 Rsvd1:14; /* reserved as of Nvm Express 1.1 Spec */
|
||||
UINT32 Iv:16; /* Interrupt Vector */
|
||||
} NVME_ADMIN_CRIOCQ;
|
||||
|
||||
//
|
||||
// NvmExpress Admin Create I/O Submission Queue
|
||||
//
|
||||
typedef struct {
|
||||
//
|
||||
// CDW 10
|
||||
//
|
||||
UINT32 Qid:16; /* Queue Identifier */
|
||||
UINT32 Qsize:16; /* Queue Size */
|
||||
|
||||
//
|
||||
// CDW 11
|
||||
//
|
||||
UINT32 Pc:1; /* Physically Contiguous */
|
||||
UINT32 Qprio:2; /* Queue Priority */
|
||||
UINT32 Rsvd1:13; /* Reserved as of Nvm Express 1.1 Spec */
|
||||
UINT32 Cqid:16; /* Completion Queue ID */
|
||||
} NVME_ADMIN_CRIOSQ;
|
||||
|
||||
//
|
||||
// NvmExpress Admin Delete I/O Completion Queue
|
||||
//
|
||||
typedef struct {
|
||||
//
|
||||
// CDW 10
|
||||
//
|
||||
UINT16 Qid;
|
||||
UINT16 Rsvd1;
|
||||
} NVME_ADMIN_DEIOCQ;
|
||||
|
||||
//
|
||||
// NvmExpress Admin Delete I/O Submission Queue
|
||||
//
|
||||
typedef struct {
|
||||
//
|
||||
// CDW 10
|
||||
//
|
||||
UINT16 Qid;
|
||||
UINT16 Rsvd1;
|
||||
} NVME_ADMIN_DEIOSQ;
|
||||
|
||||
//
|
||||
// NvmExpress Admin Security Send
|
||||
//
|
||||
typedef struct {
|
||||
//
|
||||
// CDW 10
|
||||
//
|
||||
UINT32 Resv:8; /* Reserve */
|
||||
UINT32 Spsp:16; /* SP Specific */
|
||||
UINT32 Secp:8; /* Security Protocol */
|
||||
|
||||
//
|
||||
// CDW 11
|
||||
//
|
||||
UINT32 Tl; /* Transfer Length */
|
||||
} NVME_ADMIN_SECSEND;
|
||||
|
||||
//
|
||||
// NvmExpress Admin Abort Command
|
||||
//
|
||||
typedef struct {
|
||||
//
|
||||
// CDW 10
|
||||
//
|
||||
UINT32 Sqid:16; /* Submission Queue identifier */
|
||||
UINT32 Cid:16; /* Command Identifier */
|
||||
} NVME_ADMIN_ABORT;
|
||||
|
||||
//
|
||||
// NvmExpress Admin Firmware Activate Command
|
||||
//
|
||||
typedef struct {
|
||||
//
|
||||
// CDW 10
|
||||
//
|
||||
UINT32 Fs:3; /* Submission Queue identifier */
|
||||
UINT32 Aa:2; /* Command Identifier */
|
||||
UINT32 Rsvd1:27;
|
||||
} NVME_ADMIN_FIRMWARE_ACTIVATE;
|
||||
|
||||
//
|
||||
// NvmExpress Admin Firmware Image Download Command
|
||||
//
|
||||
typedef struct {
|
||||
//
|
||||
// CDW 10
|
||||
//
|
||||
UINT32 Numd; /* Number of Dwords */
|
||||
//
|
||||
// CDW 11
|
||||
//
|
||||
UINT32 Ofst; /* Offset */
|
||||
} NVME_ADMIN_FIRMWARE_IMAGE_DOWNLOAD;
|
||||
|
||||
//
|
||||
// NvmExpress Admin Get Features Command
|
||||
//
|
||||
typedef struct {
|
||||
//
|
||||
// CDW 10
|
||||
//
|
||||
UINT32 Fid:8; /* Feature Identifier */
|
||||
UINT32 Sel:3; /* Select */
|
||||
UINT32 Rsvd1:21;
|
||||
} NVME_ADMIN_GET_FEATURES;
|
||||
|
||||
//
|
||||
// NvmExpress Admin Get Log Page Command
|
||||
//
|
||||
typedef struct {
|
||||
//
|
||||
// CDW 10
|
||||
//
|
||||
UINT32 Lid:8; /* Log Page Identifier */
|
||||
#define LID_ERROR_INFO
|
||||
#define LID_SMART_INFO
|
||||
#define LID_FW_SLOT_INFO
|
||||
UINT32 Rsvd1:8;
|
||||
UINT32 Numd:12; /* Number of Dwords */
|
||||
UINT32 Rsvd2:4; /* Reserved as of Nvm Express 1.1 Spec */
|
||||
} NVME_ADMIN_GET_LOG_PAGE;
|
||||
|
||||
//
|
||||
// NvmExpress Admin Set Features Command
|
||||
//
|
||||
typedef struct {
|
||||
//
|
||||
// CDW 10
|
||||
//
|
||||
UINT32 Fid:8; /* Feature Identifier */
|
||||
UINT32 Rsvd1:23;
|
||||
UINT32 Sv:1; /* Save */
|
||||
} NVME_ADMIN_SET_FEATURES;
|
||||
|
||||
//
|
||||
// NvmExpress Admin Format NVM Command
|
||||
//
|
||||
typedef struct {
|
||||
//
|
||||
// CDW 10
|
||||
//
|
||||
UINT32 Lbaf:4; /* LBA Format */
|
||||
UINT32 Ms:1; /* Metadata Settings */
|
||||
UINT32 Pi:3; /* Protection Information */
|
||||
UINT32 Pil:1; /* Protection Information Location */
|
||||
UINT32 Ses:3; /* Secure Erase Settings */
|
||||
UINT32 Rsvd1:20;
|
||||
} NVME_ADMIN_FORMAT_NVM;
|
||||
|
||||
//
|
||||
// NvmExpress Admin Security Receive Command
|
||||
//
|
||||
typedef struct {
|
||||
//
|
||||
// CDW 10
|
||||
//
|
||||
UINT32 Rsvd1:8;
|
||||
UINT32 Spsp:16; /* SP Specific */
|
||||
UINT32 Secp:8; /* Security Protocol */
|
||||
//
|
||||
// CDW 11
|
||||
//
|
||||
UINT32 Al; /* Allocation Length */
|
||||
} NVME_ADMIN_SECURITY_RECEIVE;
|
||||
|
||||
//
|
||||
// NvmExpress Admin Security Send Command
|
||||
//
|
||||
typedef struct {
|
||||
//
|
||||
// CDW 10
|
||||
//
|
||||
UINT32 Rsvd1:8;
|
||||
UINT32 Spsp:16; /* SP Specific */
|
||||
UINT32 Secp:8; /* Security Protocol */
|
||||
//
|
||||
// CDW 11
|
||||
//
|
||||
UINT32 Tl; /* Transfer Length */
|
||||
} NVME_ADMIN_SECURITY_SEND;
|
||||
|
||||
typedef union {
|
||||
NVME_ADMIN_IDENTIFY Identify;
|
||||
NVME_ADMIN_CRIOCQ CrIoCq;
|
||||
NVME_ADMIN_CRIOSQ CrIoSq;
|
||||
NVME_ADMIN_DEIOCQ DeIoCq;
|
||||
NVME_ADMIN_DEIOSQ DeIoSq;
|
||||
NVME_ADMIN_ABORT Abort;
|
||||
NVME_ADMIN_FIRMWARE_ACTIVATE Activate;
|
||||
NVME_ADMIN_FIRMWARE_IMAGE_DOWNLOAD FirmwareImageDownload;
|
||||
NVME_ADMIN_GET_FEATURES GetFeatures;
|
||||
NVME_ADMIN_GET_LOG_PAGE GetLogPage;
|
||||
NVME_ADMIN_SET_FEATURES SetFeatures;
|
||||
NVME_ADMIN_FORMAT_NVM FormatNvm;
|
||||
NVME_ADMIN_SECURITY_RECEIVE SecurityReceive;
|
||||
NVME_ADMIN_SECURITY_SEND SecuritySend;
|
||||
} NVME_ADMIN_CMD;
|
||||
|
||||
typedef struct {
|
||||
UINT32 Cdw10;
|
||||
UINT32 Cdw11;
|
||||
UINT32 Cdw12;
|
||||
UINT32 Cdw13;
|
||||
UINT32 Cdw14;
|
||||
UINT32 Cdw15;
|
||||
} NVME_RAW;
|
||||
|
||||
typedef union {
|
||||
NVME_ADMIN_CMD Admin; // Union of Admin commands
|
||||
NVME_CMD Nvm; // Union of Nvm commands
|
||||
NVME_RAW Raw;
|
||||
} NVME_PAYLOAD;
|
||||
|
||||
//
|
||||
// Submission Queue
|
||||
//
|
||||
typedef struct {
|
||||
//
|
||||
// CDW 0, Common to all comnmands
|
||||
//
|
||||
UINT8 Opc; // Opcode
|
||||
UINT8 Fuse:2; // Fused Operation
|
||||
UINT8 Rsvd1:5;
|
||||
UINT8 Psdt:1; // PRP or SGL for Data Transfer
|
||||
UINT16 Cid; // Command Identifier
|
||||
|
||||
//
|
||||
// CDW 1
|
||||
//
|
||||
UINT32 Nsid; // Namespace Identifier
|
||||
|
||||
//
|
||||
// CDW 2,3
|
||||
//
|
||||
UINT64 Rsvd2;
|
||||
|
||||
//
|
||||
// CDW 4,5
|
||||
//
|
||||
UINT64 Mptr; // Metadata Pointer
|
||||
|
||||
//
|
||||
// CDW 6-9
|
||||
//
|
||||
UINT64 Prp[2]; // First and second PRP entries
|
||||
|
||||
NVME_PAYLOAD Payload;
|
||||
|
||||
} NVME_SQ;
|
||||
|
||||
//
|
||||
// Completion Queue
|
||||
//
|
||||
typedef struct {
|
||||
//
|
||||
// CDW 0
|
||||
//
|
||||
UINT32 Dword0;
|
||||
//
|
||||
// CDW 1
|
||||
//
|
||||
UINT32 Rsvd1;
|
||||
//
|
||||
// CDW 2
|
||||
//
|
||||
UINT16 Sqhd; // Submission Queue Head Pointer
|
||||
UINT16 Sqid; // Submission Queue Identifier
|
||||
//
|
||||
// CDW 3
|
||||
//
|
||||
UINT16 Cid; // Command Identifier
|
||||
UINT16 Pt:1; // Phase Tag
|
||||
UINT16 Sc:8; // Status Code
|
||||
UINT16 Sct:3; // Status Code Type
|
||||
UINT16 Rsvd2:2;
|
||||
UINT16 Mo:1; // More
|
||||
UINT16 Dnr:1; // Retry
|
||||
} NVME_CQ;
|
||||
|
||||
//
|
||||
// Nvm Express Admin cmd opcodes
|
||||
//
|
||||
#define NVME_ADMIN_DELIOSQ_OPC 0
|
||||
#define NVME_ADMIN_CRIOSQ_OPC 1
|
||||
#define NVME_ADMIN_DELIOCQ_OPC 4
|
||||
#define NVME_ADMIN_CRIOCQ_OPC 5
|
||||
#define NVME_ADMIN_IDENTIFY_OPC 6
|
||||
#define NVME_ADMIN_SECURITY_SEND_OPC 0x81
|
||||
#define NVME_ADMIN_SECURITY_RECV_OPC 0x82
|
||||
|
||||
#define NVME_IO_FLUSH_OPC 0
|
||||
#define NVME_IO_WRITE_OPC 1
|
||||
#define NVME_IO_READ_OPC 2
|
||||
|
||||
//
|
||||
// Offset from the beginning of private Data queue Buffer
|
||||
//
|
||||
#define NVME_ASQ_BUF_OFFSET EFI_PAGE_SIZE
|
||||
|
||||
#pragma pack()
|
||||
|
||||
#endif
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,299 @@
|
|||
/** @file
|
||||
Opal password smm driver which is used to support Opal security feature at s3 path.
|
||||
|
||||
Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>
|
||||
This program and the accompanying materials
|
||||
are licensed and made available under the terms and conditions of the BSD License
|
||||
which accompanies this distribution. The full text of the license may be found at
|
||||
http://opensource.org/licenses/bsd-license.php
|
||||
|
||||
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
|
||||
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
|
||||
|
||||
**/
|
||||
|
||||
#ifndef _OPAL_PASSWORD_SMM_H_
|
||||
#define _OPAL_PASSWORD_SMM_H_
|
||||
|
||||
#include <PiSmm.h>
|
||||
#include <IndustryStandard/Atapi.h>
|
||||
|
||||
#include <Protocol/SmmSwDispatch2.h>
|
||||
#include <Protocol/SmmSxDispatch2.h>
|
||||
#include <Protocol/AtaPassThru.h>
|
||||
#include <Protocol/PciIo.h>
|
||||
#include <Protocol/SmmReadyToLock.h>
|
||||
#include <Protocol/SmmVariable.h>
|
||||
#include <Protocol/VariableLock.h>
|
||||
#include <Protocol/StorageSecurityCommand.h>
|
||||
|
||||
#include <Library/OpalPasswordSupportLib.h>
|
||||
#include <Library/DebugLib.h>
|
||||
#include <Library/PcdLib.h>
|
||||
#include <Library/IoLib.h>
|
||||
#include <Library/TimerLib.h>
|
||||
#include <Library/PciLib.h>
|
||||
#include <Library/BaseLib.h>
|
||||
#include <Library/BaseMemoryLib.h>
|
||||
#include <Library/SmmServicesTableLib.h>
|
||||
#include <Library/MemoryAllocationLib.h>
|
||||
#include <Library/UefiDriverEntryPoint.h>
|
||||
#include <Library/UefiBootServicesTableLib.h>
|
||||
#include <Library/UefiRuntimeServicesTableLib.h>
|
||||
#include <Library/UefiLib.h>
|
||||
#include <Library/S3BootScriptLib.h>
|
||||
#include <Library/DevicePathLib.h>
|
||||
#include <Library/SmmMemLib.h>
|
||||
|
||||
#include <Library/DxeServicesTableLib.h>
|
||||
|
||||
#include <IndustryStandard/Pci22.h>
|
||||
|
||||
#include <Guid/OpalPasswordExtraInfoVariable.h>
|
||||
|
||||
#include "OpalAhciMode.h"
|
||||
#include "OpalIdeMode.h"
|
||||
#include "OpalNvmeMode.h"
|
||||
|
||||
//
|
||||
// Time out Value for ATA pass through protocol
|
||||
//
|
||||
#define ATA_TIMEOUT EFI_TIMER_PERIOD_SECONDS (3)
|
||||
|
||||
//
|
||||
// The payload Length of HDD related ATA commands
|
||||
//
|
||||
#define HDD_PAYLOAD 512
|
||||
//
|
||||
// According to ATA spec, the max Length of hdd password is 32 bytes
|
||||
//
|
||||
#define OPAL_PASSWORD_MAX_LENGTH 32
|
||||
|
||||
extern VOID *mBuffer;
|
||||
|
||||
#pragma pack(1)
|
||||
|
||||
typedef struct {
|
||||
UINT32 Address;
|
||||
S3_BOOT_SCRIPT_LIB_WIDTH Width;
|
||||
} OPAL_HC_PCI_REGISTER_SAVE;
|
||||
|
||||
|
||||
typedef struct {
|
||||
UINT32 SegNum;
|
||||
UINT32 BusNum;
|
||||
UINT32 DevNum;
|
||||
UINT32 FuncNum;
|
||||
} PCI_DEVICE;
|
||||
|
||||
/**
|
||||
* Opal I/O Type utilized by the Trusted IO callback
|
||||
*
|
||||
* The type indicates if the I/O is a send or receive
|
||||
*/
|
||||
typedef enum {
|
||||
//
|
||||
// I/O is a TCG Trusted Send command
|
||||
//
|
||||
OpalSend,
|
||||
|
||||
//
|
||||
// I/O is a TCG Trusted Receive command
|
||||
//
|
||||
OpalRecv
|
||||
} OPAL_IO_TYPE;
|
||||
|
||||
|
||||
#define OPAL_SMM_DEVICE_SIGNATURE SIGNATURE_32 ('o', 's', 'd', 's')
|
||||
|
||||
typedef struct {
|
||||
UINTN Signature;
|
||||
LIST_ENTRY Link;
|
||||
|
||||
EFI_STORAGE_SECURITY_COMMAND_PROTOCOL Sscp;
|
||||
|
||||
UINT32 SegNum;
|
||||
UINT32 BusNum;
|
||||
UINT32 DevNum;
|
||||
UINT32 FuncNum;
|
||||
|
||||
UINT8 DeviceType;
|
||||
|
||||
UINT32 SataPort;
|
||||
UINT32 SataPortMultiplierPort;
|
||||
|
||||
UINT32 NvmeNamespaceId;
|
||||
|
||||
UINT8 Password[32];
|
||||
UINT8 PasswordLength;
|
||||
|
||||
UINT32 Length;
|
||||
PCI_DEVICE *PciBridgeNode;
|
||||
|
||||
UINT16 OpalBaseComId;
|
||||
} OPAL_SMM_DEVICE;
|
||||
|
||||
#define OPAL_SMM_DEVICE_FROM_THIS(a) CR (a, OPAL_SMM_DEVICE, Sscp, OPAL_SMM_DEVICE_SIGNATURE)
|
||||
|
||||
#pragma pack()
|
||||
|
||||
/**
|
||||
Send a security protocol command to a device that receives data and/or the result
|
||||
of one or more commands sent by SendData.
|
||||
|
||||
The ReceiveData function sends a security protocol command to the given MediaId.
|
||||
The security protocol command sent is defined by SecurityProtocolId and contains
|
||||
the security protocol specific data SecurityProtocolSpecificData. The function
|
||||
returns the data from the security protocol command in PayloadBuffer.
|
||||
|
||||
For devices supporting the SCSI command set, the security protocol command is sent
|
||||
using the SECURITY PROTOCOL IN command defined in SPC-4.
|
||||
|
||||
For devices supporting the ATA command set, the security protocol command is sent
|
||||
using one of the TRUSTED RECEIVE commands defined in ATA8-ACS if PayloadBufferSize
|
||||
is non-zero.
|
||||
|
||||
If the PayloadBufferSize is zero, the security protocol command is sent using the
|
||||
Trusted Non-Data command defined in ATA8-ACS.
|
||||
|
||||
If PayloadBufferSize is too small to store the available data from the security
|
||||
protocol command, the function shall copy PayloadBufferSize bytes into the
|
||||
PayloadBuffer and return EFI_WARN_BUFFER_TOO_SMALL.
|
||||
|
||||
If PayloadBuffer or PayloadTransferSize is NULL and PayloadBufferSize is non-zero,
|
||||
the function shall return EFI_INVALID_PARAMETER.
|
||||
|
||||
If the given MediaId does not support security protocol commands, the function shall
|
||||
return EFI_UNSUPPORTED. If there is no media in the device, the function returns
|
||||
EFI_NO_MEDIA. If the MediaId is not the ID for the current media in the device,
|
||||
the function returns EFI_MEDIA_CHANGED.
|
||||
|
||||
If the security protocol fails to complete within the Timeout period, the function
|
||||
shall return EFI_TIMEOUT.
|
||||
|
||||
If the security protocol command completes without an error, the function shall
|
||||
return EFI_SUCCESS. If the security protocol command completes with an error, the
|
||||
function shall return EFI_DEVICE_ERROR.
|
||||
|
||||
@param This Indicates a pointer to the calling context.
|
||||
@param MediaId ID of the medium to receive data from.
|
||||
@param Timeout The timeout, in 100ns units, to use for the execution
|
||||
of the security protocol command. A Timeout value of 0
|
||||
means that this function will wait indefinitely for the
|
||||
security protocol command to execute. If Timeout is greater
|
||||
than zero, then this function will return EFI_TIMEOUT
|
||||
if the time required to execute the receive data command
|
||||
is greater than Timeout.
|
||||
@param SecurityProtocolId The value of the "Security Protocol" parameter of
|
||||
the security protocol command to be sent.
|
||||
@param SecurityProtocolSpecificData The value of the "Security Protocol Specific" parameter
|
||||
of the security protocol command to be sent.
|
||||
@param PayloadBufferSize Size in bytes of the payload data buffer.
|
||||
@param PayloadBuffer A pointer to a destination buffer to store the security
|
||||
protocol command specific payload data for the security
|
||||
protocol command. The caller is responsible for having
|
||||
either implicit or explicit ownership of the buffer.
|
||||
@param PayloadTransferSize A pointer to a buffer to store the size in bytes of the
|
||||
data written to the payload data buffer.
|
||||
|
||||
@retval EFI_SUCCESS The security protocol command completed successfully.
|
||||
@retval EFI_WARN_BUFFER_TOO_SMALL The PayloadBufferSize was too small to store the available
|
||||
data from the device. The PayloadBuffer contains the truncated data.
|
||||
@retval EFI_UNSUPPORTED The given MediaId does not support security protocol commands.
|
||||
@retval EFI_DEVICE_ERROR The security protocol command completed with an error.
|
||||
@retval EFI_NO_MEDIA There is no media in the device.
|
||||
@retval EFI_MEDIA_CHANGED The MediaId is not for the current media.
|
||||
@retval EFI_INVALID_PARAMETER The PayloadBuffer or PayloadTransferSize is NULL and
|
||||
PayloadBufferSize is non-zero.
|
||||
@retval EFI_TIMEOUT A timeout occurred while waiting for the security
|
||||
protocol command to execute.
|
||||
|
||||
**/
|
||||
EFI_STATUS
|
||||
EFIAPI
|
||||
SecurityReceiveData (
|
||||
IN EFI_STORAGE_SECURITY_COMMAND_PROTOCOL *This,
|
||||
IN UINT32 MediaId,
|
||||
IN UINT64 Timeout,
|
||||
IN UINT8 SecurityProtocolId,
|
||||
IN UINT16 SecurityProtocolSpecificData,
|
||||
IN UINTN PayloadBufferSize,
|
||||
OUT VOID *PayloadBuffer,
|
||||
OUT UINTN *PayloadTransferSize
|
||||
);
|
||||
|
||||
/**
|
||||
Send a security protocol command to a device.
|
||||
|
||||
The SendData function sends a security protocol command containing the payload
|
||||
PayloadBuffer to the given MediaId. The security protocol command sent is
|
||||
defined by SecurityProtocolId and contains the security protocol specific data
|
||||
SecurityProtocolSpecificData. If the underlying protocol command requires a
|
||||
specific padding for the command payload, the SendData function shall add padding
|
||||
bytes to the command payload to satisfy the padding requirements.
|
||||
|
||||
For devices supporting the SCSI command set, the security protocol command is sent
|
||||
using the SECURITY PROTOCOL OUT command defined in SPC-4.
|
||||
|
||||
For devices supporting the ATA command set, the security protocol command is sent
|
||||
using one of the TRUSTED SEND commands defined in ATA8-ACS if PayloadBufferSize
|
||||
is non-zero. If the PayloadBufferSize is zero, the security protocol command is
|
||||
sent using the Trusted Non-Data command defined in ATA8-ACS.
|
||||
|
||||
If PayloadBuffer is NULL and PayloadBufferSize is non-zero, the function shall
|
||||
return EFI_INVALID_PARAMETER.
|
||||
|
||||
If the given MediaId does not support security protocol commands, the function
|
||||
shall return EFI_UNSUPPORTED. If there is no media in the device, the function
|
||||
returns EFI_NO_MEDIA. If the MediaId is not the ID for the current media in the
|
||||
device, the function returns EFI_MEDIA_CHANGED.
|
||||
|
||||
If the security protocol fails to complete within the Timeout period, the function
|
||||
shall return EFI_TIMEOUT.
|
||||
|
||||
If the security protocol command completes without an error, the function shall return
|
||||
EFI_SUCCESS. If the security protocol command completes with an error, the function
|
||||
shall return EFI_DEVICE_ERROR.
|
||||
|
||||
@param This Indicates a pointer to the calling context.
|
||||
@param MediaId ID of the medium to receive data from.
|
||||
@param Timeout The timeout, in 100ns units, to use for the execution
|
||||
of the security protocol command. A Timeout value of 0
|
||||
means that this function will wait indefinitely for the
|
||||
security protocol command to execute. If Timeout is greater
|
||||
than zero, then this function will return EFI_TIMEOUT
|
||||
if the time required to execute the receive data command
|
||||
is greater than Timeout.
|
||||
@param SecurityProtocolId The value of the "Security Protocol" parameter of
|
||||
the security protocol command to be sent.
|
||||
@param SecurityProtocolSpecificData The value of the "Security Protocol Specific" parameter
|
||||
of the security protocol command to be sent.
|
||||
@param PayloadBufferSize Size in bytes of the payload data buffer.
|
||||
@param PayloadBuffer A pointer to a destination buffer to store the security
|
||||
protocol command specific payload data for the security
|
||||
protocol command.
|
||||
|
||||
@retval EFI_SUCCESS The security protocol command completed successfully.
|
||||
@retval EFI_UNSUPPORTED The given MediaId does not support security protocol commands.
|
||||
@retval EFI_DEVICE_ERROR The security protocol command completed with an error.
|
||||
@retval EFI_NO_MEDIA There is no media in the device.
|
||||
@retval EFI_MEDIA_CHANGED The MediaId is not for the current media.
|
||||
@retval EFI_INVALID_PARAMETER The PayloadBuffer is NULL and PayloadBufferSize is non-zero.
|
||||
@retval EFI_TIMEOUT A timeout occurred while waiting for the security
|
||||
protocol command to execute.
|
||||
|
||||
**/
|
||||
EFI_STATUS
|
||||
EFIAPI
|
||||
SecuritySendData (
|
||||
IN EFI_STORAGE_SECURITY_COMMAND_PROTOCOL *This,
|
||||
IN UINT32 MediaId,
|
||||
IN UINT64 Timeout,
|
||||
IN UINT8 SecurityProtocolId,
|
||||
IN UINT16 SecurityProtocolSpecificData,
|
||||
IN UINTN PayloadBufferSize,
|
||||
IN VOID *PayloadBuffer
|
||||
);
|
||||
|
||||
#endif // _OPAL_PASSWORD_SMM_H_
|
||||
|
||||
|
|
@ -0,0 +1,80 @@
|
|||
## @file
|
||||
# This is a Opal Password Smm driver.
|
||||
#
|
||||
# Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>
|
||||
# This program and the accompanying materials
|
||||
# are licensed and made available under the terms and conditions of the BSD License
|
||||
# which accompanies this distribution. The full text of the license may be found at
|
||||
# http://opensource.org/licenses/bsd-license.php
|
||||
# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
|
||||
# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
|
||||
#
|
||||
##
|
||||
[Defines]
|
||||
INF_VERSION = 0x00010005
|
||||
BASE_NAME = OpalPasswordSmm
|
||||
FILE_GUID = 7D24A234-A8C2-4718-BF60-A2EF070F414E
|
||||
MODULE_TYPE = DXE_SMM_DRIVER
|
||||
VERSION_STRING = 1.0
|
||||
PI_SPECIFICATION_VERSION = 0x0001000A
|
||||
ENTRY_POINT = OpalPasswordSmmInit
|
||||
|
||||
#
|
||||
# The following information is for reference only and not required by the build tools.
|
||||
#
|
||||
# VALID_ARCHITECTURES = IA32 X64 IPF EBC
|
||||
#
|
||||
|
||||
[Sources]
|
||||
OpalPasswordSmm.c
|
||||
OpalPasswordSmm.h
|
||||
OpalAhciMode.c
|
||||
OpalAhciMode.h
|
||||
OpalIdeMode.c
|
||||
OpalIdeMode.h
|
||||
OpalNvmeMode.c
|
||||
OpalNvmeMode.h
|
||||
OpalNvmeReg.h
|
||||
|
||||
[Packages]
|
||||
MdePkg/MdePkg.dec
|
||||
SecurityPkg/SecurityPkg.dec
|
||||
MdeModulePkg/MdeModulePkg.dec
|
||||
|
||||
[LibraryClasses]
|
||||
UefiBootServicesTableLib
|
||||
UefiDriverEntryPoint
|
||||
UefiRuntimeServicesTableLib
|
||||
DebugLib
|
||||
IoLib
|
||||
PciLib
|
||||
BaseLib
|
||||
BaseMemoryLib
|
||||
SmmServicesTableLib
|
||||
MemoryAllocationLib
|
||||
UefiLib
|
||||
TimerLib
|
||||
S3BootScriptLib
|
||||
DxeServicesTableLib
|
||||
DevicePathLib
|
||||
OpalPasswordSupportLib
|
||||
SmmMemLib
|
||||
|
||||
[Guids]
|
||||
gOpalExtraInfoVariableGuid ## CONSUMES ## GUID
|
||||
|
||||
[Protocols]
|
||||
gEfiSmmSwDispatch2ProtocolGuid ## CONSUMES
|
||||
gEfiAtaPassThruProtocolGuid ## CONSUMES
|
||||
gEfiPciIoProtocolGuid ## CONSUMES
|
||||
gEfiSmmSxDispatch2ProtocolGuid ## CONSUMES
|
||||
gEfiSmmVariableProtocolGuid ## CONSUMES
|
||||
gEfiStorageSecurityCommandProtocolGuid ## CONSUMES
|
||||
|
||||
[BuildOptions]
|
||||
MSFT:*_*_*_CC_FLAGS = /Od /GL-
|
||||
|
||||
[Depex]
|
||||
gEfiSmmSwDispatch2ProtocolGuid AND
|
||||
gEfiSmmSxDispatch2ProtocolGuid AND
|
||||
gEfiSmmVariableProtocolGuid
|
||||
Loading…
Reference in New Issue