diff --git a/OvmfPkg/PlatformPei/Platform.c b/OvmfPkg/PlatformPei/Platform.c index d395bc191a..6ea9ae3199 100644 --- a/OvmfPkg/PlatformPei/Platform.c +++ b/OvmfPkg/PlatformPei/Platform.c @@ -188,29 +188,25 @@ MemMapInitialization ( 0x4000 ); - // - // Add PCI MMIO space available to PCI resource allocations - // - if (TopOfMemory < BASE_2GB) { - AddIoMemoryBaseSizeHob (BASE_2GB, 0xFC000000 - BASE_2GB); - } else { - AddIoMemoryBaseSizeHob (TopOfMemory, 0xFC000000 - TopOfMemory); - } - - // - // Local APIC range - // - AddIoMemoryBaseSizeHob (0xFEC80000, SIZE_512KB); - - // - // I/O APIC range - // - AddIoMemoryBaseSizeHob (0xFEC00000, SIZE_512KB); - // // Video memory + Legacy BIOS region // AddIoMemoryRangeHob (0x0A0000, BASE_1MB); + + // + // address purpose size + // ------------ -------- ------------------------- + // max(top, 2g) PCI MMIO 0xFEC00000 - max(top, 2g) + // 0xFEC00000 IO-APIC 4 KB + // 0xFEC01000 gap 1020 KB + // 0xFED00000 HPET 1 KB + // 0xFED00400 gap 1023 KB + // 0xFEE00000 LAPIC 1 MB + // + AddIoMemoryRangeHob (TopOfMemory < BASE_2GB ? BASE_2GB : TopOfMemory, 0xFEC00000); + AddIoMemoryBaseSizeHob (0xFEC00000, SIZE_4KB); + AddIoMemoryBaseSizeHob (0xFED00000, SIZE_1KB); + AddIoMemoryBaseSizeHob (PcdGet32(PcdCpuLocalApicBaseAddress), SIZE_1MB); } diff --git a/OvmfPkg/PlatformPei/PlatformPei.inf b/OvmfPkg/PlatformPei/PlatformPei.inf index db5ed31a6d..8742008c0d 100644 --- a/OvmfPkg/PlatformPei/PlatformPei.inf +++ b/OvmfPkg/PlatformPei/PlatformPei.inf @@ -55,6 +55,7 @@ PeiServicesTablePointerLib PeimEntryPoint MtrrLib + PcdLib [Pcd] gUefiOvmfPkgTokenSpaceGuid.PcdOvmfMemFvBase @@ -63,6 +64,7 @@ gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareSize gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize gEfiMdeModulePkgTokenSpaceGuid.PcdEmuVariableNvStoreReserved + gUefiCpuPkgTokenSpaceGuid.PcdCpuLocalApicBaseAddress [Ppis] gEfiPeiMasterBootModePpiGuid