mirror of https://github.com/acidanthera/audk.git
MdePkg/PCI: Add missing PCI/PCIE definitions
The definitions are required by certain platform initialization code. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ruiyu Ni <ruiyu.ni@intel.com> Cc: Jeff Fan <jeff.fan@intel.com> Cc: Feng Tian <feng.tian@intel.com> Reviewed-by: Amy Chan <amy.chan@intel.com>
This commit is contained in:
Ruiyu Ni
parent
dd85dd0731
commit
cbedba8698
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@ -645,18 +645,6 @@ typedef struct {
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UINT8 NextItemPtr;
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} EFI_PCI_CAPABILITY_HDR;
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///
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/// Power Management Register Block Definition
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/// Section 3.2, PCI Power Management Interface Specifiction, Revision 1.2
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///
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typedef struct {
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EFI_PCI_CAPABILITY_HDR Hdr;
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UINT16 PMC;
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UINT16 PMCSR;
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UINT8 BridgeExtention;
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UINT8 Data;
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} EFI_PCI_CAPABILITY_PMI;
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///
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/// PMC - Power Management Capabilities
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/// Section 3.2.3, PCI Power Management Interface Specifiction, Revision 1.2
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@ -684,7 +672,9 @@ typedef union {
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typedef union {
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struct {
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UINT16 PowerState : 2;
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UINT16 Reserved : 6;
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UINT16 ReservedForPciExpress : 1;
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UINT16 NoSoftReset : 1;
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UINT16 Reserved : 4;
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UINT16 PmeEnable : 1;
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UINT16 DataSelect : 4;
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UINT16 DataScale : 2;
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@ -693,6 +683,36 @@ typedef union {
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UINT16 Data;
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} EFI_PCI_PMCSR;
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#define PCI_POWER_STATE_D0 0
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#define PCI_POWER_STATE_D1 1
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#define PCI_POWER_STATE_D2 2
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#define PCI_POWER_STATE_D3_HOT 3
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///
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/// PMCSR_BSE - PMCSR PCI-to-PCI Bridge Support Extensions
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/// Section 3.2.5, PCI Power Management Interface Specifiction, Revision 1.2
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///
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typedef union {
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struct {
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UINT8 Reserved : 6;
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UINT8 B2B3 : 1;
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UINT8 BusPowerClockControl : 1;
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} Bits;
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UINT8 Uint8;
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} EFI_PCI_PMCSR_BSE;
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///
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/// Power Management Register Block Definition
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/// Section 3.2, PCI Power Management Interface Specifiction, Revision 1.2
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///
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typedef struct {
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EFI_PCI_CAPABILITY_HDR Hdr;
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EFI_PCI_PMC PMC;
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EFI_PCI_PMCSR PMCSR;
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EFI_PCI_PMCSR_BSE BridgeExtention;
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UINT8 Data;
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} EFI_PCI_CAPABILITY_PMI;
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///
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/// A.G.P Capability
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/// Section 6.1.4, Accelerated Graphics Port Interface Specification, Revision 1.0
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@ -1,7 +1,7 @@
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/** @file
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Support for the latest PCI standard.
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Copyright (c) 2006 - 2014, Intel Corporation. All rights reserved.<BR>
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Copyright (c) 2006 - 2016, Intel Corporation. All rights reserved.<BR>
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(C) Copyright 2016 Hewlett Packard Enterprise Development LP<BR>
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This program and the accompanying materials
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are licensed and made available under the terms and conditions of the BSD License
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@ -16,6 +16,337 @@
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#ifndef _PCIEXPRESS21_H_
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#define _PCIEXPRESS21_H_
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#include <IndustryStandard/Pci30.h>
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#pragma pack(1)
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///
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/// PCI Express Capability Structure
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///
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typedef union {
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struct {
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UINT16 Version : 4;
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UINT16 DevicePortType : 4;
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UINT16 SlotImplemented : 1;
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UINT16 InterruptMessageNumber : 5;
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UINT16 Undefined : 1;
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UINT16 Reserved : 1;
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} Bits;
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UINT16 Uint16;
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} PCI_REG_PCIE_CAPABILITY;
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#define PCIE_DEVICE_PORT_TYPE_PCIE_ENDPOINT 0
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#define PCIE_DEVICE_PORT_TYPE_LEGACY_PCIE_ENDPOINT 1
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#define PCIE_DEVICE_PORT_TYPE_ROOT_PORT 4
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#define PCIE_DEVICE_PORT_TYPE_UPSTREAM_PORT 5
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#define PCIE_DEVICE_PORT_TYPE_DOWNSTREAM_PORT 6
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#define PCIE_DEVICE_PORT_TYPE_PCIE_TO_PCI_BRIDGE 7
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#define PCIE_DEVICE_PORT_TYPE_PCI_TO_PCIE_BRIDGE 8
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#define PCIE_DEVICE_PORT_TYPE_ROOT_COMPLEX_INTEGRATED_ENDPOINT 9
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#define PCIE_DEVICE_PORT_TYPE_ROOT_COMPLEX_EVENT_COLLECTOR 10
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typedef union {
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struct {
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UINT32 MaxPayloadSize : 3;
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UINT32 PhantomFunctions : 2;
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UINT32 ExtendedTagField : 1;
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UINT32 EndpointL0sAcceptableLatency : 3;
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UINT32 EndpointL1AcceptableLatency : 3;
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UINT32 Undefined : 3;
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UINT32 RoleBasedErrorReporting : 1;
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UINT32 Reserved : 2;
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UINT32 CapturedSlotPowerLimitValue : 8;
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UINT32 CapturedSlotPowerLimitScale : 2;
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UINT32 FunctionLevelReset : 1;
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UINT32 Reserved2 : 3;
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} Bits;
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UINT32 Uint32;
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} PCI_REG_PCIE_DEVICE_CAPABILITY;
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typedef union {
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struct {
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UINT16 CorrectableError : 1;
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UINT16 NonFatalError : 1;
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UINT16 FatalError : 1;
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UINT16 UnsupportedRequest : 1;
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UINT16 RelaxedOrdering : 1;
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UINT16 MaxPayloadSize : 3;
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UINT16 ExtendedTagField : 1;
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UINT16 PhantomFunctions : 1;
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UINT16 AuxPower : 1;
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UINT16 NoSnoop : 1;
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UINT16 MaxReadRequestSize : 3;
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UINT16 BridgeConfigurationRetryOrFunctionLevelReset : 1;
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} Bits;
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UINT16 Uint16;
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} PCI_REG_PCIE_DEVICE_CONTROL;
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typedef union {
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struct {
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UINT16 CorrectableError : 1;
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UINT16 NonFatalError : 1;
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UINT16 FatalError : 1;
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UINT16 UnsupportedRequest : 1;
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UINT16 AuxPower : 1;
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UINT16 TransactionsPending : 1;
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UINT16 Reserved : 10;
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} Bits;
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UINT16 Uint16;
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} PCI_REG_PCIE_DEVICE_STATUS;
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typedef union {
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struct {
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UINT32 MaxLinkSpeed : 4;
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UINT32 MaxLinkWidth : 6;
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UINT32 Aspm : 2;
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UINT32 L0sExitLatency : 3;
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UINT32 L1ExitLatency : 3;
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UINT32 ClockPowerManagement : 1;
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UINT32 SurpriseDownError : 1;
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UINT32 DataLinkLayerLinkActive : 1;
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UINT32 LinkBandwidthNotification : 1;
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UINT32 AspmOptionalityCompliance : 1;
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UINT32 Reserved : 1;
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UINT32 PortNumber : 8;
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} Bits;
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UINT32 Uint32;
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} PCI_REG_PCIE_LINK_CAPABILITY;
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#define PCIE_LINK_ASPM_L0S BIT0
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#define PCIE_LINK_ASPM_L1 BIT1
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typedef union {
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struct {
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UINT16 AspmControl : 2;
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UINT16 Reserved : 1;
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UINT16 ReadCompletionBoundary : 1;
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UINT16 LinkDisable : 1;
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UINT16 RetrainLink : 1;
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UINT16 CommonClockConfiguration : 1;
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UINT16 ExtendedSynch : 1;
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UINT16 ClockPowerManagement : 1;
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UINT16 HardwareAutonomousWidthDisable : 1;
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UINT16 LinkBandwidthManagementInterrupt : 1;
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UINT16 LinkAutonomousBandwidthInterrupt : 1;
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} Bits;
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UINT16 Uint16;
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} PCI_REG_PCIE_LINK_CONTROL;
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typedef union {
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struct {
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UINT16 CurrentLinkSpeed : 4;
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UINT16 NegotiatedLinkWidth : 6;
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UINT16 Undefined : 1;
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UINT16 LinkTraining : 1;
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UINT16 SlotClockConfiguration : 1;
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UINT16 DataLinkLayerLinkActive : 1;
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UINT16 LinkBandwidthManagement : 1;
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UINT16 LinkAutonomousBandwidth : 1;
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} Bits;
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UINT16 Uint16;
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} PCI_REG_PCIE_LINK_STATUS;
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typedef union {
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struct {
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UINT32 AttentionButton : 1;
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UINT32 PowerController : 1;
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UINT32 MrlSensor : 1;
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UINT32 AttentionIndicator : 1;
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UINT32 PowerIndicator : 1;
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UINT32 HotPlugSurprise : 1;
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UINT32 HotPlugCapable : 1;
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UINT32 SlotPowerLimitValue : 8;
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UINT32 SlotPowerLimitScale : 2;
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UINT32 ElectromechanicalInterlock : 1;
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UINT32 NoCommandCompleted : 1;
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UINT32 PhysicalSlotNumber : 13;
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} Bits;
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UINT32 Uint32;
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} PCI_REG_PCIE_SLOT_CAPABILITY;
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typedef union {
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struct {
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UINT32 AttentionButtonPressed : 1;
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UINT32 PowerFaultDetected : 1;
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UINT32 MrlSensorChanged : 1;
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UINT32 PresenceDetectChanged : 1;
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UINT32 CommandCompletedInterrupt : 1;
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UINT32 HotPlugInterrupt : 1;
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UINT32 AttentionIndicator : 2;
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UINT32 PowerIndicator : 2;
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UINT32 PowerController : 1;
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UINT32 ElectromechanicalInterlock : 1;
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UINT32 DataLinkLayerStateChanged : 1;
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UINT32 Reserved : 3;
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} Bits;
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UINT16 Uint16;
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} PCI_REG_PCIE_SLOT_CONTROL;
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typedef union {
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struct {
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UINT16 AttentionButtonPressed : 1;
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UINT16 PowerFaultDetected : 1;
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UINT16 MrlSensorChanged : 1;
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UINT16 PresenceDetectChanged : 1;
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UINT16 CommandCompleted : 1;
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UINT16 MrlSensor : 1;
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UINT16 PresenceDetect : 1;
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UINT16 ElectromechanicalInterlock : 1;
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UINT16 DataLinkLayerStateChanged : 1;
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UINT16 Reserved : 7;
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} Bits;
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UINT16 Uint16;
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} PCI_REG_PCIE_SLOT_STATUS;
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typedef union {
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struct {
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UINT16 SystemErrorOnCorrectableError : 1;
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UINT16 SystemErrorOnNonFatalError : 1;
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UINT16 SystemErrorOnFatalError : 1;
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UINT16 PmeInterrupt : 1;
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UINT16 CrsSoftwareVisibility : 1;
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UINT16 Reserved : 11;
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} Bits;
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UINT16 Uint16;
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} PCI_REG_PCIE_ROOT_CONTROL;
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typedef union {
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struct {
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UINT16 CrsSoftwareVisibility : 1;
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UINT16 Reserved : 15;
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} Bits;
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UINT16 Uint16;
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} PCI_REG_PCIE_ROOT_CAPABILITY;
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typedef union {
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struct {
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UINT32 PmeRequesterId : 16;
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UINT32 PmeStatus : 1;
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UINT32 PmePending : 1;
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UINT32 Reserved : 14;
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} Bits;
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UINT32 Uint32;
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} PCI_REG_PCIE_ROOT_STATUS;
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typedef union {
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struct {
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UINT32 CompletionTimeoutRanges : 4;
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UINT32 CompletionTimeoutDisable : 1;
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UINT32 AriForwarding : 1;
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UINT32 AtomicOpRouting : 1;
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UINT32 AtomicOp32Completer : 1;
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UINT32 AtomicOp64Completer : 1;
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UINT32 Cas128Completer : 1;
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UINT32 NoRoEnabledPrPrPassing : 1;
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UINT32 LtrMechanism : 1;
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UINT32 TphCompleter : 2;
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UINT32 Reserved : 4;
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UINT32 Obff : 2;
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UINT32 ExtendedFmtField : 1;
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UINT32 EndEndTlpPrefix : 1;
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UINT32 MaxEndEndTlpPrefixes : 2;
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UINT32 Reserved2 : 8;
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} Bits;
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UINT32 Uint32;
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} PCI_REG_PCIE_DEVICE_CAPABILITY2;
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#define PCIE_DEVICE_CAPABILITY_OBFF_MESSAGE BIT0
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#define PCIE_DEVICE_CAPABILITY_OBFF_WAKE BIT1
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typedef union {
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struct {
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UINT16 CompletionTimeoutValue : 4;
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UINT16 CompletionTimeoutDisable : 1;
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UINT16 AriForwarding : 1;
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UINT16 AtomicOpRequester : 1;
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UINT16 AtomicOpEgressBlocking : 1;
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UINT16 IdoRequest : 1;
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UINT16 IdoCompletion : 1;
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UINT16 LtrMechanism : 2;
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UINT16 Reserved : 2;
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UINT16 Obff : 2;
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UINT16 EndEndTlpPrefixBlocking : 1;
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} Bits;
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UINT16 Uint16;
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} PCI_REG_PCIE_DEVICE_CONTROL2;
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#define PCIE_COMPLETION_TIMEOUT_50US_50MS 0
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#define PCIE_COMPLETION_TIMEOUT_50US_100US 1
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#define PCIE_COMPLETION_TIMEOUT_1MS_10MS 2
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#define PCIE_COMPLETION_TIMEOUT_16MS_55MS 5
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#define PCIE_COMPLETION_TIMEOUT_65MS_210MS 6
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#define PCIE_COMPLETION_TIMEOUT_260MS_900MS 9
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#define PCIE_COMPLETION_TIMEOUT_1S_3_5S 10
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#define PCIE_COMPLETION_TIMEOUT_4S_13S 13
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#define PCIE_COMPLETION_TIMEOUT_17S_64S 14
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#define PCIE_DEVICE_CONTROL_OBFF_DISABLED 0
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#define PCIE_DEVICE_CONTROL_OBFF_MESSAGE_A 1
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#define PCIE_DEVICE_CONTROL_OBFF_MESSAGE_B 2
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#define PCIE_DEVICE_CONTROL_OBFF_WAKE 3
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typedef union {
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struct {
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UINT32 Reserved : 1;
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UINT32 LinkSpeedsVector : 7;
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UINT32 Crosslink : 1;
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UINT32 Reserved2 : 23;
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} Bits;
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UINT32 Uint32;
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} PCI_REG_PCIE_LINK_CAPABILITY2;
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typedef union {
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struct {
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UINT16 TargetLinkSpeed : 4;
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UINT16 EnterCompliance : 1;
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UINT16 HardwareAutonomousSpeedDisable : 1;
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UINT16 SelectableDeemphasis : 1;
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UINT16 TransmitMargin : 3;
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UINT16 EnterModifiedCompliance : 1;
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UINT16 ComplianceSos : 1;
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UINT16 CompliancePresetDeemphasis : 4;
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} Bits;
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UINT16 Uint16;
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} PCI_REG_PCIE_LINK_CONTROL2;
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typedef union {
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struct {
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UINT16 CurrentDeemphasisLevel : 1;
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UINT16 EqualizationComplete : 1;
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UINT16 EqualizationPhase1Successful : 1;
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UINT16 EqualizationPhase2Successful : 1;
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UINT16 EqualizationPhase3Successful : 1;
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UINT16 LinkEqualizationRequest : 1;
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UINT16 Reserved : 10;
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} Bits;
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UINT16 Uint16;
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} PCI_REG_PCIE_LINK_STATUS2;
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typedef struct {
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EFI_PCI_CAPABILITY_HDR Hdr;
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PCI_REG_PCIE_CAPABILITY Capability;
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PCI_REG_PCIE_DEVICE_CAPABILITY DeviceCapability;
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PCI_REG_PCIE_DEVICE_CONTROL DeviceControl;
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PCI_REG_PCIE_DEVICE_STATUS DeviceStatus;
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PCI_REG_PCIE_LINK_CAPABILITY LinkCapability;
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PCI_REG_PCIE_LINK_CONTROL LinkControl;
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PCI_REG_PCIE_LINK_STATUS LinkStatus;
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PCI_REG_PCIE_SLOT_CAPABILITY SlotCapability;
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PCI_REG_PCIE_SLOT_CONTROL SlotControl;
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PCI_REG_PCIE_SLOT_STATUS SlotStatus;
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PCI_REG_PCIE_ROOT_CONTROL RootControl;
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PCI_REG_PCIE_ROOT_CAPABILITY RootCapability;
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PCI_REG_PCIE_ROOT_STATUS RootStatus;
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PCI_REG_PCIE_DEVICE_CAPABILITY2 DeviceCapability2;
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PCI_REG_PCIE_DEVICE_CONTROL2 DeviceControl2;
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UINT16 DeviceStatus2;
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PCI_REG_PCIE_LINK_CAPABILITY2 LinkCapability2;
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PCI_REG_PCIE_LINK_CONTROL2 LinkControl2;
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PCI_REG_PCIE_LINK_STATUS2 LinkStatus2;
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UINT32 SlotCapability2;
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UINT16 SlotControl2;
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UINT16 SlotStatus2;
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} PCI_CAPABILITY_PCIEXP;
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#define EFI_PCIE_CAPABILITY_BASE_OFFSET 0x100
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#define EFI_PCIE_CAPABILITY_ID_SRIOV_CONTROL_ARI_HIERARCHY 0x10
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#define EFI_PCIE_CAPABILITY_DEVICE_CAPABILITIES_2_OFFSET 0x24
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@ -83,11 +414,37 @@ typedef struct {
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#define PCI_EXPRESS_EXTENDED_CAPABILITY_ADVANCED_ERROR_REPORTING_VER1 0x1
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#define PCI_EXPRESS_EXTENDED_CAPABILITY_ADVANCED_ERROR_REPORTING_VER2 0x2
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typedef union {
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struct {
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UINT32 Undefined : 1;
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UINT32 Reserved : 3;
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UINT32 DataLinkProtocolError : 1;
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UINT32 SurpriseDownError : 1;
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UINT32 Reserved2 : 6;
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UINT32 PoisonedTlp : 1;
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UINT32 FlowControlProtocolError : 1;
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UINT32 CompletionTimeout : 1;
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UINT32 CompleterAbort : 1;
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UINT32 UnexpectedCompletion : 1;
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UINT32 ReceiverOverflow : 1;
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UINT32 MalformedTlp : 1;
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UINT32 EcrcError : 1;
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UINT32 UnsupportedRequestError : 1;
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UINT32 AcsVoilation : 1;
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UINT32 UncorrectableInternalError : 1;
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UINT32 McBlockedTlp : 1;
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UINT32 AtomicOpEgressBlocked : 1;
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UINT32 TlpPrefixBlockedError : 1;
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UINT32 Reserved3 : 6;
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} Bits;
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UINT32 Uint32;
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} PCI_EXPRESS_REG_UNCORRECTABLE_ERROR;
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typedef struct {
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PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER Header;
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UINT32 UncorrectableErrorStatus;
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UINT32 UncorrectableErrorMask;
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UINT32 UncorrectableErrorSeverity;
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PCI_EXPRESS_REG_UNCORRECTABLE_ERROR UncorrectableErrorStatus;
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PCI_EXPRESS_REG_UNCORRECTABLE_ERROR UncorrectableErrorMask;
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PCI_EXPRESS_REG_UNCORRECTABLE_ERROR UncorrectableErrorSeverity;
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UINT32 CorrectableErrorStatus;
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UINT32 CorrectableErrorMask;
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UINT32 AdvancedErrorCapabilitiesAndControl;
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@ -289,4 +646,6 @@ typedef struct {
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#define GET_TPH_TABLE_SIZE(x) ((x->TphRequesterCapability & 0x7FF0000)>>16) * sizeof(UINT16)
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#pragma pack()
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#endif
|
||||
|
|
|
|||
|
|
@ -3,7 +3,7 @@
|
|||
|
||||
This header file may not define all structures. Please extend as required.
|
||||
|
||||
Copyright (c) 2014, Intel Corporation. All rights reserved.<BR>
|
||||
Copyright (c) 2014 - 2016, Intel Corporation. All rights reserved.<BR>
|
||||
This program and the accompanying materials
|
||||
are licensed and made available under the terms and conditions of the BSD License
|
||||
which accompanies this distribution. The full text of the license may be found at
|
||||
|
|
@ -17,16 +17,41 @@
|
|||
#ifndef _PCIEXPRESS30_H_
|
||||
#define _PCIEXPRESS30_H_
|
||||
|
||||
#include "PciExpress21.h"
|
||||
#include <IndustryStandard/PciExpress21.h>
|
||||
|
||||
#pragma pack(1)
|
||||
|
||||
#define PCI_EXPRESS_EXTENDED_CAPABILITY_SECONDARY_PCIE_ID 0x0019
|
||||
#define PCI_EXPRESS_EXTENDED_CAPABILITY_SECONDARY_PCIE_VER1 0x1
|
||||
|
||||
typedef union {
|
||||
struct {
|
||||
UINT32 PerformEqualization : 1;
|
||||
UINT32 LinkEqualizationRequestInterruptEnable : 1;
|
||||
UINT32 Reserved : 30;
|
||||
} Bits;
|
||||
UINT32 Uint32;
|
||||
} PCI_EXPRESS_REG_LINK_CONTROL3;
|
||||
|
||||
typedef union {
|
||||
struct {
|
||||
UINT16 DownstreamPortTransmitterPreset : 4;
|
||||
UINT16 DownstreamPortReceiverPresetHint : 3;
|
||||
UINT16 Reserved : 1;
|
||||
UINT16 UpstreamPortTransmitterPreset : 4;
|
||||
UINT16 UpstreamPortReceiverPresetHint : 3;
|
||||
UINT16 Reserved2 : 1;
|
||||
} Bits;
|
||||
UINT16 Uint16;
|
||||
} PCI_EXPRESS_REG_LANE_EQUALIZATION_CONTROL;
|
||||
|
||||
typedef struct {
|
||||
PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER Header;
|
||||
UINT32 LinkControl3;
|
||||
PCI_EXPRESS_REG_LINK_CONTROL3 LinkControl3;
|
||||
UINT32 LaneErrorStatus;
|
||||
UINT16 EqualizationControl[2];
|
||||
PCI_EXPRESS_REG_LANE_EQUALIZATION_CONTROL EqualizationControl[2];
|
||||
} PCI_EXPRESS_EXTENDED_CAPABILITIES_SECONDARY_PCIE;
|
||||
|
||||
#pragma pack()
|
||||
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -0,0 +1,78 @@
|
|||
/** @file
|
||||
Support for the PCI Express 3.1 standard.
|
||||
|
||||
This header file may not define all structures. Please extend as required.
|
||||
|
||||
Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>
|
||||
This program and the accompanying materials
|
||||
are licensed and made available under the terms and conditions of the BSD License
|
||||
which accompanies this distribution. The full text of the license may be found at
|
||||
http://opensource.org/licenses/bsd-license.php
|
||||
|
||||
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
|
||||
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
|
||||
|
||||
**/
|
||||
|
||||
#ifndef _PCIEXPRESS31_H_
|
||||
#define _PCIEXPRESS31_H_
|
||||
|
||||
#include <IndustryStandard/PciExpress30.h>
|
||||
|
||||
#pragma pack(1)
|
||||
|
||||
#define PCI_EXPRESS_EXTENDED_CAPABILITY_L1_PM_SUBSTATES_ID 0x001E
|
||||
#define PCI_EXPRESS_EXTENDED_CAPABILITY_L1_PM_SUBSTATES_VER1 0x1
|
||||
|
||||
typedef union {
|
||||
struct {
|
||||
UINT32 PciPmL12 : 1;
|
||||
UINT32 PciPmL11 : 1;
|
||||
UINT32 AspmL12 : 1;
|
||||
UINT32 AspmL11 : 1;
|
||||
UINT32 L1PmSubstates : 1;
|
||||
UINT32 Reserved : 3;
|
||||
UINT32 CommonModeRestoreTime : 8;
|
||||
UINT32 TPowerOnScale : 2;
|
||||
UINT32 Reserved2 : 1;
|
||||
UINT32 TPowerOnValue : 5;
|
||||
UINT32 Reserved3 : 8;
|
||||
} Bits;
|
||||
UINT32 Uint32;
|
||||
} PCI_EXPRESS_REG_L1_PM_SUBSTATES_CAPABILITY;
|
||||
|
||||
typedef union {
|
||||
struct {
|
||||
UINT32 PciPmL12 : 1;
|
||||
UINT32 PciPmL11 : 1;
|
||||
UINT32 AspmL12 : 1;
|
||||
UINT32 AspmL11 : 1;
|
||||
UINT32 Reserved : 4;
|
||||
UINT32 CommonModeRestoreTime : 8;
|
||||
UINT32 LtrL12ThresholdValue : 10;
|
||||
UINT32 Reserved2 : 3;
|
||||
UINT32 LtrL12ThresholdScale : 3;
|
||||
} Bits;
|
||||
UINT32 Uint32;
|
||||
} PCI_EXPRESS_REG_L1_PM_SUBSTATES_CONTROL1;
|
||||
|
||||
typedef union {
|
||||
struct {
|
||||
UINT32 TPowerOnScale : 2;
|
||||
UINT32 Reserved : 1;
|
||||
UINT32 TPowerOnValue : 5;
|
||||
UINT32 Reserved2 : 24;
|
||||
} Bits;
|
||||
UINT32 Uint32;
|
||||
} PCI_EXPRESS_REG_L1_PM_SUBSTATES_CONTROL2;
|
||||
|
||||
typedef struct {
|
||||
PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER Header;
|
||||
PCI_EXPRESS_REG_L1_PM_SUBSTATES_CAPABILITY Capability;
|
||||
PCI_EXPRESS_REG_L1_PM_SUBSTATES_CONTROL1 Control1;
|
||||
PCI_EXPRESS_REG_L1_PM_SUBSTATES_CONTROL2 Control2;
|
||||
} PCI_EXPRESS_EXTENDED_CAPABILITIES_L1_PM_SUBSTATES;
|
||||
|
||||
#pragma pack()
|
||||
|
||||
#endif
|
||||
Loading…
Reference in New Issue