ArmPlatformPkg: Fix ARM RealView EB and VE builds

Tested with RVCTLINUX and ARMGCC toolchains.



git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@12233 6f19259b-4bc3-4df7-8a09-765794883524
This commit is contained in:
oliviermartin 2011-08-30 16:54:48 +00:00
parent 78c2b9a334
commit cc1e814923
5 changed files with 21 additions and 38 deletions

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@ -280,9 +280,9 @@ InitializeDebugAgent (
// modules // modules
if (InitFlag == DEBUG_AGENT_INIT_PREMEM_SEC) { if (InitFlag == DEBUG_AGENT_INIT_PREMEM_SEC) {
// //
// Get the PrePi or PrePeiCore module (defined as SEC type module) // Get the Sec or PrePeiCore module (defined as SEC type module)
// //
Status = GetFfsFile ((EFI_FIRMWARE_VOLUME_HEADER*)PcdGet32(PcdSecureFdBaseAddress), EFI_FV_FILETYPE_SECURITY_CORE, &FfsHeader); Status = GetFfsFile ((EFI_FIRMWARE_VOLUME_HEADER*)PcdGet32(PcdSecureFvBaseAddress), EFI_FV_FILETYPE_SECURITY_CORE, &FfsHeader);
if (!EFI_ERROR(Status)) { if (!EFI_ERROR(Status)) {
Status = GetImageContext (FfsHeader,&ImageContext); Status = GetImageContext (FfsHeader,&ImageContext);
if (!EFI_ERROR(Status)) { if (!EFI_ERROR(Status)) {

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@ -42,21 +42,6 @@ ArmPlatformTrustzoneSupported (
return FALSE; return FALSE;
} }
/**
Initialize the Secure peripherals and memory regions
If Trustzone is supported by your platform then this function makes the required initialization
of the secure peripherals and memory regions.
**/
VOID
ArmPlatformTrustzoneInit (
VOID
)
{
ASSERT(FALSE);
}
/** /**
Remap the memory at 0x0 Remap the memory at 0x0
@ -87,20 +72,6 @@ ArmPlatformGetBootMode (
return BOOT_WITH_FULL_CONFIGURATION; return BOOT_WITH_FULL_CONFIGURATION;
} }
/**
Initialize controllers that must setup at the early stage
Some peripherals must be initialized in Secure World.
For example, some L2x0 requires to be initialized in Secure World
**/
VOID
ArmPlatformSecInitialize (
VOID
) {
// Do nothing yet
}
/** /**
Initialize controllers that must setup in the normal world Initialize controllers that must setup in the normal world

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@ -32,6 +32,7 @@
[Sources.common] [Sources.common]
ArmRealViewEb.c ArmRealViewEb.c
ArmRealViewEbSec.c
ArmRealViewEbHelper.asm | RVCT ArmRealViewEbHelper.asm | RVCT
ArmRealViewEbHelper.S | GCC ArmRealViewEbHelper.S | GCC
ArmRealViewEbBoot.asm | RVCT ArmRealViewEbBoot.asm | RVCT
@ -39,3 +40,6 @@
[FeaturePcd] [FeaturePcd]
gEmbeddedTokenSpaceGuid.PcdCacheEnable gEmbeddedTokenSpaceGuid.PcdCacheEnable
[FixedPcd]
gArmTokenSpaceGuid.PcdNormalFvBaseAddress

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@ -17,13 +17,17 @@
#define _SP804_TIMER_H__ #define _SP804_TIMER_H__
// SP804 Timer constants // SP804 Timer constants
#define SP804_TIMER_LOAD_REG 0x00 // Note: The SP804 Timer module comprises two timers, Timer_0 and Timer_1
#define SP804_TIMER_CURRENT_REG 0x04 // These timers are identical and all their registers have an offset of 0x20
#define SP804_TIMER_CONTROL_REG 0x08 // i.e. SP804_TIMER_0_LOAD_REG = 0x00 and SP804_TIMER_1_LOAD_REG = 0x20
#define SP804_TIMER_INT_CLR_REG 0x0C // Therefore, define all registers only once and adjust the base addresses by 0x20
#define SP804_TIMER_RAW_INT_STS_REG 0x10 #define SP804_TIMER_LOAD_REG 0x00
#define SP804_TIMER_MSK_INT_STS_REG 0x14 #define SP804_TIMER_CURRENT_REG 0x04
#define SP804_TIMER_BG_LOAD_REG 0x18 #define SP804_TIMER_CONTROL_REG 0x08
#define SP804_TIMER_INT_CLR_REG 0x0C
#define SP804_TIMER_RAW_INT_STS_REG 0x10
#define SP804_TIMER_MSK_INT_STS_REG 0x14
#define SP804_TIMER_BG_LOAD_REG 0x18
// Timer control register bit definitions // Timer control register bit definitions
#define SP804_TIMER_CTRL_ONESHOT BIT0 #define SP804_TIMER_CTRL_ONESHOT BIT0
@ -36,6 +40,9 @@
#define SP804_TIMER_CTRL_PERIODIC BIT6 #define SP804_TIMER_CTRL_PERIODIC BIT6
#define SP804_TIMER_CTRL_ENABLE BIT7 #define SP804_TIMER_CTRL_ENABLE BIT7
// Other SP804 Timer definitions
#define SP804_MAX_TICKS 0xFFFFFFFF
// SP810 System Controller constants // SP810 System Controller constants
#define SP810_SYS_CTRL_REG 0x00 #define SP810_SYS_CTRL_REG 0x00
#define SP810_SYS_CTRL_TIMER0_TIMCLK BIT15 // 0=REFCLK, 1=TIMCLK #define SP810_SYS_CTRL_TIMER0_TIMCLK BIT15 // 0=REFCLK, 1=TIMCLK

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@ -43,4 +43,5 @@
gArmPlatformTokenSpaceGuid.PcdPeiServicePtrGlobalOffset gArmPlatformTokenSpaceGuid.PcdPeiServicePtrGlobalOffset
gArmPlatformTokenSpaceGuid.PcdCPUCoresNonSecStackBase gArmPlatformTokenSpaceGuid.PcdCPUCoresNonSecStackBase
gArmPlatformTokenSpaceGuid.PcdCPUCoresNonSecStackSize gArmPlatformTokenSpaceGuid.PcdCPUCoresNonSecStackSize
gArmPlatformTokenSpaceGuid.PcdPeiGlobalVariableSize