mirror of https://github.com/acidanthera/audk.git
OvmfPkg: extract some bits and port offsets common to Q35 and I440FX
The PMBA_RTE and ACPI_TIMER_OFFSET macros apply equally to both boards, plus they are triplicated between the various AcpiTimerLib instances. Define them centrally in "OvmfPlatforms.h". Cc: Gabriel Somlo <somlo@cmu.edu> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Laszlo Ersek <lersek@redhat.com> Acked-by: Gabriel Somlo <somlo@cmu.edu> Tested-by: Gabriel Somlo <somlo@cmu.edu> Reviewed-by: Jordan Justen <jordan.l.justen@intel.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@17436 6f19259b-4bc3-4df7-8a09-765794883524
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@ -27,4 +27,14 @@
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#define OVMF_HOSTBRIDGE_DID \
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PCI_LIB_ADDRESS (0, 0, 0, PCI_DEVICE_ID_OFFSET)
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//
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// Common bits in same-purpose registers
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//
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#define PMBA_RTE BIT0
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//
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// Common IO ports relative to the Power Management Base Address
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//
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#define ACPI_TIMER_OFFSET 0x8
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#endif
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@ -18,16 +18,6 @@
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#include <Library/PcdLib.h>
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#include <OvmfPlatforms.h>
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//
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// Power Management PCI Configuration Register fields
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//
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#define PMBA_RTE BIT0
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//
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// Offset in the Power Management Base Address to the ACPI Timer
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//
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#define ACPI_TIMER_OFFSET 0x8
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//
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// Cached ACPI Timer IO Address
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//
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@ -19,16 +19,6 @@
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#include <Library/PcdLib.h>
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#include <OvmfPlatforms.h>
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//
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// Power Management PCI Configuration Register fields
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//
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#define PMBA_RTE BIT0
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//
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// Offset in the Power Management Base Address to the ACPI Timer
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//
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#define ACPI_TIMER_OFFSET 0x8
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/**
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The constructor function enables ACPI IO space.
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@ -18,16 +18,6 @@
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#include <Library/PciLib.h>
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#include <OvmfPlatforms.h>
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//
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// Power Management PCI Configuration Register fields
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//
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#define PMBA_RTE BIT0
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//
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// Offset in the Power Management Base Address to the ACPI Timer
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//
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#define ACPI_TIMER_OFFSET 0x8
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//
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// Cached ACPI Timer IO Address
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//
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