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IntelFsp2Pkg/GenCfgOpt.py: support FixedAtBuild PCD 

REF: https://bugzilla.tianocore.org/show_bug.cgi?id=1210

FixedAtBuild PCD is suggested to be used instead
of FeatureFlag PCD so extend this tool to support.
Also skipped PCDs which commented out by '#'.

Test: Verified with FixedAtBuild PCD for including or
excluding lines in generated UPD header files successfully.

Cc: Jiewen Yao <Jiewen.yao@intel.com>
Cc: Gao Liming <liming.gao@intel.com>
Cc: Zhu Yonghong <yonghong.zhu@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Chasel Chiu <chasel.chiu@intel.com>
Reviewed-by: Jiewen Yao <Jiewen.yao@intel.com>
This commit is contained in:
Chasel, Chiu 2018-09-26 10:52:36 +08:00
parent 4063d37c6a
commit ccacc4d273
1 changed files with 3 additions and 3 deletions
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6
IntelFsp2Pkg/Tools/GenCfgOpt.py
View File

@ -1,6 +1,6 @@
## @ GenCfgOpt.py ## @ GenCfgOpt.py
# #
# Copyright (c) 2014 - 2017, Intel Corporation. All rights reserved.<BR> # Copyright (c) 2014 - 2018, Intel Corporation. All rights reserved.<BR>
# This program and the accompanying materials are licensed and made available under # This program and the accompanying materials are licensed and made available under
# the terms and conditions of the BSD License that accompanies this distribution. # the terms and conditions of the BSD License that accompanies this distribution.
# The full text of the license may be found at # The full text of the license may be found at
@ -449,7 +449,7 @@ EndList
IsUpdSect = False IsUpdSect = False
if Match.group(1).lower() == "Defines".lower(): if Match.group(1).lower() == "Defines".lower():
IsDefSect = True IsDefSect = True
if Match.group(1).lower() == "PcdsFeatureFlag".lower(): if (Match.group(1).lower() == "PcdsFeatureFlag".lower() or Match.group(1).lower() == "PcdsFixedAtBuild".lower()):
IsPcdSect = True IsPcdSect = True
elif Match.group(1).lower() == "PcdsDynamicVpd.Upd".lower(): elif Match.group(1).lower() == "PcdsDynamicVpd.Upd".lower():
ConfigDict = {} ConfigDict = {}
@ -491,7 +491,7 @@ EndList
IfStack.append(Result) IfStack.append(Result)
ElifStack.append(0) ElifStack.append(0)
else: else:
Match = re.match("!(if|elseif)\s+(.+)", DscLine) Match = re.match("!(if|elseif)\s+(.+)", DscLine.split("#")[0])
if Match: if Match:
Result = self.EvaluateExpress(Match.group(2)) Result = self.EvaluateExpress(Match.group(2))
if Match.group(1) == "if": if Match.group(1) == "if":