diff --git a/MdePkg/Include/Library/BaseLib.h b/MdePkg/Include/Library/BaseLib.h index c1d1fa0900..e414e27399 100644 --- a/MdePkg/Include/Library/BaseLib.h +++ b/MdePkg/Include/Library/BaseLib.h @@ -5019,4 +5019,88 @@ AsmSwitchStackAndBackingStore ( IN VOID *NewBsp ); +typedef struct { + UINT64 Status; + UINT64 r9; + UINT64 r10; + UINT64 r11; +} PAL_PROC_RETURN; + +// +// IPF Specific functions +// + + +/** + Performs a PAL call using static calling convention. + + An internal function to perform a PAL call using static calling convention. + + @param PalEntryPoint The entry point address of PAL. The address in ar.kr5 + would be used if this parameter were NULL on input. + @param Arg1 The first argument of a PAL call. + @param Arg1 The second argument of a PAL call. + @param Arg1 The third argument of a PAL call. + @param Arg1 The fourth argument of a PAL call. + + @return The values returned in r8, r9, r10 and r11. + +**/ +PAL_PROC_RETURN +PalCallStatic ( + IN CONST VOID *PalEntryPoint, + IN UINT64 Arg1, + IN UINT64 Arg2, + IN UINT64 Arg3, + IN UINT64 Arg4 + ); + + +/** + Returns the current value of ar.itc. + + An internal function to return the current value of ar.itc, which is the + timer tick on IPF. + + @return The currect value of ar.itc + +**/ +INT64 +IpfReadItc ( + VOID + ); + + +/** + Invalidates a range of instruction cache lines in the cache coherency domain + of the calling CPU. + + Invalidates the instruction cache lines specified by Address and Length. If + Address is not aligned on a cache line boundary, then entire instruction + cache line containing Address is invalidated. If Address + Length is not + aligned on a cache line boundary, then the entire instruction cache line + containing Address + Length -1 is invalidated. This function may choose to + invalidate the entire instruction cache if that is more efficient than + invalidating the specified range. If Length is 0, the no instruction cache + lines are invalidated. Address is returned. + + If Length is greater than (MAX_ADDRESS - Address + 1), then ASSERT(). + + @param Address The base address of the instruction cache lines to + invalidate. If the CPU is in a physical addressing mode, then + Address is a physical address. If the CPU is in a virtual + addressing mode, then Address is a virtual address. + + @param Length The number of bytes to invalidate from the instruction cache. + + @return Address + +**/ +VOID * +EFIAPI +IpfInvalidateInstructionCacheRange ( + IN VOID *Address, + IN UINTN Length + ); + #endif diff --git a/MdePkg/Library/BaseCacheMaintenanceLib/BaseCacheMaintenanceLib.msa b/MdePkg/Library/BaseCacheMaintenanceLib/BaseCacheMaintenanceLib.msa index 02ea370151..16d5b20998 100644 --- a/MdePkg/Library/BaseCacheMaintenanceLib/BaseCacheMaintenanceLib.msa +++ b/MdePkg/Library/BaseCacheMaintenanceLib/BaseCacheMaintenanceLib.msa @@ -1,19 +1,19 @@ - + BaseCacheMaintenanceLib BASE 123dd843-57c9-4158-8418-ce68b3944ce7 1.0 Component description file for Base Cache Maintenance Library - Cache Maintenance Library that uses Base Library services to maintain caches. + Cache Maintenance Library that uses Base Library services to maintain caches. This library assumes there are no chipset dependencies required to maintain caches. Copyright (c) 2006, Intel Corporation - All rights reserved. This program and the accompanying materials - are licensed and made available under the terms and conditions of the BSD License - which accompanies this distribution. The full text of the license may be found at - http://opensource.org/licenses/bsd-license.php - THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + All rights reserved. This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. FRAMEWORK_BUILD_PACKAGING_SPECIFICATION 0x00000052 @@ -38,8 +38,6 @@ x86Cache.c EbcCache.c IpfCache.c - Ipf/Cpu.s - Ipf/PalCallStatic.s diff --git a/MdePkg/Library/BaseCacheMaintenanceLib/IpfCache.c b/MdePkg/Library/BaseCacheMaintenanceLib/IpfCache.c index 7e96d9b76a..0c6f0e4dc8 100644 --- a/MdePkg/Library/BaseCacheMaintenanceLib/IpfCache.c +++ b/MdePkg/Library/BaseCacheMaintenanceLib/IpfCache.c @@ -12,21 +12,6 @@ **/ -typedef struct { - UINT64 Status; - UINT64 r9; - UINT64 r10; - UINT64 r11; -} PAL_PROC_RETURN; - -PAL_PROC_RETURN -PalCallStatic ( - IN CONST VOID *PalEntryPoint, - IN UINT64 Arg1, - IN UINT64 Arg2, - IN UINT64 Arg3, - IN UINT64 Arg4 - ); /** Invalidates the entire instruction cache in cache coherency domain of the @@ -45,6 +30,41 @@ InvalidateInstructionCache ( PalCallStatic (NULL, 1, 1, 1, 0); } +/** + Invalidates a range of instruction cache lines in the cache coherency domain + of the calling CPU. + + Invalidates the instruction cache lines specified by Address and Length. If + Address is not aligned on a cache line boundary, then entire instruction + cache line containing Address is invalidated. If Address + Length is not + aligned on a cache line boundary, then the entire instruction cache line + containing Address + Length -1 is invalidated. This function may choose to + invalidate the entire instruction cache if that is more efficient than + invalidating the specified range. If Length is 0, the no instruction cache + lines are invalidated. Address is returned. + + If Length is greater than (MAX_ADDRESS - Address + 1), then ASSERT(). + + @param Address The base address of the instruction cache lines to + invalidate. If the CPU is in a physical addressing mode, then + Address is a physical address. If the CPU is in a virtual + addressing mode, then Address is a virtual address. + + @param Length The number of bytes to invalidate from the instruction cache. + + @return Address + +**/ +VOID * +EFIAPI +InvalidateInstructionCacheRange ( + IN VOID *Address, + IN UINTN Length + ) +{ + return IpfInvalidateInstructionCacheRange (Address, Length); +} + /** Writes Back and Invalidates the entire data cache in cache coherency domain of the calling CPU. diff --git a/MdePkg/Library/BaseLib/BaseLib.msa b/MdePkg/Library/BaseLib/BaseLib.msa index 5d24dcf425..52dbf7304a 100644 --- a/MdePkg/Library/BaseLib/BaseLib.msa +++ b/MdePkg/Library/BaseLib/BaseLib.msa @@ -1,4 +1,4 @@ - +