diff --git a/ArmPkg/Drivers/CpuDxe/Mmu.c b/ArmPkg/Drivers/CpuDxe/Mmu.c
index f54350b5a2..7bed1f69c0 100644
--- a/ArmPkg/Drivers/CpuDxe/Mmu.c
+++ b/ArmPkg/Drivers/CpuDxe/Mmu.c
@@ -784,7 +784,7 @@ ConvertSectionToPages (
   // formulate page table entry, Domain=0, NS=0
   PageTableDescriptor = (((UINTN)PageTableAddr) & TT_DESCRIPTOR_SECTION_PAGETABLE_ADDRESS_MASK) | TT_DESCRIPTOR_SECTION_TYPE_PAGE_TABLE;
 
-  // write the page table entry out, repalcing section entry
+  // write the page table entry out, replacing section entry
   FirstLevelTable[FirstLevelIdx] = PageTableDescriptor;
 
   return EFI_SUCCESS;
diff --git a/ArmPkg/Drivers/PL390Gic/PL390GicSec.c b/ArmPkg/Drivers/PL390Gic/PL390GicSec.c
index 25038bd63f..e47e23d581 100644
--- a/ArmPkg/Drivers/PL390Gic/PL390GicSec.c
+++ b/ArmPkg/Drivers/PL390Gic/PL390GicSec.c
@@ -99,7 +99,7 @@ ArmGicEnableInterruptInterface (
   MmioWrite32 (GicInterruptInterfaceBase + ARM_GIC_ICCPMR, 0x000000FF);
 
   // Enable CPU interface in Secure world
-  // Enable CPU inteface in Non-secure World
+  // Enable CPU interface in Non-secure World
   // Signal Secure Interrupts to CPU using FIQ line *
   MmioWrite32 (GicInterruptInterfaceBase + ARM_GIC_ICCICR,
       ARM_GIC_ICCICR_ENABLE_SECURE |
diff --git a/ArmPkg/Library/ArmArchTimerLib/ArmArchTimerLib.c b/ArmPkg/Library/ArmArchTimerLib/ArmArchTimerLib.c
index d4602738ec..8c1fe415dc 100644
--- a/ArmPkg/Library/ArmArchTimerLib/ArmArchTimerLib.c
+++ b/ArmPkg/Library/ArmArchTimerLib/ArmArchTimerLib.c
@@ -54,7 +54,7 @@ TimerConstructor (
     ASSERT (TimerFreq);
 
   } else {
-    DEBUG ((EFI_D_ERROR, "ARM Architectural Timer is not available in the CPU, Hence cann't use this library \n"));
+    DEBUG ((EFI_D_ERROR, "ARM Architectural Timer is not available in the CPU, hence this library can not be used.\n"));
     ASSERT (0);
   }
 
@@ -79,7 +79,7 @@ MicroSecondDelay (
   UINT64 TimerTicks64;
   UINT64 SystemCounterVal;
 
-  // Calculate counter ticks that can represent requsted delay
+  // Calculate counter ticks that can represent requested delay
   TimerTicks64 = MultU64x32 (MicroSeconds, TICKS_PER_MICRO_SEC);
 
   // Read System Counter value
@@ -106,7 +106,7 @@ MicroSecondDelay (
 
   @param  NanoSeconds The minimum number of nanoseconds to delay.
 
-  @return The value of NanoSeconds inputted.
+  @return The value of NanoSeconds inputed.
 
 **/
 UINTN
diff --git a/ArmPkg/Library/ArmLib/ArmV7/ArmV7ArchTimer.c b/ArmPkg/Library/ArmLib/ArmV7/ArmV7ArchTimer.c
index 1cba12d300..7835b414c0 100644
--- a/ArmPkg/Library/ArmLib/ArmV7/ArmV7ArchTimer.c
+++ b/ArmPkg/Library/ArmLib/ArmV7/ArmV7ArchTimer.c
@@ -83,7 +83,7 @@ ArmArchTimerReadReg (
     case CnthpTval:
     case CnthpCtl:
     case CnthpCval:
-    DEBUG ((EFI_D_ERROR, "The register is related to Hyperviser Mode. Can't perform requested operation\n "));
+    DEBUG ((EFI_D_ERROR, "The register is related to Hypervisor Mode. Can't perform requested operation\n "));
       break;
 
     default:
diff --git a/ArmPlatformPkg/PrePi/ModuleEntryPoint.S b/ArmPlatformPkg/PrePi/ModuleEntryPoint.S
index 845ae208b2..a5593d7290 100755
--- a/ArmPlatformPkg/PrePi/ModuleEntryPoint.S
+++ b/ArmPlatformPkg/PrePi/ModuleEntryPoint.S
@@ -108,7 +108,7 @@ _GetStackBaseMpCore:
   LoadConstantToReg (FixedPcdGet32(PcdCPUCorePrimaryStackSize), r2)
   sub   r7, r1, r2
 
-  // Stack for the secondary core = Number of Cluster * (4 Core per cluster) * SecondaryStackSize
+  // Stack for the secondary core = Number of Clusters * (4 Cores per cluster) * SecondaryStackSize
   LoadConstantToReg (FixedPcdGet32(PcdClusterCount), r2)
   lsl   r2, r2, #2
   LoadConstantToReg (FixedPcdGet32(PcdCPUCoreSecondaryStackSize), r3)
diff --git a/ArmPlatformPkg/PrePi/ModuleEntryPoint.asm b/ArmPlatformPkg/PrePi/ModuleEntryPoint.asm
index 780371c15c..0c7299a995 100644
--- a/ArmPlatformPkg/PrePi/ModuleEntryPoint.asm
+++ b/ArmPlatformPkg/PrePi/ModuleEntryPoint.asm
@@ -109,7 +109,7 @@ _GetStackBaseMpCore
   LoadConstantToReg (FixedPcdGet32(PcdCPUCorePrimaryStackSize), r2)
   sub   r7, r1, r2
 
-  // Stack for the secondary core = Number of Cluster * (4 Core per cluster) * SecondaryStackSize
+  // Stack for the secondary core = Number of Clusters * (4 Cores per cluster) * SecondaryStackSize
   LoadConstantToReg (FixedPcdGet32(PcdClusterCount), r2)
   lsl   r2, r2, #2
   LoadConstantToReg (FixedPcdGet32(PcdCPUCoreSecondaryStackSize), r3)