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ArmPlatformPkg/PrePi: Drop MPCore variant
The PrePi SEC driver can be built in unicore and MPcore versions from [mostly] the same source. The latter is obsolete, so remove it and simplyify the remaining code accordingly. Signed-off-by: Ard Biesheuvel <ardb@kernel.org>
This commit is contained in:
Ard Biesheuvel
mergify[bot]
parent
4fc1c513f8
commit
cee49c82d5
@ -123,7 +123,6 @@
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ArmPlatformPkg/PrePeiCore/PrePeiCoreMPCore.inf
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ArmPlatformPkg/PrePeiCore/PrePeiCoreUniCore.inf
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ArmPlatformPkg/PrePi/PeiMPCore.inf
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ArmPlatformPkg/PrePi/PeiUniCore.inf
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ArmPlatformPkg/Library/ArmMaliDp/ArmMaliDp.inf
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@ -1,104 +0,0 @@
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/** @file
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Copyright (c) 2011-2014, ARM Limited. All rights reserved.
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SPDX-License-Identifier: BSD-2-Clause-Patent
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**/
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#include "PrePi.h"
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#include <Library/ArmGicLib.h>
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#include <Ppi/ArmMpCoreInfo.h>
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VOID
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PrimaryMain (
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IN UINTN UefiMemoryBase,
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IN UINTN StacksBase,
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IN UINT64 StartTimeStamp
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)
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{
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// Enable the GIC Distributor
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ArmGicEnableDistributor (PcdGet64 (PcdGicDistributorBase));
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// In some cases, the secondary cores are waiting for an SGI from the next stage boot loader to resume their initialization
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if (!FixedPcdGet32 (PcdSendSgiToBringUpSecondaryCores)) {
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// Sending SGI to all the Secondary CPU interfaces
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ArmGicSendSgiTo (PcdGet64 (PcdGicDistributorBase), ARM_GIC_ICDSGIR_FILTER_EVERYONEELSE, 0x0E, PcdGet32 (PcdGicSgiIntId));
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}
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PrePiMain (UefiMemoryBase, StacksBase, StartTimeStamp);
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// We must never return
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ASSERT (FALSE);
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}
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VOID
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SecondaryMain (
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IN UINTN MpId
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)
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{
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EFI_STATUS Status;
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ARM_MP_CORE_INFO_PPI *ArmMpCoreInfoPpi;
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UINTN Index;
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UINTN ArmCoreCount;
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ARM_CORE_INFO *ArmCoreInfoTable;
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UINT32 ClusterId;
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UINT32 CoreId;
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VOID (*SecondaryStart)(
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VOID
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);
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UINTN SecondaryEntryAddr;
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UINTN AcknowledgeInterrupt;
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UINTN InterruptId;
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ClusterId = GET_CLUSTER_ID (MpId);
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CoreId = GET_CORE_ID (MpId);
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// On MP Core Platform we must implement the ARM MP Core Info PPI (gArmMpCoreInfoPpiGuid)
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Status = GetPlatformPpi (&gArmMpCoreInfoPpiGuid, (VOID **)&ArmMpCoreInfoPpi);
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ASSERT_EFI_ERROR (Status);
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ArmCoreCount = 0;
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Status = ArmMpCoreInfoPpi->GetMpCoreInfo (&ArmCoreCount, &ArmCoreInfoTable);
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ASSERT_EFI_ERROR (Status);
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// Find the core in the ArmCoreTable
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for (Index = 0; Index < ArmCoreCount; Index++) {
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if ((GET_MPIDR_AFF1 (ArmCoreInfoTable[Index].Mpidr) == ClusterId) &&
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(GET_MPIDR_AFF0 (ArmCoreInfoTable[Index].Mpidr) == CoreId))
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{
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break;
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}
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}
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// The ARM Core Info Table must define every core
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ASSERT (Index != ArmCoreCount);
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// Clear Secondary cores MailBox
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MmioWrite32 (ArmCoreInfoTable[Index].MailboxClearAddress, ArmCoreInfoTable[Index].MailboxClearValue);
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do {
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ArmCallWFI ();
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// Read the Mailbox
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SecondaryEntryAddr = MmioRead32 (ArmCoreInfoTable[Index].MailboxGetAddress);
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// Acknowledge the interrupt and send End of Interrupt signal.
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AcknowledgeInterrupt = ArmGicAcknowledgeInterrupt (PcdGet64 (PcdGicInterruptInterfaceBase), &InterruptId);
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// Check if it is a valid interrupt ID
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if (InterruptId < ArmGicGetMaxNumInterrupts (PcdGet64 (PcdGicDistributorBase))) {
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// Got a valid SGI number hence signal End of Interrupt
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ArmGicEndOfInterrupt (PcdGet64 (PcdGicInterruptInterfaceBase), AcknowledgeInterrupt);
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}
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} while (SecondaryEntryAddr == 0);
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// Jump to secondary core entry point.
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SecondaryStart = (VOID (*)()) SecondaryEntryAddr;
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SecondaryStart ();
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// The secondaries shouldn't reach here
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ASSERT (FALSE);
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}
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@ -1,31 +0,0 @@
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/** @file
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Copyright (c) 2011, ARM Limited. All rights reserved.
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SPDX-License-Identifier: BSD-2-Clause-Patent
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**/
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#include "PrePi.h"
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VOID
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PrimaryMain (
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IN UINTN UefiMemoryBase,
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IN UINTN StacksBase,
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IN UINT64 StartTimeStamp
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)
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{
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PrePiMain (UefiMemoryBase, StacksBase, StartTimeStamp);
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// We must never return
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ASSERT (FALSE);
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}
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VOID
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SecondaryMain (
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IN UINTN MpId
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)
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{
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// We must never get into this function on UniCore system
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ASSERT (FALSE);
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}
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@ -1,106 +0,0 @@
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#/** @file
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#
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# (C) Copyright 2015 Hewlett-Packard Development Company, L.P.<BR>
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# Copyright (c) 2011-2017, ARM Ltd. All rights reserved.<BR>
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#
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# SPDX-License-Identifier: BSD-2-Clause-Patent
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#
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#**/
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[Defines]
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INF_VERSION = 1.30
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BASE_NAME = ArmPlatformPrePiMPCore
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FILE_GUID = d959e387-7b91-452c-90e0-a1dbac90ddb8
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MODULE_TYPE = SEC
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VERSION_STRING = 1.0
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[Sources]
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PrePi.h
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PrePi.c
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MainMPCore.c
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[Sources.ARM]
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Arm/ArchPrePi.c
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Arm/ModuleEntryPoint.S | GCC
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[Sources.AArch64]
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AArch64/ArchPrePi.c
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AArch64/ModuleEntryPoint.S
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[Packages]
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MdePkg/MdePkg.dec
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MdeModulePkg/MdeModulePkg.dec
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EmbeddedPkg/EmbeddedPkg.dec
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ArmPkg/ArmPkg.dec
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ArmPlatformPkg/ArmPlatformPkg.dec
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[LibraryClasses]
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BaseLib
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CacheMaintenanceLib
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DebugLib
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DebugAgentLib
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ArmLib
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ArmGicLib
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IoLib
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TimerLib
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SerialPortLib
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ExtractGuidedSectionLib
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LzmaDecompressLib
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DebugAgentLib
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PrePiLib
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ArmPlatformLib
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ArmPlatformStackLib
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MemoryAllocationLib
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HobLib
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PrePiHobListPointerLib
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PlatformPeiLib
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MemoryInitPeiLib
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[Ppis]
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gArmMpCoreInfoPpiGuid
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[Guids]
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gArmMpCoreInfoGuid
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gEfiFirmwarePerformanceGuid
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[FeaturePcd]
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gEmbeddedTokenSpaceGuid.PcdPrePiProduceMemoryTypeInformationHob
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gArmPlatformTokenSpaceGuid.PcdSendSgiToBringUpSecondaryCores
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[Pcd]
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gEfiMdeModulePkgTokenSpaceGuid.PcdFirmwareVersionString
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[FixedPcd]
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gArmTokenSpaceGuid.PcdVFPEnabled
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gArmTokenSpaceGuid.PcdFdBaseAddress
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gArmTokenSpaceGuid.PcdFdSize
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gArmTokenSpaceGuid.PcdFvBaseAddress
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gArmTokenSpaceGuid.PcdFvSize
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gArmPlatformTokenSpaceGuid.PcdCPUCorePrimaryStackSize
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gArmPlatformTokenSpaceGuid.PcdCPUCoreSecondaryStackSize
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gArmTokenSpaceGuid.PcdGicDistributorBase
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gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase
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gArmTokenSpaceGuid.PcdGicSgiIntId
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gArmTokenSpaceGuid.PcdSystemMemoryBase
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gArmTokenSpaceGuid.PcdSystemMemorySize
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gArmPlatformTokenSpaceGuid.PcdSystemMemoryUefiRegionSize
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gArmPlatformTokenSpaceGuid.PcdCoreCount
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gEmbeddedTokenSpaceGuid.PcdPrePiCpuIoSize
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gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiACPIReclaimMemory
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gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiACPIMemoryNVS
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gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiReservedMemoryType
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gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiRuntimeServicesData
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gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiRuntimeServicesCode
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gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiBootServicesCode
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gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiBootServicesData
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gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiLoaderCode
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gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiLoaderData
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@ -18,7 +18,6 @@
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[Sources]
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PrePi.h
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PrePi.c
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MainUniCore.c
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[Sources.ARM]
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Arm/ArchPrePi.c
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@ -108,14 +108,8 @@ PrePiMain (
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Status = MemoryPeim (UefiMemoryBase, FixedPcdGet32 (PcdSystemMemoryUefiRegionSize));
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ASSERT_EFI_ERROR (Status);
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// Create the Stacks HOB (reserve the memory for all stacks)
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if (ArmIsMpCore ()) {
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StacksSize = PcdGet32 (PcdCPUCorePrimaryStackSize) +
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((FixedPcdGet32 (PcdCoreCount) - 1) * FixedPcdGet32 (PcdCPUCoreSecondaryStackSize));
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} else {
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StacksSize = PcdGet32 (PcdCPUCorePrimaryStackSize);
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}
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// Create the Stacks HOB
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StacksSize = PcdGet32 (PcdCPUCorePrimaryStackSize);
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BuildStackHob (StacksBase, StacksSize);
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// TODO: Call CpuPei as a library
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@ -177,7 +171,7 @@ CEntryPoint (
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// Initialize the platform specific controllers
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ArmPlatformInitialize (MpId);
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if (ArmPlatformIsPrimaryCore (MpId) && PerformanceMeasurementEnabled ()) {
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if (PerformanceMeasurementEnabled ()) {
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// Initialize the Timer Library to setup the Timer HW controller
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TimerConstructor ();
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// We cannot call yet the PerformanceLib because the HOB List has not been initialized
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@ -193,31 +187,12 @@ CEntryPoint (
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// Enable Instruction Caches on all cores.
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ArmEnableInstructionCache ();
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// Define the Global Variable region when we are not running in XIP
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if (!IS_XIP ()) {
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if (ArmPlatformIsPrimaryCore (MpId)) {
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if (ArmIsMpCore ()) {
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// Signal the Global Variable Region is defined (event: ARM_CPU_EVENT_DEFAULT)
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ArmCallSEV ();
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}
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} else {
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// Wait the Primary core has defined the address of the Global Variable region (event: ARM_CPU_EVENT_DEFAULT)
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ArmCallWFE ();
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}
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}
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InvalidateDataCacheRange (
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(VOID *)UefiMemoryBase,
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FixedPcdGet32 (PcdSystemMemoryUefiRegionSize)
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);
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// If not primary Jump to Secondary Main
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if (ArmPlatformIsPrimaryCore (MpId)) {
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InvalidateDataCacheRange (
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(VOID *)UefiMemoryBase,
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FixedPcdGet32 (PcdSystemMemoryUefiRegionSize)
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);
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// Goto primary Main.
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PrimaryMain (UefiMemoryBase, StacksBase, StartTimeStamp);
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} else {
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SecondaryMain (MpId);
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}
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PrePiMain (UefiMemoryBase, StacksBase, StartTimeStamp);
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// DXE Core should always load and never return
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ASSERT (FALSE);
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@ -29,13 +29,6 @@ TimerConstructor (
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VOID
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);
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VOID
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PrePiMain (
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IN UINTN UefiMemoryBase,
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IN UINTN StacksBase,
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IN UINT64 StartTimeStamp
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);
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EFI_STATUS
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EFIAPI
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MemoryPeim (
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@ -49,18 +42,6 @@ PlatformPeim (
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VOID
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);
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VOID
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PrimaryMain (
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IN UINTN UefiMemoryBase,
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IN UINTN StacksBase,
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IN UINT64 StartTimeStamp
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);
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VOID
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SecondaryMain (
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IN UINTN MpId
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);
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// Either implemented by PrePiLib or by MemoryInitPei
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VOID
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BuildMemoryTypeInformationHob (
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