mirror of https://github.com/acidanthera/audk.git
UefiCpuPkg/PiSmmCpuDxe: code refinement for CpuS3.c
This commit is code logic refinement for s3 boot flow in CpuS3.c. It doesn't change any code functionality. This commit implementes InitializeAp and InitializeBsp as a single function since they are doing almost the same thing. Then both BSP and AP will execute the same function InitializeCpuProcedure to do CPU initialization. This can make the code logic easier to understand. Signed-off-by: Dun Tan <dun.tan@intel.com> Cc: Eric Dong <eric.dong@intel.com> Reviewed-by: Ray Ni <ray.ni@intel.com> Cc: Rahul Kumar <rahul1.kumar@intel.com>
This commit is contained in:
Dun Tan
mergify[bot]
parent
48de494bb4
commit
cf82c09bac
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@ -539,44 +539,149 @@ SetRegister (
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}
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/**
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AP initialization before then after SMBASE relocation in the S3 boot path.
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The function is invoked before SMBASE relocation in S3 path to restores CPU status.
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The function is invoked before SMBASE relocation in S3 path. It does first time microcode load
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and restores MTRRs for both BSP and APs.
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@param IsBsp The CPU this function executes on is BSP or not.
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**/
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VOID
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InitializeAp (
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VOID
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InitializeCpuBeforeRebase (
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IN BOOLEAN IsBsp
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)
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{
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UINTN TopOfStack;
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UINT8 Stack[128];
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LoadMtrrData (mAcpiCpuData.MtrrTable);
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SetRegister (TRUE);
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ProgramVirtualWireMode ();
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if (!IsBsp) {
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DisableLvtInterrupts ();
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}
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//
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// Count down the number with lock mechanism.
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//
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InterlockedDecrement (&mNumberToFinish);
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//
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// Wait for BSP to signal SMM Base relocation done.
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//
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while (!mInitApsAfterSmmBaseReloc) {
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CpuPause ();
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if (IsBsp) {
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//
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// Bsp wait here till all AP finish the initialization before rebase
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//
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while (mNumberToFinish > 0) {
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CpuPause ();
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}
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}
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}
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ProgramVirtualWireMode ();
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DisableLvtInterrupts ();
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/**
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The function is invoked after SMBASE relocation in S3 path to restores CPU status.
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The function is invoked after SMBASE relocation in S3 path. It restores configuration according to
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data saved by normal boot path for both BSP and APs.
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@param IsBsp The CPU this function executes on is BSP or not.
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**/
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VOID
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InitializeCpuAfterRebase (
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IN BOOLEAN IsBsp
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)
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{
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UINTN TopOfStack;
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UINT8 Stack[128];
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SetRegister (FALSE);
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if (IsBsp) {
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while (mNumberToFinish > 0) {
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CpuPause ();
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}
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} else {
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//
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// Place AP into the safe code, count down the number with lock mechanism in the safe code.
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//
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TopOfStack = (UINTN)Stack + sizeof (Stack);
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TopOfStack &= ~(UINTN)(CPU_STACK_ALIGNMENT - 1);
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CopyMem ((VOID *)(UINTN)mApHltLoopCode, mApHltLoopCodeTemplate, sizeof (mApHltLoopCodeTemplate));
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TransferApToSafeState ((UINTN)mApHltLoopCode, TopOfStack, (UINTN)&mNumberToFinish);
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}
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}
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/**
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Cpu initialization procedure.
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@param[in,out] Buffer The pointer to private data buffer.
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**/
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VOID
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EFIAPI
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InitializeCpuProcedure (
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IN OUT VOID *Buffer
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)
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{
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BOOLEAN IsBsp;
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IsBsp = (BOOLEAN)(mBspApicId == GetApicId ());
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//
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// Place AP into the safe code, count down the number with lock mechanism in the safe code.
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// Skip initialization if mAcpiCpuData is not valid
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//
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TopOfStack = (UINTN)Stack + sizeof (Stack);
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TopOfStack &= ~(UINTN)(CPU_STACK_ALIGNMENT - 1);
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CopyMem ((VOID *)(UINTN)mApHltLoopCode, mApHltLoopCodeTemplate, sizeof (mApHltLoopCodeTemplate));
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TransferApToSafeState ((UINTN)mApHltLoopCode, TopOfStack, (UINTN)&mNumberToFinish);
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if (mAcpiCpuData.NumberOfCpus > 0) {
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//
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// First time microcode load and restore MTRRs
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//
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InitializeCpuBeforeRebase (IsBsp);
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}
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if (IsBsp) {
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DEBUG ((DEBUG_INFO, "SmmRestoreCpu: mSmmRelocated is %d\n", mSmmRelocated));
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//
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// Check whether Smm Relocation is done or not.
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// If not, will do the SmmBases Relocation here!!!
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//
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if (!mSmmRelocated) {
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//
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// Restore SMBASE for BSP and all APs
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//
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SmmRelocateBases ();
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} else {
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//
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// Issue SMI IPI (All Excluding Self SMM IPI + BSP SMM IPI) to execute first SMI init.
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//
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ExecuteFirstSmiInit ();
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}
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}
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//
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// Skip initialization if mAcpiCpuData is not valid
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//
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if (mAcpiCpuData.NumberOfCpus > 0) {
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if (IsBsp) {
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//
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// mNumberToFinish should be set before AP executes InitializeCpuAfterRebase()
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//
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mNumberToFinish = (UINT32)(mNumberOfCpus - 1);
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//
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// Signal that SMM base relocation is complete and to continue initialization for all APs.
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//
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mInitApsAfterSmmBaseReloc = TRUE;
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} else {
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//
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// AP Wait for BSP to signal SMM Base relocation done.
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//
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while (!mInitApsAfterSmmBaseReloc) {
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CpuPause ();
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}
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}
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//
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// Restore MSRs for BSP and all APs
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//
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InitializeCpuAfterRebase (IsBsp);
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}
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}
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/**
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@ -627,91 +732,7 @@ PrepareApStartupVector (
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mExchangeInfo->BufferStart = (UINT32)StartupVector;
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mExchangeInfo->Cr3 = (UINT32)(AsmReadCr3 ());
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mExchangeInfo->InitializeFloatingPointUnitsAddress = (UINTN)InitializeFloatingPointUnits;
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}
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/**
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The function is invoked before SMBASE relocation in S3 path to restores CPU status.
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The function is invoked before SMBASE relocation in S3 path. It does first time microcode load
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and restores MTRRs for both BSP and APs.
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**/
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VOID
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InitializeCpuBeforeRebase (
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VOID
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)
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{
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LoadMtrrData (mAcpiCpuData.MtrrTable);
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SetRegister (TRUE);
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ProgramVirtualWireMode ();
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PrepareApStartupVector (mAcpiCpuData.StartupVector);
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if (FeaturePcdGet (PcdCpuHotPlugSupport)) {
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ASSERT (mNumberOfCpus <= mAcpiCpuData.NumberOfCpus);
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} else {
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ASSERT (mNumberOfCpus == mAcpiCpuData.NumberOfCpus);
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}
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mNumberToFinish = (UINT32)(mNumberOfCpus - 1);
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mExchangeInfo->ApFunction = (VOID *)(UINTN)InitializeAp;
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//
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// Execute code for before SmmBaseReloc. Note: This flag is maintained across S3 boots.
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//
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mInitApsAfterSmmBaseReloc = FALSE;
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//
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// Send INIT IPI - SIPI to all APs
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//
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SendInitSipiSipiAllExcludingSelf ((UINT32)mAcpiCpuData.StartupVector);
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while (mNumberToFinish > 0) {
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CpuPause ();
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}
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}
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/**
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The function is invoked after SMBASE relocation in S3 path to restores CPU status.
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The function is invoked after SMBASE relocation in S3 path. It restores configuration according to
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data saved by normal boot path for both BSP and APs.
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**/
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VOID
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InitializeCpuAfterRebase (
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VOID
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)
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{
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if (FeaturePcdGet (PcdCpuHotPlugSupport)) {
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ASSERT (mNumberOfCpus <= mAcpiCpuData.NumberOfCpus);
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} else {
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ASSERT (mNumberOfCpus == mAcpiCpuData.NumberOfCpus);
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}
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mNumberToFinish = (UINT32)(mNumberOfCpus - 1);
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//
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// Signal that SMM base relocation is complete and to continue initialization for all APs.
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//
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mInitApsAfterSmmBaseReloc = TRUE;
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//
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// Must begin set register after all APs have continue their initialization.
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// This is a requirement to support semaphore mechanism in register table.
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// Because if semaphore's dependence type is package type, semaphore will wait
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// for all Aps in one package finishing their tasks before set next register
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// for all APs. If the Aps not begin its task during BSP doing its task, the
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// BSP thread will hang because it is waiting for other Aps in the same
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// package finishing their task.
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//
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SetRegister (FALSE);
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while (mNumberToFinish > 0) {
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CpuPause ();
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}
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mExchangeInfo->ApFunction = (VOID *)(UINTN)InitializeCpuProcedure;
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}
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/**
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@ -813,43 +834,32 @@ SmmRestoreCpu (
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InitializeDebugAgent (DEBUG_AGENT_INIT_THUNK_PEI_IA32TOX64, (VOID *)&Ia32Idtr, NULL);
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}
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mBspApicId = GetApicId ();
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//
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// Skip initialization if mAcpiCpuData is not valid
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// Skip AP initialization if mAcpiCpuData is not valid
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//
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if (mAcpiCpuData.NumberOfCpus > 0) {
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if (FeaturePcdGet (PcdCpuHotPlugSupport)) {
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ASSERT (mNumberOfCpus <= mAcpiCpuData.NumberOfCpus);
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} else {
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ASSERT (mNumberOfCpus == mAcpiCpuData.NumberOfCpus);
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}
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mNumberToFinish = (UINT32)mNumberOfCpus;
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//
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// First time microcode load and restore MTRRs
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// Execute code for before SmmBaseReloc. Note: This flag is maintained across S3 boots.
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//
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InitializeCpuBeforeRebase ();
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mInitApsAfterSmmBaseReloc = FALSE;
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PrepareApStartupVector (mAcpiCpuData.StartupVector);
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//
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// Send INIT IPI - SIPI to all APs
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//
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SendInitSipiSipiAllExcludingSelf ((UINT32)mAcpiCpuData.StartupVector);
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}
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DEBUG ((DEBUG_INFO, "SmmRestoreCpu: mSmmRelocated is %d\n", mSmmRelocated));
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//
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// Check whether Smm Relocation is done or not.
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// If not, will do the SmmBases Relocation here!!!
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//
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if (!mSmmRelocated) {
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//
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// Restore SMBASE for BSP and all APs
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//
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SmmRelocateBases ();
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} else {
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//
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// Issue SMI IPI (All Excluding Self SMM IPI + BSP SMM IPI) to execute first SMI init.
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//
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ExecuteFirstSmiInit ();
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}
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//
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// Skip initialization if mAcpiCpuData is not valid
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//
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if (mAcpiCpuData.NumberOfCpus > 0) {
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//
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// Restore MSRs for BSP and all APs
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//
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InitializeCpuAfterRebase ();
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}
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InitializeCpuProcedure (NULL);
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//
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// Set a flag to restore SMM configuration in S3 path.
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