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ArmPkg BeagleBoardPkg Omap35xxPkg: fix typo 'ArmDataSyncronizationBarrier' 

Replace all instances of ArmDataSyncronizationBarrier with
ArmDataSynchronizationBarrier.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Acked-by: Mark Rutland <mark.rutland@arm.com>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>

git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@18751 6f19259b-4bc3-4df7-8a09-765794883524
This commit is contained in:
Ard Biesheuvel 2015-11-09 13:25:50 +00:00 committed by abiesheuvel
parent 417165735e
commit cf93a37859
7 changed files with 13 additions and 13 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
ArmPkg/Include/Library/ArmLib.h
View File

@ -483,7 +483,7 @@ ArmDataMemoryBarrier (
VOID
EFIAPI
ArmDataSyncronizationBarrier (
ArmDataSynchronizationBarrier (
VOID
);

4
ArmPkg/Library/ArmLib/AArch64/AArch64Support.S
View File

@ -42,7 +42,7 @@ GCC_ASM_EXPORT (ArmDisableBranchPrediction)
GCC_ASM_EXPORT (AArch64AllDataCachesOperation)
GCC_ASM_EXPORT (AArch64PerformPoUDataCacheOperation)
GCC_ASM_EXPORT (ArmDataMemoryBarrier)
GCC_ASM_EXPORT (ArmDataSyncronizationBarrier)
GCC_ASM_EXPORT (ArmDataSynchronizationBarrier)
GCC_ASM_EXPORT (ArmInstructionSynchronizationBarrier)
GCC_ASM_EXPORT (ArmWriteVBar)
GCC_ASM_EXPORT (ArmReadVBar)
@ -389,7 +389,7 @@ ASM_PFX(ArmDataMemoryBarrier):
ret
ASM_PFX(ArmDataSyncronizationBarrier):
ASM_PFX(ArmDataSynchronizationBarrier):
ASM_PFX(ArmDrainWriteBuffer):
dsb sy
ret

4
ArmPkg/Library/ArmLib/ArmV7/ArmV7Support.S
View File

@ -40,7 +40,7 @@ GCC_ASM_EXPORT (ArmSetHighVectors)
GCC_ASM_EXPORT (ArmV7AllDataCachesOperation)
GCC_ASM_EXPORT (ArmV7PerformPoUDataCacheOperation)
GCC_ASM_EXPORT (ArmDataMemoryBarrier)
GCC_ASM_EXPORT (ArmDataSyncronizationBarrier)
GCC_ASM_EXPORT (ArmDataSynchronizationBarrier)
GCC_ASM_EXPORT (ArmInstructionSynchronizationBarrier)
GCC_ASM_EXPORT (ArmReadVBar)
GCC_ASM_EXPORT (ArmWriteVBar)
@ -321,7 +321,7 @@ ASM_PFX(ArmDataMemoryBarrier):
dmb
bx LR
ASM_PFX(ArmDataSyncronizationBarrier):
ASM_PFX(ArmDataSynchronizationBarrier):
ASM_PFX(ArmDrainWriteBuffer):
dsb
bx LR

4
ArmPkg/Library/ArmLib/ArmV7/ArmV7Support.asm
View File

@ -37,7 +37,7 @@
EXPORT ArmV7AllDataCachesOperation
EXPORT ArmV7PerformPoUDataCacheOperation
EXPORT ArmDataMemoryBarrier
EXPORT ArmDataSyncronizationBarrier
EXPORT ArmDataSynchronizationBarrier
EXPORT ArmInstructionSynchronizationBarrier
EXPORT ArmReadVBar
EXPORT ArmWriteVBar
@ -315,7 +315,7 @@ ArmDataMemoryBarrier
dmb
bx LR
ArmDataSyncronizationBarrier
ArmDataSynchronizationBarrier
ArmDrainWriteBuffer
dsb
bx LR

4
BeagleBoardPkg/Library/BeagleBoardLib/BeagleBoard.c
View File

@ -92,11 +92,11 @@ ArmPlatformInitialize (
// Turn off the functional clock for Timer 3
MmioAnd32 (CM_FCLKEN_PER, 0xFFFFFFFF ^ CM_ICLKEN_PER_EN_GPT3_ENABLE );
ArmDataSyncronizationBarrier ();
ArmDataSynchronizationBarrier ();
// Clear IRQs
MmioWrite32 (INTCPS_CONTROL, INTCPS_CONTROL_NEWIRQAGR);
ArmDataSyncronizationBarrier ();
ArmDataSynchronizationBarrier ();
return RETURN_SUCCESS;
}

6
Omap35xxPkg/InterruptDxe/HardwareInterrupt.c
View File

@ -237,7 +237,7 @@ EndOfInterrupt (
)
{
MmioWrite32 (INTCPS_CONTROL, INTCPS_CONTROL_NEWIRQAGR);
ArmDataSyncronizationBarrier ();
ArmDataSynchronizationBarrier ();
return EFI_SUCCESS;
}
@ -267,7 +267,7 @@ IrqInterruptHandler (
// Needed to prevent infinite nesting when Time Driver lowers TPL
MmioWrite32 (INTCPS_CONTROL, INTCPS_CONTROL_NEWIRQAGR);
ArmDataSyncronizationBarrier ();
ArmDataSynchronizationBarrier ();
InterruptHandler = gRegisteredInterruptHandlers[Vector];
if (InterruptHandler != NULL) {
@ -277,7 +277,7 @@ IrqInterruptHandler (
// Needed to clear after running the handler
MmioWrite32 (INTCPS_CONTROL, INTCPS_CONTROL_NEWIRQAGR);
ArmDataSyncronizationBarrier ();
ArmDataSynchronizationBarrier ();
}
//

2
Omap35xxPkg/Library/DebugAgentTimerLib/DebugAgentTimerLib.c
View File

@ -159,7 +159,7 @@ DebugAgentTimerEndOfInterrupt (
while ((MmioRead32 (gTISR) & TISR_ALL_INTERRUPT_MASK) != TISR_NO_INTERRUPTS_PENDING);
MmioWrite32 (INTCPS_CONTROL, INTCPS_CONTROL_NEWFIQAGR);
ArmDataSyncronizationBarrier ();
ArmDataSynchronizationBarrier ();
}