mirror of https://github.com/acidanthera/audk.git
OvmfPkg: PlatformPei: beautify memory HOB order in QemuInitializeRam()
Build the memory HOBs in a tight block, in increasing base address order. Cc: Maoming <maoming.maoming@huawei.com> Cc: Huangpeng (Peter) <peter.huangpeng@huawei.com> Cc: Wei Liu <wei.liu2@citrix.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Laszlo Ersek <lersek@redhat.com> Tested-by: Maoming <maoming.maoming@huawei.com> Reviewed-by: Jordan Justen <jordan.l.justen@intel.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@17721 6f19259b-4bc3-4df7-8a09-765794883524
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@ -265,8 +265,11 @@ QemuInitializeRam (
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//
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// Create memory HOBs
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//
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AddMemoryRangeHob (BASE_1MB, LowerMemorySize);
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AddMemoryRangeHob (0, BASE_512KB + BASE_128KB);
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AddMemoryRangeHob (BASE_1MB, LowerMemorySize);
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if (UpperMemorySize != 0) {
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AddUntestedMemoryBaseSizeHob (BASE_4GB, UpperMemorySize);
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}
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}
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MtrrSetMemoryAttribute (BASE_1MB, LowerMemorySize - BASE_1MB, CacheWriteBack);
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@ -274,10 +277,6 @@ QemuInitializeRam (
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MtrrSetMemoryAttribute (0, BASE_512KB + BASE_128KB, CacheWriteBack);
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if (UpperMemorySize != 0) {
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if (mBootMode != BOOT_ON_S3_RESUME) {
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AddUntestedMemoryBaseSizeHob (BASE_4GB, UpperMemorySize);
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}
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MtrrSetMemoryAttribute (BASE_4GB, UpperMemorySize, CacheWriteBack);
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}
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}
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