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OvmfPkg: PlatformPei: beautify memory HOB order in QemuInitializeRam() 

Build the memory HOBs in a tight block, in increasing base address order.

Cc: Maoming <maoming.maoming@huawei.com>
Cc: Huangpeng (Peter) <peter.huangpeng@huawei.com>
Cc: Wei Liu <wei.liu2@citrix.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Laszlo Ersek <lersek@redhat.com>
Tested-by: Maoming <maoming.maoming@huawei.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>

git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@17721 6f19259b-4bc3-4df7-8a09-765794883524
This commit is contained in:
Laszlo Ersek 2015-06-26 16:09:48 +00:00 committed by lersek
parent 86a14b0a7b
commit cfc80e2e95
1 changed files with 4 additions and 5 deletions
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9
OvmfPkg/PlatformPei/MemDetect.c
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@ -265,8 +265,11 @@ QemuInitializeRam (
// //
// Create memory HOBs // Create memory HOBs
// //
AddMemoryRangeHob (BASE_1MB, LowerMemorySize);
AddMemoryRangeHob (0, BASE_512KB + BASE_128KB); AddMemoryRangeHob (0, BASE_512KB + BASE_128KB);
AddMemoryRangeHob (BASE_1MB, LowerMemorySize);
if (UpperMemorySize != 0) {
AddUntestedMemoryBaseSizeHob (BASE_4GB, UpperMemorySize);
}
} }
MtrrSetMemoryAttribute (BASE_1MB, LowerMemorySize - BASE_1MB, CacheWriteBack); MtrrSetMemoryAttribute (BASE_1MB, LowerMemorySize - BASE_1MB, CacheWriteBack);
@ -274,10 +277,6 @@ QemuInitializeRam (
MtrrSetMemoryAttribute (0, BASE_512KB + BASE_128KB, CacheWriteBack); MtrrSetMemoryAttribute (0, BASE_512KB + BASE_128KB, CacheWriteBack);
if (UpperMemorySize != 0) { if (UpperMemorySize != 0) {
if (mBootMode != BOOT_ON_S3_RESUME) {
AddUntestedMemoryBaseSizeHob (BASE_4GB, UpperMemorySize);
}
MtrrSetMemoryAttribute (BASE_4GB, UpperMemorySize, CacheWriteBack); MtrrSetMemoryAttribute (BASE_4GB, UpperMemorySize, CacheWriteBack);
} }
} }