ArmPkg: remove ArmCpuLib header and implementations

Remove ArmCpuLib entirely. It is no longer used.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Laszlo Ersek <lersek@redhat.com>
This commit is contained in:
Ard Biesheuvel 2017-03-31 09:45:35 +01:00
parent cb811673c7
commit cffa7925a2
15 changed files with 0 additions and 592 deletions

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@ -151,12 +151,5 @@
ArmPkg/Library/PeiServicesTablePointerLib/PeiServicesTablePointerLib.inf ArmPkg/Library/PeiServicesTablePointerLib/PeiServicesTablePointerLib.inf
ArmPkg/Library/PlatformBootManagerLib/PlatformBootManagerLib.inf ArmPkg/Library/PlatformBootManagerLib/PlatformBootManagerLib.inf
[Components.ARM]
ArmPkg/Drivers/ArmCpuLib/ArmCortexA8Lib/ArmCortexA8Lib.inf
ArmPkg/Drivers/ArmCpuLib/ArmCortexA9Lib/ArmCortexA9Lib.inf
ArmPkg/Drivers/ArmCpuLib/ArmCortexA15Lib/ArmCortexA15Lib.inf
[Components.AARCH64] [Components.AARCH64]
ArmPkg/Drivers/ArmCpuLib/ArmCortexAEMv8Lib/ArmCortexAEMv8Lib.inf
ArmPkg/Drivers/ArmCpuLib/ArmCortexA5xLib/ArmCortexA5xLib.inf
ArmPkg/Library/ArmMmuLib/ArmMmuPeiLib.inf ArmPkg/Library/ArmMmuLib/ArmMmuPeiLib.inf

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@ -1,67 +0,0 @@
/** @file
Copyright (c) 2011-2012, ARM Limited. All rights reserved.
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
**/
#include <Base.h>
#include <Library/ArmLib.h>
#include <Library/ArmCpuLib.h>
#include <Library/ArmGenericTimerCounterLib.h>
#include <Library/DebugLib.h>
#include <Library/PcdLib.h>
#include <Chipset/ArmV7.h>
#define A15_FEATURE_SMP (1<<6)
VOID
ArmCpuSetup (
IN UINTN MpId
)
{
// Check if Architectural Timer frequency is valid number (should not be 0)
ASSERT (PcdGet32 (PcdArmArchTimerFreqInHz));
ASSERT(ArmIsArchTimerImplemented () != 0);
// Enable SWP instructions
ArmEnableSWPInstruction ();
// Enable program flow prediction, if supported.
ArmEnableBranchPrediction ();
// Note: System Counter frequency can only be set in Secure privileged mode,
// if security extensions are implemented.
ArmGenericTimerSetTimerFreq (PcdGet32 (PcdArmArchTimerFreqInHz));
if (ArmIsMpCore()) {
// Turn on SMP coherency
ArmSetAuxCrBit (A15_FEATURE_SMP);
}
}
VOID
ArmCpuSetupSmpNonSecure (
IN UINTN MpId
)
{
/*// Make the SCU accessible in Non Secure world
if (ArmPlatformIsPrimaryCore (MpId)) {
ScuBase = ArmGetScuBaseAddress();
// Allow NS access to SCU register
MmioOr32 (ScuBase + A9_SCU_SACR_OFFSET, 0xf);
// Allow NS access to Private Peripherals
MmioOr32 (ScuBase + A9_SCU_SSACR_OFFSET, 0xfff);
}*/
}

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@ -1,35 +0,0 @@
#/* @file
# Copyright (c) 2011-2014, ARM Limited. All rights reserved.
#
# This program and the accompanying materials
# are licensed and made available under the terms and conditions of the BSD License
# which accompanies this distribution. The full text of the license may be found at
# http://opensource.org/licenses/bsd-license.php
#
# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
#
#*/
[Defines]
INF_VERSION = 0x00010005
BASE_NAME = ArmCortexA15Lib
FILE_GUID = 501b1c8f-21d5-4ef5-a565-435b7f0aae2d
MODULE_TYPE = BASE
VERSION_STRING = 1.0
LIBRARY_CLASS = ArmCpuLib
[Packages]
MdePkg/MdePkg.dec
ArmPkg/ArmPkg.dec
[LibraryClasses]
ArmLib
ArmGenericTimerCounterLib
PcdLib
[Sources.common]
ArmCortexA15Lib.c
[FixedPcd]
gArmTokenSpaceGuid.PcdArmArchTimerFreqInHz

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@ -1,27 +0,0 @@
#------------------------------------------------------------------------------
#
# Copyright (c) 2013 - 2014, ARM Limited. All rights reserved.
#
# This program and the accompanying materials
# are licensed and made available under the terms and conditions of the BSD License
# which accompanies this distribution. The full text of the license may be found at
# http://opensource.org/licenses/bsd-license.php
#
# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
#
#------------------------------------------------------------------------------
#include <AsmMacroIoLibV8.h>
ASM_FUNC(ArmReadCpuExCr)
mrs x0, S3_1_c15_c2_1
ret
ASM_FUNC(ArmWriteCpuExCr)
msr S3_1_c15_c2_1, x0
dsb sy
isb
ret
ASM_FUNCTION_REMOVE_IF_UNREFERENCED

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@ -1,84 +0,0 @@
/** @file
Copyright (c) 2011-2014, ARM Limited. All rights reserved.
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
**/
#include <Base.h>
#include <Library/ArmLib.h>
#include <Library/ArmCpuLib.h>
#include <Library/ArmGenericTimerCounterLib.h>
#include <Library/DebugLib.h>
#include <Library/PcdLib.h>
#include <Chipset/ArmCortexA5x.h>
VOID
ArmCpuSetup (
IN UINTN MpId
)
{
// Check if Architectural Timer frequency is valid number (should not be 0)
ASSERT (PcdGet32 (PcdArmArchTimerFreqInHz));
ASSERT (ArmIsArchTimerImplemented () != 0);
// Note: System Counter frequency can only be set in Secure privileged mode,
// if security extensions are implemented.
ArmGenericTimerSetTimerFreq (PcdGet32 (PcdArmArchTimerFreqInHz));
if (ArmIsMpCore ()) {
// Turn on SMP coherency
ArmSetCpuExCrBit (A5X_FEATURE_SMP);
}
//
// If CPU is CortexA57 r0p0 apply Errata workarounds
//
if ((ArmReadMidr () & ((ARM_CPU_TYPE_MASK << 4) | ARM_CPU_REV_MASK)) ==
((ARM_CPU_TYPE_A57 << 4) | ARM_CPU_REV(0,0))) {
// Errata 806969: DisableLoadStoreWB (1ULL << 49)
// Errata 813420: Execute Data Cache clean as Data Cache clean/invalidate (1ULL << 44)
// Errata 814670: disable DMB nullification (1ULL << 58)
ArmSetCpuActlrBit ( (1ULL << 49) | (1ULL << 44) | (1ULL << 58) );
}
}
VOID
ArmCpuSetupSmpNonSecure (
IN UINTN MpId
)
{
}
VOID
EFIAPI
ArmSetCpuExCrBit (
IN UINT64 Bits
)
{
UINT64 Value;
Value = ArmReadCpuExCr ();
Value |= Bits;
ArmWriteCpuExCr (Value);
}
VOID
EFIAPI
ArmUnsetCpuExCrBit (
IN UINT64 Bits
)
{
UINT64 Value;
Value = ArmReadCpuExCr ();
Value &= ~Bits;
ArmWriteCpuExCr (Value);
}

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@ -1,38 +0,0 @@
#/* @file
# Copyright (c) 2011-2014, ARM Limited. All rights reserved.
#
# This program and the accompanying materials
# are licensed and made available under the terms and conditions of the BSD License
# which accompanies this distribution. The full text of the license may be found at
# http://opensource.org/licenses/bsd-license.php
#
# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
#
#*/
[Defines]
INF_VERSION = 0x00010005
BASE_NAME = ArmCortexA5xLib
FILE_GUID = 08107938-85d8-4967-ba65-b673f708fcb2
MODULE_TYPE = BASE
VERSION_STRING = 1.0
LIBRARY_CLASS = ArmCpuLib
[Packages]
MdePkg/MdePkg.dec
ArmPkg/ArmPkg.dec
[LibraryClasses]
ArmLib
ArmGenericTimerCounterLib
PcdLib
[Sources.common]
ArmCortexA5xLib.c
[Sources.AARCH64]
AArch64/ArmCortexA5xHelper.S | GCC
[FixedPcd]
gArmTokenSpaceGuid.PcdArmArchTimerFreqInHz

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@ -1,41 +0,0 @@
/** @file
Copyright (c) 2011, ARM Limited. All rights reserved.
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
**/
#include <Base.h>
#include <Library/ArmLib.h>
#include <Library/ArmCpuLib.h>
#include <Library/DebugLib.h>
#include <Chipset/ArmV7.h>
VOID
ArmCpuSetup (
IN UINTN MpId
)
{
// Enable SWP instructions
ArmEnableSWPInstruction ();
// Enable program flow prediction, if supported.
ArmEnableBranchPrediction ();
}
VOID
ArmCpuSetupSmpNonSecure (
IN UINTN MpId
)
{
// The CortexA8 is a Unicore CPU. We must not initialize SMP for Non Secure Accesses
ASSERT(0);
}

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@ -1,27 +0,0 @@
#/* @file
# Copyright (c) 2011, ARM Limited. All rights reserved.
#
# This program and the accompanying materials
# are licensed and made available under the terms and conditions of the BSD License
# which accompanies this distribution. The full text of the license may be found at
# http://opensource.org/licenses/bsd-license.php
#
# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
#
#*/
[Defines]
INF_VERSION = 0x00010005
BASE_NAME = ArmCortexA8Lib
FILE_GUID = 34b5745e-f575-44ce-ba2e-df0886807c16
MODULE_TYPE = BASE
VERSION_STRING = 1.0
LIBRARY_CLASS = ArmCpuLib
[Packages]
MdePkg/MdePkg.dec
ArmPkg/ArmPkg.dec
[Sources.common]
ArmCortexA8Lib.c

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@ -1,23 +0,0 @@
//
// Copyright (c) 2011-2012, ARM Limited. All rights reserved.
//
// This program and the accompanying materials
// are licensed and made available under the terms and conditions of the BSD License
// which accompanies this distribution. The full text of the license may be found at
// http://opensource.org/licenses/bsd-license.php
//
// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
//
//
#include <AsmMacroIoLib.h>
// IN None
// OUT r0 = SCU Base Address
ASM_FUNC(ArmGetScuBaseAddress)
// Read Configuration Base Address Register. ArmCBar cannot be called to get
// the Configuration BAR as a stack is not necessary setup. The SCU is at the
// offset 0x0000 from the Private Memory Region.
mrc p15, 4, r0, c15, c0, 0
bx lr

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@ -1,29 +0,0 @@
//
// Copyright (c) 2011-2012, ARM Limited. All rights reserved.
//
// This program and the accompanying materials
// are licensed and made available under the terms and conditions of the BSD License
// which accompanies this distribution. The full text of the license may be found at
// http://opensource.org/licenses/bsd-license.php
//
// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
//
//
INCLUDE AsmMacroExport.inc
INCLUDE AsmMacroIoLib.inc
PRESERVE8
// IN None
// OUT r0 = SCU Base Address
RVCT_ASM_EXPORT ArmGetScuBaseAddress
// Read Configuration Base Address Register. ArmCBar cannot be called to get
// the Configuration BAR as a stack is not necessary setup. The SCU is at the
// offset 0x0000 from the Private Memory Region.
mrc p15, 4, r0, c15, c0, 0
bx lr
END

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@ -1,76 +0,0 @@
/** @file
Copyright (c) 2011-2012, ARM Limited. All rights reserved.
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
**/
#include <Base.h>
#include <Library/ArmLib.h>
#include <Library/ArmCpuLib.h>
#include <Library/ArmPlatformLib.h>
#include <Library/IoLib.h>
#include <Library/PcdLib.h>
#include <Chipset/ArmCortexA9.h>
VOID
ArmEnableScu (
VOID
)
{
INTN ScuBase;
ScuBase = ArmGetScuBaseAddress();
// Invalidate all: write -1 to SCU Invalidate All register
MmioWrite32(ScuBase + A9_SCU_INVALL_OFFSET, 0xffffffff);
// Enable SCU
MmioWrite32(ScuBase + A9_SCU_CONTROL_OFFSET, 0x1);
}
VOID
ArmCpuSetup (
IN UINTN MpId
)
{
// Enable SWP instructions
ArmEnableSWPInstruction ();
// Enable program flow prediction, if supported.
ArmEnableBranchPrediction ();
// If MPCore then Enable the SCU
if (ArmIsMpCore()) {
// Signals the Cortex-A9 processor is taking part in coherency
ArmSetAuxCrBit (A9_FEATURE_SMP);
ArmEnableScu ();
}
}
VOID
ArmCpuSetupSmpNonSecure (
IN UINTN MpId
)
{
INTN ScuBase;
// Make the SCU accessible in Non Secure world
if (ArmPlatformIsPrimaryCore (MpId)) {
ScuBase = ArmGetScuBaseAddress();
// Allow NS access to SCU register
MmioOr32 (ScuBase + A9_SCU_SACR_OFFSET, 0xf);
// Allow NS access to Private Peripherals
MmioOr32 (ScuBase + A9_SCU_SSACR_OFFSET, 0xfff);
}
}

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@ -1,37 +0,0 @@
#/* @file
# Copyright (c) 2011-2013, ARM Limited. All rights reserved.
#
# This program and the accompanying materials
# are licensed and made available under the terms and conditions of the BSD License
# which accompanies this distribution. The full text of the license may be found at
# http://opensource.org/licenses/bsd-license.php
#
# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
#
#*/
[Defines]
INF_VERSION = 0x00010005
BASE_NAME = ArmCortexA9Lib
FILE_GUID = c9709ea3-1beb-4806-889a-8a1d5e5e1697
MODULE_TYPE = BASE
VERSION_STRING = 1.0
LIBRARY_CLASS = ArmCpuLib
[Packages]
MdePkg/MdePkg.dec
ArmPkg/ArmPkg.dec
ArmPlatformPkg/ArmPlatformPkg.dec
[LibraryClasses]
ArmLib
ArmPlatformLib
IoLib
PcdLib
[Sources.common]
ArmCortexA9Lib.c
ArmCortexA9Helper.asm | RVCT
ArmCortexA9Helper.S | GCC

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@ -1,39 +0,0 @@
/** @file
Copyright (c) 2011 - 2013, ARM Limited. All rights reserved.
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
**/
#include <Base.h>
#include <Library/ArmCpuLib.h>
#include <Library/ArmGenericTimerCounterLib.h>
#include <Library/PcdLib.h>
#include <Chipset/AArch64.h>
VOID
ArmCpuSetup (
IN UINTN MpId
)
{
// Note: System Counter frequency can only be set in Secure privileged mode,
// if security extensions are implemented.
ArmGenericTimerSetTimerFreq (PcdGet32 (PcdArmArchTimerFreqInHz));
}
VOID
ArmCpuSetupSmpNonSecure (
IN UINTN MpId
)
{
// Nothing to do
}

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@ -1,34 +0,0 @@
#/* @file
# Copyright (c) 2011 - 2014, ARM Limited. All rights reserved.
#
# This program and the accompanying materials
# are licensed and made available under the terms and conditions of the BSD License
# which accompanies this distribution. The full text of the license may be found at
# http://opensource.org/licenses/bsd-license.php
#
# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
#
#*/
[Defines]
INF_VERSION = 0x00010005
BASE_NAME = ArmCortexAEMv8Lib
FILE_GUID = 8ab5a7e3-86b1-4dd3-a092-09ee801e774b
MODULE_TYPE = BASE
VERSION_STRING = 1.0
LIBRARY_CLASS = ArmCpuLib
[Packages]
MdePkg/MdePkg.dec
ArmPkg/ArmPkg.dec
[LibraryClasses]
ArmGenericTimerCounterLib
PcdLib
[Sources.common]
ArmCortexAEMv8Lib.c
[FixedPcd]
gArmTokenSpaceGuid.PcdArmArchTimerFreqInHz

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@ -1,28 +0,0 @@
/** @file
Copyright (c) 2011-2012, ARM Limited. All rights reserved.
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
**/
#ifndef __ARMCPU_LIB__
#define __ARMCPU_LIB__
VOID
ArmCpuSetup (
IN UINTN MpId
);
VOID
ArmCpuSetupSmpNonSecure (
IN UINTN MpId
);
#endif // __ARMCPU_LIB__