mirror of https://github.com/acidanthera/audk.git
ArmPkg: remove ArmCpuLib header and implementations
Remove ArmCpuLib entirely. It is no longer used. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Laszlo Ersek <lersek@redhat.com>
This commit is contained in:
parent
cb811673c7
commit
cffa7925a2
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@ -151,12 +151,5 @@
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ArmPkg/Library/PeiServicesTablePointerLib/PeiServicesTablePointerLib.inf
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ArmPkg/Library/PlatformBootManagerLib/PlatformBootManagerLib.inf
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[Components.ARM]
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ArmPkg/Drivers/ArmCpuLib/ArmCortexA8Lib/ArmCortexA8Lib.inf
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ArmPkg/Drivers/ArmCpuLib/ArmCortexA9Lib/ArmCortexA9Lib.inf
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ArmPkg/Drivers/ArmCpuLib/ArmCortexA15Lib/ArmCortexA15Lib.inf
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[Components.AARCH64]
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ArmPkg/Drivers/ArmCpuLib/ArmCortexAEMv8Lib/ArmCortexAEMv8Lib.inf
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ArmPkg/Drivers/ArmCpuLib/ArmCortexA5xLib/ArmCortexA5xLib.inf
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ArmPkg/Library/ArmMmuLib/ArmMmuPeiLib.inf
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@ -1,67 +0,0 @@
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/** @file
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Copyright (c) 2011-2012, ARM Limited. All rights reserved.
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This program and the accompanying materials
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are licensed and made available under the terms and conditions of the BSD License
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which accompanies this distribution. The full text of the license may be found at
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http://opensource.org/licenses/bsd-license.php
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THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
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WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
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**/
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#include <Base.h>
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#include <Library/ArmLib.h>
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#include <Library/ArmCpuLib.h>
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#include <Library/ArmGenericTimerCounterLib.h>
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#include <Library/DebugLib.h>
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#include <Library/PcdLib.h>
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#include <Chipset/ArmV7.h>
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#define A15_FEATURE_SMP (1<<6)
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VOID
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ArmCpuSetup (
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IN UINTN MpId
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)
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{
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// Check if Architectural Timer frequency is valid number (should not be 0)
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ASSERT (PcdGet32 (PcdArmArchTimerFreqInHz));
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ASSERT(ArmIsArchTimerImplemented () != 0);
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// Enable SWP instructions
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ArmEnableSWPInstruction ();
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// Enable program flow prediction, if supported.
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ArmEnableBranchPrediction ();
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// Note: System Counter frequency can only be set in Secure privileged mode,
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// if security extensions are implemented.
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ArmGenericTimerSetTimerFreq (PcdGet32 (PcdArmArchTimerFreqInHz));
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if (ArmIsMpCore()) {
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// Turn on SMP coherency
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ArmSetAuxCrBit (A15_FEATURE_SMP);
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}
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}
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VOID
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ArmCpuSetupSmpNonSecure (
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IN UINTN MpId
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)
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{
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/*// Make the SCU accessible in Non Secure world
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if (ArmPlatformIsPrimaryCore (MpId)) {
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ScuBase = ArmGetScuBaseAddress();
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// Allow NS access to SCU register
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MmioOr32 (ScuBase + A9_SCU_SACR_OFFSET, 0xf);
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// Allow NS access to Private Peripherals
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MmioOr32 (ScuBase + A9_SCU_SSACR_OFFSET, 0xfff);
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}*/
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}
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@ -1,35 +0,0 @@
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#/* @file
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# Copyright (c) 2011-2014, ARM Limited. All rights reserved.
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#
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# This program and the accompanying materials
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# are licensed and made available under the terms and conditions of the BSD License
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# which accompanies this distribution. The full text of the license may be found at
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# http://opensource.org/licenses/bsd-license.php
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#
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# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
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# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
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#
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#*/
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[Defines]
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INF_VERSION = 0x00010005
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BASE_NAME = ArmCortexA15Lib
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FILE_GUID = 501b1c8f-21d5-4ef5-a565-435b7f0aae2d
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MODULE_TYPE = BASE
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VERSION_STRING = 1.0
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LIBRARY_CLASS = ArmCpuLib
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[Packages]
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MdePkg/MdePkg.dec
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ArmPkg/ArmPkg.dec
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[LibraryClasses]
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ArmLib
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ArmGenericTimerCounterLib
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PcdLib
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[Sources.common]
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ArmCortexA15Lib.c
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[FixedPcd]
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gArmTokenSpaceGuid.PcdArmArchTimerFreqInHz
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@ -1,27 +0,0 @@
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#------------------------------------------------------------------------------
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#
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# Copyright (c) 2013 - 2014, ARM Limited. All rights reserved.
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#
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# This program and the accompanying materials
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# are licensed and made available under the terms and conditions of the BSD License
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# which accompanies this distribution. The full text of the license may be found at
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# http://opensource.org/licenses/bsd-license.php
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#
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# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
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# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
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#
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#------------------------------------------------------------------------------
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#include <AsmMacroIoLibV8.h>
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ASM_FUNC(ArmReadCpuExCr)
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mrs x0, S3_1_c15_c2_1
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ret
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ASM_FUNC(ArmWriteCpuExCr)
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msr S3_1_c15_c2_1, x0
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dsb sy
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isb
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ret
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ASM_FUNCTION_REMOVE_IF_UNREFERENCED
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@ -1,84 +0,0 @@
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/** @file
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Copyright (c) 2011-2014, ARM Limited. All rights reserved.
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This program and the accompanying materials
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are licensed and made available under the terms and conditions of the BSD License
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which accompanies this distribution. The full text of the license may be found at
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http://opensource.org/licenses/bsd-license.php
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THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
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WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
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**/
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#include <Base.h>
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#include <Library/ArmLib.h>
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#include <Library/ArmCpuLib.h>
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#include <Library/ArmGenericTimerCounterLib.h>
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#include <Library/DebugLib.h>
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#include <Library/PcdLib.h>
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#include <Chipset/ArmCortexA5x.h>
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VOID
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ArmCpuSetup (
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IN UINTN MpId
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)
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{
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// Check if Architectural Timer frequency is valid number (should not be 0)
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ASSERT (PcdGet32 (PcdArmArchTimerFreqInHz));
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ASSERT (ArmIsArchTimerImplemented () != 0);
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// Note: System Counter frequency can only be set in Secure privileged mode,
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// if security extensions are implemented.
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ArmGenericTimerSetTimerFreq (PcdGet32 (PcdArmArchTimerFreqInHz));
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if (ArmIsMpCore ()) {
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// Turn on SMP coherency
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ArmSetCpuExCrBit (A5X_FEATURE_SMP);
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}
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//
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// If CPU is CortexA57 r0p0 apply Errata workarounds
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//
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if ((ArmReadMidr () & ((ARM_CPU_TYPE_MASK << 4) | ARM_CPU_REV_MASK)) ==
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((ARM_CPU_TYPE_A57 << 4) | ARM_CPU_REV(0,0))) {
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// Errata 806969: DisableLoadStoreWB (1ULL << 49)
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// Errata 813420: Execute Data Cache clean as Data Cache clean/invalidate (1ULL << 44)
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// Errata 814670: disable DMB nullification (1ULL << 58)
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ArmSetCpuActlrBit ( (1ULL << 49) | (1ULL << 44) | (1ULL << 58) );
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}
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}
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VOID
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ArmCpuSetupSmpNonSecure (
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IN UINTN MpId
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)
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{
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}
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VOID
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EFIAPI
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ArmSetCpuExCrBit (
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IN UINT64 Bits
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)
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{
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UINT64 Value;
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Value = ArmReadCpuExCr ();
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Value |= Bits;
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ArmWriteCpuExCr (Value);
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}
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VOID
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EFIAPI
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ArmUnsetCpuExCrBit (
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IN UINT64 Bits
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)
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{
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UINT64 Value;
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Value = ArmReadCpuExCr ();
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Value &= ~Bits;
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ArmWriteCpuExCr (Value);
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}
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@ -1,38 +0,0 @@
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#/* @file
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# Copyright (c) 2011-2014, ARM Limited. All rights reserved.
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#
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# This program and the accompanying materials
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# are licensed and made available under the terms and conditions of the BSD License
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# which accompanies this distribution. The full text of the license may be found at
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# http://opensource.org/licenses/bsd-license.php
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#
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# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
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# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
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#
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#*/
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[Defines]
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INF_VERSION = 0x00010005
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BASE_NAME = ArmCortexA5xLib
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FILE_GUID = 08107938-85d8-4967-ba65-b673f708fcb2
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MODULE_TYPE = BASE
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VERSION_STRING = 1.0
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LIBRARY_CLASS = ArmCpuLib
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[Packages]
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MdePkg/MdePkg.dec
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ArmPkg/ArmPkg.dec
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[LibraryClasses]
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ArmLib
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ArmGenericTimerCounterLib
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PcdLib
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[Sources.common]
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ArmCortexA5xLib.c
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[Sources.AARCH64]
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AArch64/ArmCortexA5xHelper.S | GCC
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[FixedPcd]
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gArmTokenSpaceGuid.PcdArmArchTimerFreqInHz
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@ -1,41 +0,0 @@
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/** @file
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Copyright (c) 2011, ARM Limited. All rights reserved.
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This program and the accompanying materials
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are licensed and made available under the terms and conditions of the BSD License
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which accompanies this distribution. The full text of the license may be found at
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http://opensource.org/licenses/bsd-license.php
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THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
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WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
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**/
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#include <Base.h>
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#include <Library/ArmLib.h>
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#include <Library/ArmCpuLib.h>
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#include <Library/DebugLib.h>
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#include <Chipset/ArmV7.h>
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VOID
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ArmCpuSetup (
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IN UINTN MpId
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)
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{
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// Enable SWP instructions
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ArmEnableSWPInstruction ();
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// Enable program flow prediction, if supported.
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ArmEnableBranchPrediction ();
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}
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VOID
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ArmCpuSetupSmpNonSecure (
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IN UINTN MpId
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)
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{
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// The CortexA8 is a Unicore CPU. We must not initialize SMP for Non Secure Accesses
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ASSERT(0);
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}
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@ -1,27 +0,0 @@
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#/* @file
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# Copyright (c) 2011, ARM Limited. All rights reserved.
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#
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# This program and the accompanying materials
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# are licensed and made available under the terms and conditions of the BSD License
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# which accompanies this distribution. The full text of the license may be found at
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# http://opensource.org/licenses/bsd-license.php
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#
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# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
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# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
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#
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#*/
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[Defines]
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INF_VERSION = 0x00010005
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BASE_NAME = ArmCortexA8Lib
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FILE_GUID = 34b5745e-f575-44ce-ba2e-df0886807c16
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MODULE_TYPE = BASE
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VERSION_STRING = 1.0
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LIBRARY_CLASS = ArmCpuLib
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[Packages]
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MdePkg/MdePkg.dec
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ArmPkg/ArmPkg.dec
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[Sources.common]
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ArmCortexA8Lib.c
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@ -1,23 +0,0 @@
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//
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// Copyright (c) 2011-2012, ARM Limited. All rights reserved.
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//
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// This program and the accompanying materials
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// are licensed and made available under the terms and conditions of the BSD License
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// which accompanies this distribution. The full text of the license may be found at
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// http://opensource.org/licenses/bsd-license.php
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//
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// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
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// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
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//
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//
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#include <AsmMacroIoLib.h>
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// IN None
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// OUT r0 = SCU Base Address
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ASM_FUNC(ArmGetScuBaseAddress)
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// Read Configuration Base Address Register. ArmCBar cannot be called to get
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// the Configuration BAR as a stack is not necessary setup. The SCU is at the
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// offset 0x0000 from the Private Memory Region.
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mrc p15, 4, r0, c15, c0, 0
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bx lr
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@ -1,29 +0,0 @@
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//
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// Copyright (c) 2011-2012, ARM Limited. All rights reserved.
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//
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// This program and the accompanying materials
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// are licensed and made available under the terms and conditions of the BSD License
|
||||
// which accompanies this distribution. The full text of the license may be found at
|
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// http://opensource.org/licenses/bsd-license.php
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//
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// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
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// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
|
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//
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//
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INCLUDE AsmMacroExport.inc
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INCLUDE AsmMacroIoLib.inc
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PRESERVE8
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// IN None
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// OUT r0 = SCU Base Address
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RVCT_ASM_EXPORT ArmGetScuBaseAddress
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// Read Configuration Base Address Register. ArmCBar cannot be called to get
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// the Configuration BAR as a stack is not necessary setup. The SCU is at the
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// offset 0x0000 from the Private Memory Region.
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mrc p15, 4, r0, c15, c0, 0
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bx lr
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END
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@ -1,76 +0,0 @@
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/** @file
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|
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Copyright (c) 2011-2012, ARM Limited. All rights reserved.
|
||||
|
||||
This program and the accompanying materials
|
||||
are licensed and made available under the terms and conditions of the BSD License
|
||||
which accompanies this distribution. The full text of the license may be found at
|
||||
http://opensource.org/licenses/bsd-license.php
|
||||
|
||||
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
|
||||
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
|
||||
|
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**/
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#include <Base.h>
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#include <Library/ArmLib.h>
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#include <Library/ArmCpuLib.h>
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#include <Library/ArmPlatformLib.h>
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#include <Library/IoLib.h>
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#include <Library/PcdLib.h>
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#include <Chipset/ArmCortexA9.h>
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VOID
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ArmEnableScu (
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VOID
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)
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{
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INTN ScuBase;
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ScuBase = ArmGetScuBaseAddress();
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// Invalidate all: write -1 to SCU Invalidate All register
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MmioWrite32(ScuBase + A9_SCU_INVALL_OFFSET, 0xffffffff);
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// Enable SCU
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MmioWrite32(ScuBase + A9_SCU_CONTROL_OFFSET, 0x1);
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}
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VOID
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ArmCpuSetup (
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IN UINTN MpId
|
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)
|
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{
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// Enable SWP instructions
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ArmEnableSWPInstruction ();
|
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|
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// Enable program flow prediction, if supported.
|
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ArmEnableBranchPrediction ();
|
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|
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// If MPCore then Enable the SCU
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if (ArmIsMpCore()) {
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// Signals the Cortex-A9 processor is taking part in coherency
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ArmSetAuxCrBit (A9_FEATURE_SMP);
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ArmEnableScu ();
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}
|
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}
|
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|
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|
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VOID
|
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ArmCpuSetupSmpNonSecure (
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IN UINTN MpId
|
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)
|
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{
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INTN ScuBase;
|
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|
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// Make the SCU accessible in Non Secure world
|
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if (ArmPlatformIsPrimaryCore (MpId)) {
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ScuBase = ArmGetScuBaseAddress();
|
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|
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// Allow NS access to SCU register
|
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MmioOr32 (ScuBase + A9_SCU_SACR_OFFSET, 0xf);
|
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// Allow NS access to Private Peripherals
|
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MmioOr32 (ScuBase + A9_SCU_SSACR_OFFSET, 0xfff);
|
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}
|
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}
|
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@ -1,37 +0,0 @@
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#/* @file
|
||||
# Copyright (c) 2011-2013, ARM Limited. All rights reserved.
|
||||
#
|
||||
# This program and the accompanying materials
|
||||
# are licensed and made available under the terms and conditions of the BSD License
|
||||
# which accompanies this distribution. The full text of the license may be found at
|
||||
# http://opensource.org/licenses/bsd-license.php
|
||||
#
|
||||
# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
|
||||
# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
|
||||
#
|
||||
#*/
|
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|
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[Defines]
|
||||
INF_VERSION = 0x00010005
|
||||
BASE_NAME = ArmCortexA9Lib
|
||||
FILE_GUID = c9709ea3-1beb-4806-889a-8a1d5e5e1697
|
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MODULE_TYPE = BASE
|
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VERSION_STRING = 1.0
|
||||
LIBRARY_CLASS = ArmCpuLib
|
||||
|
||||
[Packages]
|
||||
MdePkg/MdePkg.dec
|
||||
ArmPkg/ArmPkg.dec
|
||||
ArmPlatformPkg/ArmPlatformPkg.dec
|
||||
|
||||
[LibraryClasses]
|
||||
ArmLib
|
||||
ArmPlatformLib
|
||||
IoLib
|
||||
PcdLib
|
||||
|
||||
[Sources.common]
|
||||
ArmCortexA9Lib.c
|
||||
ArmCortexA9Helper.asm | RVCT
|
||||
ArmCortexA9Helper.S | GCC
|
||||
|
|
@ -1,39 +0,0 @@
|
|||
/** @file
|
||||
|
||||
Copyright (c) 2011 - 2013, ARM Limited. All rights reserved.
|
||||
|
||||
This program and the accompanying materials
|
||||
are licensed and made available under the terms and conditions of the BSD License
|
||||
which accompanies this distribution. The full text of the license may be found at
|
||||
http://opensource.org/licenses/bsd-license.php
|
||||
|
||||
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
|
||||
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
|
||||
|
||||
**/
|
||||
|
||||
#include <Base.h>
|
||||
#include <Library/ArmCpuLib.h>
|
||||
#include <Library/ArmGenericTimerCounterLib.h>
|
||||
#include <Library/PcdLib.h>
|
||||
|
||||
#include <Chipset/AArch64.h>
|
||||
|
||||
VOID
|
||||
ArmCpuSetup (
|
||||
IN UINTN MpId
|
||||
)
|
||||
{
|
||||
// Note: System Counter frequency can only be set in Secure privileged mode,
|
||||
// if security extensions are implemented.
|
||||
ArmGenericTimerSetTimerFreq (PcdGet32 (PcdArmArchTimerFreqInHz));
|
||||
}
|
||||
|
||||
|
||||
VOID
|
||||
ArmCpuSetupSmpNonSecure (
|
||||
IN UINTN MpId
|
||||
)
|
||||
{
|
||||
// Nothing to do
|
||||
}
|
|
@ -1,34 +0,0 @@
|
|||
#/* @file
|
||||
# Copyright (c) 2011 - 2014, ARM Limited. All rights reserved.
|
||||
#
|
||||
# This program and the accompanying materials
|
||||
# are licensed and made available under the terms and conditions of the BSD License
|
||||
# which accompanies this distribution. The full text of the license may be found at
|
||||
# http://opensource.org/licenses/bsd-license.php
|
||||
#
|
||||
# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
|
||||
# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
|
||||
#
|
||||
#*/
|
||||
|
||||
[Defines]
|
||||
INF_VERSION = 0x00010005
|
||||
BASE_NAME = ArmCortexAEMv8Lib
|
||||
FILE_GUID = 8ab5a7e3-86b1-4dd3-a092-09ee801e774b
|
||||
MODULE_TYPE = BASE
|
||||
VERSION_STRING = 1.0
|
||||
LIBRARY_CLASS = ArmCpuLib
|
||||
|
||||
[Packages]
|
||||
MdePkg/MdePkg.dec
|
||||
ArmPkg/ArmPkg.dec
|
||||
|
||||
[LibraryClasses]
|
||||
ArmGenericTimerCounterLib
|
||||
PcdLib
|
||||
|
||||
[Sources.common]
|
||||
ArmCortexAEMv8Lib.c
|
||||
|
||||
[FixedPcd]
|
||||
gArmTokenSpaceGuid.PcdArmArchTimerFreqInHz
|
|
@ -1,28 +0,0 @@
|
|||
/** @file
|
||||
|
||||
Copyright (c) 2011-2012, ARM Limited. All rights reserved.
|
||||
|
||||
This program and the accompanying materials
|
||||
are licensed and made available under the terms and conditions of the BSD License
|
||||
which accompanies this distribution. The full text of the license may be found at
|
||||
http://opensource.org/licenses/bsd-license.php
|
||||
|
||||
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
|
||||
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
|
||||
|
||||
**/
|
||||
|
||||
#ifndef __ARMCPU_LIB__
|
||||
#define __ARMCPU_LIB__
|
||||
|
||||
VOID
|
||||
ArmCpuSetup (
|
||||
IN UINTN MpId
|
||||
);
|
||||
|
||||
VOID
|
||||
ArmCpuSetupSmpNonSecure (
|
||||
IN UINTN MpId
|
||||
);
|
||||
|
||||
#endif // __ARMCPU_LIB__
|
Loading…
Reference in New Issue