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UefiCpuPkg/Include/Register/ArchitecturalMsr.h: Add new MSR.

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Changes includes:
  1. Add new MSRs: MSR_IA32_L2_QOS_CFG/MSR_IA32_CSTAR.

Cc: Michael D Kinney <michael.d.kinney@intel.com>
Cc: Ruiyu Ni <ruiyu.ni@intel.com>
Cc: Laszlo Ersek <lersek@redhat.com>
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Eric Dong <eric.dong@intel.com>
Reviewed-by: Ruiyu Ni <ruiyu.ni@intel.com>
Acked-by: Laszlo Ersek <lersek@redhat.com>
This commit is contained in:
Eric Dong 2018-08-30 14:13:13 +08:00
parent 3add020579
commit d05b288ae9
1 changed files with 64 additions and 0 deletions

64
UefiCpuPkg/Include/Register/ArchitecturalMsr.h

@ -5908,6 +5908,51 @@ typedef union {
UINT64 Uint64;
} MSR_IA32_L3_QOS_CFG_REGISTER;
/**
L2 QOS Configuration (R/W). If ( CPUID.(EAX=10H, ECX=2):ECX.[2] = 1 ).
@param ECX MSR_IA32_L2_QOS_CFG (0x00000C82)
@param EAX Lower 32-bits of MSR value.
Described by the type MSR_IA32_L2_QOS_CFG_REGISTER.
@param EDX Upper 32-bits of MSR value.
Described by the type MSR_IA32_L2_QOS_CFG_REGISTER.
<b>Example usage</b>
@code
MSR_IA32_L2_QOS_CFG_REGISTER Msr;
Msr.Uint64 = AsmReadMsr64 (MSR_IA32_L2_QOS_CFG);
AsmWriteMsr64 (MSR_IA32_L2_QOS_CFG, Msr.Uint64);
@endcode
@note MSR_IA32_L2_QOS_CFG is defined as IA32_L2_QOS_CFG in SDM.
**/
#define MSR_IA32_L2_QOS_CFG 0x00000C82
/**
MSR information returned for MSR index #MSR_IA32_L2_QOS_CFG
**/
typedef union {
///
/// Individual bit fields
///
struct {
///
/// [Bit 0] Enable (R/W) Set 1 to enable L2 CAT masks and COS to operate
/// in Code and Data Prioritization (CDP) mode.
///
UINT32 Enable:1;
UINT32 Reserved1:31;
UINT32 Reserved2:32;
} Bits;
///
/// All bit fields as a 32-bit value
///
UINT32 Uint32;
///
/// All bit fields as a 64-bit value
///
UINT64 Uint64;
} MSR_IA32_L2_QOS_CFG_REGISTER;
/**
Monitoring Event Select Register (R/W). If ( CPUID.(EAX=07H, ECX=0):EBX.[12]
@ -6380,6 +6425,25 @@ typedef union {
**/
#define MSR_IA32_LSTAR 0xC0000082
/**
IA-32e Mode System Call Target Address (R/W) Not used, as the SYSCALL
instruction is not recognized in compatibility mode. If
CPUID.80000001:EDX.[29] = 1.
@param ECX MSR_IA32_CSTAR (0xC0000083)
@param EAX Lower 32-bits of MSR value.
@param EDX Upper 32-bits of MSR value.
<b>Example usage</b>
@code
UINT64 Msr;
Msr = AsmReadMsr64 (MSR_IA32_CSTAR);
AsmWriteMsr64 (MSR_IA32_CSTAR, Msr);
@endcode
@note MSR_IA32_CSTAR is defined as IA32_CSTAR in SDM.
**/
#define MSR_IA32_CSTAR 0xC0000083
/**
System Call Flag Mask (R/W). If CPUID.80000001:EDX.[29] = 1.