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UefiCpuPkg: SmmCpuFeaturesLib: Add MSR_SMM_FEATURE_CONTROL support

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Add support for the reading and writing MSR_SMM_FEATURE_CONTROL
through the SmmCpuFeaturesIsSmmRegisterSupported(),
SmmCpuFeaturesGetSmmRegister(), and SmmCpuFeaturesSetSmmRegister()
functions.  This MSR is supported if the Family/Model is 06_3C,
06_45, or 06_46.

Cc: "Yao, Jiewen" <jiewen.yao@intel.com>
Cc: Jeff Fan <jeff.fan@intel.com>

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Michael Kinney <michael.d.kinney@intel.com>
Reviewed-by: "Yao, Jiewen" <jiewen.yao@intel.com>

git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@18690 6f19259b-4bc3-4df7-8a09-765794883524
This commit is contained in:
Michael Kinney 2015-10-28 07:16:38 +00:00 committed by mdkinney
parent c617380446
commit d26a7a3fa2
1 changed files with 29 additions and 0 deletions
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29
UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmCpuFeaturesLib.c
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@ -33,12 +33,18 @@ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
#define SMM_FEATURES_LIB_IA32_CORE_SMRR_PHYSMASK 0x0A1 #define SMM_FEATURES_LIB_IA32_CORE_SMRR_PHYSMASK 0x0A1
#define EFI_MSR_SMRR_MASK 0xFFFFF000 #define EFI_MSR_SMRR_MASK 0xFFFFF000
#define EFI_MSR_SMRR_PHYS_MASK_VALID BIT11 #define EFI_MSR_SMRR_PHYS_MASK_VALID BIT11
#define SMM_FEATURES_LIB_SMM_FEATURE_CONTROL 0x4E0
// //
// Set default value to assume SMRR is not supported // Set default value to assume SMRR is not supported
// //
BOOLEAN mSmrrSupported = FALSE; BOOLEAN mSmrrSupported = FALSE;
//
// Set default value to assume MSR_SMM_FEATURE_CONTROL is not supported
//
BOOLEAN mSmmFeatureControlSupported = FALSE;
// //
// Set default value to assume IA-32 Architectural MSRs are used // Set default value to assume IA-32 Architectural MSRs are used
// //
@ -125,6 +131,20 @@ SmmCpuFeaturesLibConstructor (
} }
} }
//
// Intel(R) 64 and IA-32 Architectures Software Developer's Manual
// Volume 3C, Section 35.10.1 MSRs in 4th Generation Intel(R) Core(TM)
// Processor Family
//
// If CPU Family/Model is 06_3C, 06_45, or 06_46 then use 4th Generation
// Intel(R) Core(TM) Processor Family MSRs
//
if (FamilyId == 0x06) {
if (ModelId == 0x3C || ModelId == 0x45 || ModelId == 0x46) {
mSmmFeatureControlSupported = TRUE;
}
}
// //
// Intel(R) 64 and IA-32 Architectures Software Developer's Manual // Intel(R) 64 and IA-32 Architectures Software Developer's Manual
// Volume 3C, Section 34.4.2 SMRAM Caching // Volume 3C, Section 34.4.2 SMRAM Caching
@ -457,6 +477,9 @@ SmmCpuFeaturesIsSmmRegisterSupported (
IN SMM_REG_NAME RegName IN SMM_REG_NAME RegName
) )
{ {
if (mSmmFeatureControlSupported && RegName == SmmRegFeatureControl) {
return TRUE;
}
return FALSE; return FALSE;
} }
@ -479,6 +502,9 @@ SmmCpuFeaturesGetSmmRegister (
IN SMM_REG_NAME RegName IN SMM_REG_NAME RegName
) )
{ {
if (mSmmFeatureControlSupported && RegName == SmmRegFeatureControl) {
return AsmReadMsr64 (SMM_FEATURES_LIB_SMM_FEATURE_CONTROL);
}
return 0; return 0;
} }
@ -501,6 +527,9 @@ SmmCpuFeaturesSetSmmRegister (
IN UINT64 Value IN UINT64 Value
) )
{ {
if (mSmmFeatureControlSupported && RegName == SmmRegFeatureControl) {
AsmWriteMsr64 (SMM_FEATURES_LIB_SMM_FEATURE_CONTROL, Value);
}
} }
/** /**