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MdePkg/Include: Add LOONGARCH related definitions EDK2 CI. 

REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4053

HTTP/PXE boot LOONGARCH64 related definitions for EDK2 CI.

For the LOONGARCH values, please seeing following URL section
"Processor Architecture Types":
https://www.iana.org/assignments/dhcpv6-parameters/dhcpv6-parameters.xhtml

Cc: Michael D Kinney <michael.d.kinney@intel.com>
Cc: Liming Gao <gaoliming@byosoft.com.cn>
Cc: Zhiguang Liu <zhiguang.liu@intel.com>

Signed-off-by: Chao Li <lichao@loongson.cn>
Reviewed-by: Michael D Kinney <michael.d.kinney@intel.com>
This commit is contained in:
Chao Li 2022-09-13 17:03:33 +08:00 committed by mergify[bot]
parent c5f4b4fd03
commit d2c0d52ed6
1 changed files with 25 additions and 20 deletions
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45
MdePkg/Include/IndustryStandard/Dhcp.h
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@ -4,6 +4,7 @@
Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>
Copyright (c) 2020, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
Copyright (c) 2022, Loongson Technology Corporation Limited. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
**/
@ -256,27 +257,31 @@ typedef enum {
///
/// Processor Architecture Types
/// These identifiers are defined by IETF:
/// http://www.ietf.org/assignments/dhcpv6-parameters/dhcpv6-parameters.xml
/// These identifiers are defined by IANA:
/// https://www.iana.org/assignments/dhcpv6-parameters/dhcpv6-parameters.xhtml
///
#define PXE_CLIENT_ARCH_X86_BIOS 0x0000 /// x86 BIOS for PXE
#define PXE_CLIENT_ARCH_IPF 0x0002 /// Itanium for PXE
#define PXE_CLIENT_ARCH_IA32 0x0006 /// x86 uefi for PXE
#define PXE_CLIENT_ARCH_X64 0x0007 /// x64 uefi for PXE
#define PXE_CLIENT_ARCH_EBC 0x0009 /// EBC for PXE
#define PXE_CLIENT_ARCH_ARM 0x000A /// Arm uefi 32 for PXE
#define PXE_CLIENT_ARCH_AARCH64 0x000B /// Arm uefi 64 for PXE
#define PXE_CLIENT_ARCH_RISCV32 0x0019 /// RISC-V uefi 32 for PXE
#define PXE_CLIENT_ARCH_RISCV64 0x001B /// RISC-V uefi 64 for PXE
#define PXE_CLIENT_ARCH_RISCV128 0x001D /// RISC-V uefi 128 for PXE
#define PXE_CLIENT_ARCH_X86_BIOS 0x0000 /// x86 BIOS for PXE
#define PXE_CLIENT_ARCH_IPF 0x0002 /// Itanium for PXE
#define PXE_CLIENT_ARCH_IA32 0x0006 /// x86 uefi for PXE
#define PXE_CLIENT_ARCH_X64 0x0007 /// x64 uefi for PXE
#define PXE_CLIENT_ARCH_EBC 0x0009 /// EBC for PXE
#define PXE_CLIENT_ARCH_ARM 0x000A /// Arm uefi 32 for PXE
#define PXE_CLIENT_ARCH_AARCH64 0x000B /// Arm uefi 64 for PXE
#define PXE_CLIENT_ARCH_RISCV32 0x0019 /// RISC-V uefi 32 for PXE
#define PXE_CLIENT_ARCH_RISCV64 0x001B /// RISC-V uefi 64 for PXE
#define PXE_CLIENT_ARCH_RISCV128 0x001D /// RISC-V uefi 128 for PXE
#define PXE_CLIENT_ARCH_LOONGARCH32 0x0025 /// LoongArch uefi 32 for PXE
#define PXE_CLIENT_ARCH_LOONGARCH64 0x0027 /// LoongArch uefi 64 for PXE
#define HTTP_CLIENT_ARCH_IA32 0x000F /// x86 uefi boot from http
#define HTTP_CLIENT_ARCH_X64 0x0010 /// x64 uefi boot from http
#define HTTP_CLIENT_ARCH_EBC 0x0011 /// EBC boot from http
#define HTTP_CLIENT_ARCH_ARM 0x0012 /// Arm uefi 32 boot from http
#define HTTP_CLIENT_ARCH_AARCH64 0x0013 /// Arm uefi 64 boot from http
#define HTTP_CLIENT_ARCH_RISCV32 0x001A /// RISC-V uefi 32 boot from http
#define HTTP_CLIENT_ARCH_RISCV64 0x001C /// RISC-V uefi 64 boot from http
#define HTTP_CLIENT_ARCH_RISCV128 0x001E /// RISC-V uefi 128 boot from http
#define HTTP_CLIENT_ARCH_IA32 0x000F /// x86 uefi boot from http
#define HTTP_CLIENT_ARCH_X64 0x0010 /// x64 uefi boot from http
#define HTTP_CLIENT_ARCH_EBC 0x0011 /// EBC boot from http
#define HTTP_CLIENT_ARCH_ARM 0x0012 /// Arm uefi 32 boot from http
#define HTTP_CLIENT_ARCH_AARCH64 0x0013 /// Arm uefi 64 boot from http
#define HTTP_CLIENT_ARCH_RISCV32 0x001A /// RISC-V uefi 32 boot from http
#define HTTP_CLIENT_ARCH_RISCV64 0x001C /// RISC-V uefi 64 boot from http
#define HTTP_CLIENT_ARCH_RISCV128 0x001E /// RISC-V uefi 128 boot from http
#define HTTP_CLIENT_ARCH_LOONGARCH32 0x0026 /// LoongArch uefi 32 boot from http
#define HTTP_CLIENT_ARCH_LOONGARCH64 0x0028 /// LoongArch uefi 64 boot from http
#endif