mirror of https://github.com/acidanthera/audk.git
MdeModulePkg: Replace with UFS_UNIT_DESC to fix timeout problem
BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=3714 Replace with UFS_UNIT_DESC to fix response timeout problem. Cc: Hao A Wu <hao.a.wu@intel.com> Cc: Ray Ni <ray.ni@intel.com> Cc: Ian Chiu <Ian.chiu@intel.com> Cc: Maggie Chu <maggie.chu@intel.com> Signed-off-by: VincentX Ke <vincentx.ke@intel.com> Reviewed-by: Hao A Wu <hao.a.wu@intel.com>
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@ -1,6 +1,6 @@
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/** @file
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Copyright (c) 2014 - 2019, Intel Corporation. All rights reserved.<BR>
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Copyright (c) 2014 - 2021, Intel Corporation. All rights reserved.<BR>
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SPDX-License-Identifier: BSD-2-Clause-Patent
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**/
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@ -1037,9 +1037,9 @@ InitializeUfsBlockIoPeim (
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UFS_PEIM_HC_PRIVATE_DATA *Private;
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EDKII_UFS_HOST_CONTROLLER_PPI *UfsHcPpi;
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UINT32 Index;
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UFS_CONFIG_DESC Config;
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UINTN MmioBase;
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UINT8 Controller;
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UFS_UNIT_DESC UnitDescriptor;
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//
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// Shadow this PEIM to run from memory
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@ -1126,19 +1126,18 @@ InitializeUfsBlockIoPeim (
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}
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//
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// Get Ufs Device's Lun Info by reading Configuration Descriptor.
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// Check if 8 common luns are active and set corresponding bit mask.
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//
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Status = UfsRwDeviceDesc (Private, TRUE, UfsConfigDesc, 0, 0, &Config, sizeof (UFS_CONFIG_DESC));
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if (EFI_ERROR (Status)) {
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DEBUG ((DEBUG_ERROR, "Ufs Get Configuration Descriptor Error, Status = %r\n", Status));
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Controller++;
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continue;
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}
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for (Index = 0; Index < UFS_PEIM_MAX_LUNS; Index++) {
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if (Config.UnitDescConfParams[Index].LunEn != 0) {
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Private->Luns.BitMask |= (BIT0 << Index);
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Status = UfsRwDeviceDesc (Private, TRUE, UfsUnitDesc, (UINT8)Index, 0, &UnitDescriptor, sizeof (UFS_UNIT_DESC));
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if (EFI_ERROR (Status)) {
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DEBUG ((DEBUG_ERROR, "Fail to read UFS Unit Descriptor, Index = %X, Status = %r\n", Index, Status));
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continue;
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}
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if (UnitDescriptor.LunEn == 0x1) {
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DEBUG ((DEBUG_INFO, "Ufs %d Lun %d is enabled\n", Controller, Index));
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Private->Luns.BitMask |= (BIT0 << Index);
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}
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}
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