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IntelSiliconPkg: Fixed bug in IgdOpregion spec 

Spec documents Mailbox3 - RM31 size as 0x45(69) instead of 0x46(70)

Cc: Jiewen Yao <jiewen.yao@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Giri P Mudusuru <giri.p.mudusuru@intel.com>
Reviewed-by: Jiewen Yao <jiewen.yao@intel.com>
This commit is contained in:
Giri P Mudusuru 2016-10-17 20:10:16 -07:00
parent aaba2a44c2
commit d4a9b90fa7
1 changed files with 3 additions and 1 deletions
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4
IntelSiliconPkg/Include/IndustryStandard/IgdOpRegion.h
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@ -4,6 +4,8 @@
https://01.org/sites/default/files/documentation/skl_opregion_rev0p5.pdf https://01.org/sites/default/files/documentation/skl_opregion_rev0p5.pdf
@note Fixed bug in the spec Mailbox3 - RM31 size from 0x45(69) to 0x46(70)
Copyright (c) 2016, Intel Corporation. All rights reserved.<BR> Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>
This program and the accompanying materials This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License are licensed and made available under the terms and conditions of the BSD License
@ -116,7 +118,7 @@ typedef struct {
UINT64 FDSS; ///< Offset 0x3AA DSS Buffer address allocated for IFFS feature UINT64 FDSS; ///< Offset 0x3AA DSS Buffer address allocated for IFFS feature
UINT32 FDSP; ///< Offset 0x3B2 Size of DSS buffer UINT32 FDSP; ///< Offset 0x3B2 Size of DSS buffer
UINT32 STAT; ///< Offset 0x3B6 State Indicator UINT32 STAT; ///< Offset 0x3B6 State Indicator
UINT8 RM31[0x45]; ///< Offset 0x3BA - 0x3FF Reserved Must be zero UINT8 RM31[0x46]; ///< Offset 0x3BA - 0x3FF Reserved Must be zero. Bug in spec 0x45(69)
} IGD_OPREGION_MBOX3; } IGD_OPREGION_MBOX3;
/// ///