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ShellPkg: Support parser of MADT for LoongArch64
Parse CORE_PIC, LIO_PIC, HT_PIC, EIO_PIC, MSI_PIC, BIO_PIC and LPC_PIC tables in ACPI SPEC 6.5. REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4306 Cc: Zhichao Gao <zhichao.gao@intel.com> Cc: Chao Li <lichao@loongson.cn> Signed-off-by: Dongyan Qian <qiandongyan@loongson.cn> Co-authored-by: Jinwei Wang <wangjinwei@loongson.cn> Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn> Reviewed-by: Chao Li <lichao@loongson.cn>
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Dongyan Qian
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@ -3,6 +3,7 @@
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Copyright (c) 2016 - 2023, ARM Limited. All rights reserved.
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Copyright (c) 2016 - 2023, ARM Limited. All rights reserved.
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Copyright (c) 2022, AMD Incorporated. All rights reserved.
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Copyright (c) 2022, AMD Incorporated. All rights reserved.
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Copyright (c) 2024, Loongson Technology Corporation Limited. All rights reserved.
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SPDX-License-Identifier: BSD-2-Clause-Patent
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SPDX-License-Identifier: BSD-2-Clause-Patent
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@par Reference(s):
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@par Reference(s):
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@ -325,6 +326,92 @@ STATIC CONST ACPI_PARSER LocalX2ApicNmi[] = {
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{ L"Reserved", 3, 9, L"0x%x%x%x", Dump3Chars, NULL, NULL, NULL }
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{ L"Reserved", 3, 9, L"0x%x%x%x", Dump3Chars, NULL, NULL, NULL }
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};
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};
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/**
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An ACPI_PARSER array describing the Core Pragrammable Interrupt Controller (CORE PIC) Structure.
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**/
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STATIC CONST ACPI_PARSER CorePic[] = {
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{ L"Type", 1, 0, L"0x%x", NULL, NULL, NULL, NULL },
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{ L"Length", 1, 1, L"%d", NULL, NULL, NULL, NULL },
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{ L"Version", 1, 2, L"0x%x", NULL, NULL, NULL, NULL },
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{ L"ACPI Processor ID", 4, 3, L"0x%x", NULL, NULL, NULL, NULL },
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{ L"Physical Processor ID", 4, 7, L"0x%x", NULL, NULL, NULL, NULL },
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{ L"Flags", 4, 11, L"0x%x", NULL, NULL, NULL, NULL }
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};
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/**
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An ACPI_PARSER array describing the Leagcy I/O Programmable Interrupt Controller (LIO PIC) Structure.
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**/
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STATIC CONST ACPI_PARSER LegacyIoPic[] = {
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{ L"Type", 1, 0, L"0x%x", NULL, NULL, NULL, NULL },
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{ L"Length", 1, 1, L"%d", NULL, NULL, NULL, NULL },
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{ L"Version", 1, 2, L"0x%x", NULL, NULL, NULL, NULL },
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{ L"Base Address", 8, 3, L"0x%lx", NULL, NULL, NULL, NULL },
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{ L"Size", 2, 11, L"0x%x", NULL, NULL, NULL, NULL },
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{ L"Cascade Vector", 2, 13, L"0x%x", NULL, NULL, NULL, NULL },
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{ L"Cascade vector mapping", 8, 15, L"0x%lx", NULL, NULL, NULL, NULL }
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};
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/**
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An ACPI_PARSER array describing the HyperTransport Programmable Interrupt Controller (HT PIC) Structure.
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**/
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STATIC CONST ACPI_PARSER HyperTransportPic[] = {
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{ L"Type", 1, 0, L"0x%x", NULL, NULL, NULL, NULL },
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{ L"Length", 1, 1, L"%d", NULL, NULL, NULL, NULL },
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{ L"Version", 1, 2, L"0x%x", NULL, NULL, NULL, NULL },
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{ L"Base Address", 8, 3, L"0x%lx", NULL, NULL, NULL, NULL },
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{ L"Size", 2, 11, L"0x%x", NULL, NULL, NULL, NULL },
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{ L"Cascade Vector", 8, 13, L"0x%lx", NULL, NULL, NULL, NULL }
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};
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/**
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An ACPI_PARSER array describing the Extend I/0 Programmable Interrupt Controller (EIO PIC) Structure.
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**/
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STATIC CONST ACPI_PARSER ExtendIoPic[] = {
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{ L"Type", 1, 0, L"0x%x", NULL, NULL, NULL, NULL },
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{ L"Length", 1, 1, L"%d", NULL, NULL, NULL, NULL },
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{ L"Version", 1, 2, L"0x%x", NULL, NULL, NULL, NULL },
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{ L"Cascade Vector", 1, 3, L"0x%x", NULL, NULL, NULL, NULL },
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{ L"Node", 1, 4, L"0x%x", NULL, NULL, NULL, NULL },
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{ L"Node Map", 8, 5, L"0x%lx", NULL, NULL, NULL, NULL }
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};
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/**
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An ACPI_PARSER array describing the MSI Programmable Interrupt Controller (MSI PIC) Structure.
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**/
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STATIC CONST ACPI_PARSER MsiPic[] = {
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{ L"Type", 1, 0, L"0x%x", NULL, NULL, NULL, NULL },
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{ L"Length", 1, 1, L"%d", NULL, NULL, NULL, NULL },
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{ L"Version", 1, 2, L"0x%x", NULL, NULL, NULL, NULL },
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{ L"Message Address", 8, 3, L"0x%lx", NULL, NULL, NULL, NULL },
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{ L"Start", 4, 11, L"0x%x", NULL, NULL, NULL, NULL },
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{ L"Count", 4, 15, L"0x%x", NULL, NULL, NULL, NULL }
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};
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/**
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An ACPI_PARSER array describing the Bridge I/O Programmable Interrupt Controller (BIO PIC) Structure.
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**/
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STATIC CONST ACPI_PARSER BridgeIoPic[] = {
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{ L"Type", 1, 0, L"0x%x", NULL, NULL, NULL, NULL },
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{ L"Length", 1, 1, L"%d", NULL, NULL, NULL, NULL },
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{ L"Version", 1, 2, L"0x%x", NULL, NULL, NULL, NULL },
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{ L"Base Address", 8, 3, L"0x%lx", NULL, NULL, NULL, NULL },
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{ L"Size", 2, 11, L"0x%x", NULL, NULL, NULL, NULL },
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{ L"Hardware ID", 2, 13, L"0x%x", NULL, NULL, NULL, NULL },
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{ L"GSI base", 2, 15, L"0x%x", NULL, NULL, NULL, NULL }
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};
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/**
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An ACPI_PARSER array describing the LPC Programmable Interrupt Controller (LPC PIC) Structure.
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**/
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STATIC CONST ACPI_PARSER LpcPic[] = {
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{ L"Type", 1, 0, L"0x%x", NULL, NULL, NULL, NULL },
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{ L"Length", 1, 1, L"%d", NULL, NULL, NULL, NULL },
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{ L"Version", 1, 2, L"0x%x", NULL, NULL, NULL, NULL },
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{ L"Base Address", 8, 3, L"0x%lx", NULL, NULL, NULL, NULL },
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{ L"Size", 2, 11, L"0x%x", NULL, NULL, NULL, NULL },
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{ L"Cascade vector", 2, 13, L"0x%x", NULL, NULL, NULL, NULL }
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};
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/**
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/**
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An ACPI_PARSER array describing the ACPI MADT Table.
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An ACPI_PARSER array describing the ACPI MADT Table.
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**/
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**/
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@ -572,6 +659,97 @@ ParseAcpiMadt (
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break;
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break;
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}
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}
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case EFI_ACPI_6_5_CORE_PIC:
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{
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ParseAcpi (
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TRUE,
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2,
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"CORE PIC",
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InterruptContollerPtr,
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*MadtInterruptControllerLength,
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PARSER_PARAMS (CorePic)
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);
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break;
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}
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case EFI_ACPI_6_5_LIO_PIC:
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{
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ParseAcpi (
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TRUE,
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2,
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"LIO PIC",
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InterruptContollerPtr,
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*MadtInterruptControllerLength,
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PARSER_PARAMS (LegacyIoPic)
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);
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break;
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}
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case EFI_ACPI_6_5_HT_PIC:
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{
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ParseAcpi (
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TRUE,
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2,
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"HT PIC",
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InterruptContollerPtr,
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*MadtInterruptControllerLength,
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PARSER_PARAMS (HyperTransportPic)
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);
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break;
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}
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case EFI_ACPI_6_5_EIO_PIC:
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{
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ParseAcpi (
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TRUE,
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2,
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"EIO PIC",
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InterruptContollerPtr,
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*MadtInterruptControllerLength,
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PARSER_PARAMS (ExtendIoPic)
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);
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break;
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}
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case EFI_ACPI_6_5_MSI_PIC:
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{
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ParseAcpi (
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TRUE,
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2,
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"MSI PIC",
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InterruptContollerPtr,
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*MadtInterruptControllerLength,
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PARSER_PARAMS (MsiPic)
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);
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break;
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}
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case EFI_ACPI_6_5_BIO_PIC:
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{
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ParseAcpi (
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TRUE,
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2,
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"BIO PIC",
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InterruptContollerPtr,
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*MadtInterruptControllerLength,
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PARSER_PARAMS (BridgeIoPic)
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);
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break;
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}
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case EFI_ACPI_6_5_LPC_PIC:
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{
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ParseAcpi (
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TRUE,
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2,
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"LPC PIC",
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InterruptContollerPtr,
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*MadtInterruptControllerLength,
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PARSER_PARAMS (LpcPic)
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);
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break;
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}
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default:
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default:
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{
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{
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IncrementErrorCount ();
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IncrementErrorCount ();
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