mirror of https://github.com/acidanthera/audk.git
ArmPlatformPkg/ArmVExpressLibCTA9x4: Fixed the initial secondary core bringup when remapping DRAM at 0x0
If the DRAM is remapped at 0x0 then we need to wake up the secondary cores from wfe (waiting for the memory to be initialized) as the instruction is still in the remapped flash region at 0x0 to make them jumping into the C-code which lives in the NOR1 at 0x44000000 before the region 0x0 is remapped as DRAM. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@14910 6f19259b-4bc3-4df7-8a09-765794883524
This commit is contained in:
Olivier Martin
oliviermartin
parent
6cc28dc4c0
commit
d4c92adef7
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@ -33,8 +33,6 @@
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MemoryAllocationLib
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PL341DmcLib
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PL301AxiLib
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L2X0CacheLib
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SerialPortLib
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[Sources.common]
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CTA9x4Helper.asm | RVCT
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@ -1,6 +1,6 @@
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/** @file
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*
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* Copyright (c) 2011-2012, ARM Limited. All rights reserved.
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* Copyright (c) 2011-2013, ARM Limited. All rights reserved.
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*
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* This program and the accompanying materials
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* are licensed and made available under the terms and conditions of the BSD License
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@ -16,7 +16,6 @@
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#include <Library/ArmPlatformLib.h>
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#include <Library/DebugLib.h>
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#include <Library/PcdLib.h>
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#include <Library/SerialPortLib.h>
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#include <Drivers/PL341Dmc.h>
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#include <Drivers/PL301Axi.h>
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@ -26,8 +25,6 @@
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#include <ArmPlatform.h>
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#define SerialPrint(txt) SerialPortWrite ((UINT8*)(txt), AsciiStrLen(txt)+1);
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ARM_CORE_INFO mVersatileExpressMpCoreInfoCTA9x4[] = {
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{
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// Cluster 0, Core 0
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@ -163,19 +160,8 @@ ArmPlatformInitializeSystemMemory (
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VOID
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)
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{
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UINT32 Value;
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// Memory Map remapping
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if (FeaturePcdGet(PcdNorFlashRemapping)) {
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SerialPrint ("Secure ROM at 0x0\n\r");
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} else {
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Value = MmioRead32(ARM_VE_SYS_CFGRW1_REG); //Scc - CFGRW1
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// Remap the DRAM to 0x0
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MmioWrite32(ARM_VE_SYS_CFGRW1_REG, (Value & 0x0FFFFFFF) | ARM_VE_CFGRW1_REMAP_DRAM);
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}
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PL341DmcInit(ARM_VE_DMC_BASE, &DDRTimings);
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PL301AxiInit(ARM_VE_FAXI_BASE);
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PL341DmcInit (ARM_VE_DMC_BASE, &DDRTimings);
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PL301AxiInit (ARM_VE_FAXI_BASE);
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}
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EFI_STATUS
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@ -1,5 +1,5 @@
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#/* @file
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# Copyright (c) 2011-2012, ARM Limited. All rights reserved.
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# Copyright (c) 2011-2013, ARM Limited. All rights reserved.
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#
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# This program and the accompanying materials
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# are licensed and made available under the terms and conditions of the BSD License
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@ -46,6 +46,7 @@
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[FeaturePcd]
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gArmPlatformTokenSpaceGuid.PcdStandalone
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gArmPlatformTokenSpaceGuid.PcdNorFlashRemapping
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gArmPlatformTokenSpaceGuid.PcdSystemMemoryInitializeInSec
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[FixedPcd]
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@ -1,6 +1,6 @@
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/** @file
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*
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* Copyright (c) 2011-2012, ARM Limited. All rights reserved.
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* Copyright (c) 2011-2013, ARM Limited. All rights reserved.
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*
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* This program and the accompanying materials
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* are licensed and made available under the terms and conditions of the BSD License
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@ -17,12 +17,15 @@
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#include <Library/DebugLib.h>
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#include <Library/IoLib.h>
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#include <Library/PcdLib.h>
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#include <Library/SerialPortLib.h>
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#include <Drivers/ArmTrustzone.h>
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#include <Drivers/PL310L2Cache.h>
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#include <ArmPlatform.h>
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#define SerialPrint(txt) SerialPortWrite ((UINT8*)(txt), AsciiStrLen(txt)+1)
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/**
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Initialize the Secure peripherals and memory regions
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@ -119,6 +122,22 @@ ArmPlatformSecInitialize (
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IN UINTN MpId
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)
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{
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UINT32 Value;
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// If the DRAM is remapped at 0x0 then we need to wake up the secondary cores from wfe
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// (waiting for the memory to be initialized) as the instruction is still in the remapped
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// flash region at 0x0 to jump in the C-code which lives in the NOR1 at 0x44000000 before
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// the region 0x0 is remapped as DRAM.
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if (!FeaturePcdGet (PcdNorFlashRemapping)) {
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if (!ArmPlatformIsPrimaryCore (MpId)) {
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// Replaced ArmCallWFE () in ArmPlatformPkg/Sec/SecEntryPoint.(S|asm)
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ArmCallWFE ();
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} else {
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// Wake up the secondary core from ArmCallWFE () in ArmPlatformPkg/Sec/SecEntryPoint.(S|asm)
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ArmCallSEV ();
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}
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}
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// If it is not the primary core then there is nothing to do
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if (!ArmPlatformIsPrimaryCore (MpId)) {
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return RETURN_SUCCESS;
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@ -144,5 +163,14 @@ ArmPlatformSecInitialize (
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ArmPlatformInitializeSystemMemory ();
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}
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// Memory Map remapping
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if (FeaturePcdGet (PcdNorFlashRemapping)) {
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SerialPrint ("Secure ROM at 0x0\n\r");
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} else {
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Value = MmioRead32 (ARM_VE_SYS_CFGRW1_REG); //Scc - CFGRW1
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// Remap the DRAM to 0x0
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MmioWrite32 (ARM_VE_SYS_CFGRW1_REG, (Value & 0x0FFFFFFF) | ARM_VE_CFGRW1_REMAP_DRAM);
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}
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return RETURN_SUCCESS;
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}
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