mirror of https://github.com/acidanthera/audk.git
Missed a fix in the Cpu Driver. Added some more debug for Execption handling and clean up some uncached stuff.
git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@9789 6f19259b-4bc3-4df7-8a09-765794883524
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@ -311,7 +311,16 @@ CommonCExceptionHandler (
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// you need to subtact out the size of the PE/COFF header to get
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// get the offset that matches the link map.
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//
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DEBUG ((EFI_D_ERROR, "loadded at 0x%08x (PE/COFF offset) 0x%x (ELF or Mach-O offset) 0x%x", ImageBase, Offset, Offset - PeCoffSizeOfHeader));
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DEBUG ((EFI_D_ERROR, "loaded at 0x%08x (PE/COFF offset) 0x%x (ELF or Mach-O offset) 0x%x", ImageBase, Offset, Offset - PeCoffSizeOfHeader));
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// If we come from an image it is safe to show the instruction. We know it should not fault
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if ((SystemContext.SystemContextArm->CPSR & 0x20) == 0) {
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// ARM
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DEBUG ((EFI_D_ERROR, "\nFaulting Instruction 0x%08x", *(UINT32 *)(UINTN)SystemContext.SystemContextArm->PC));
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} else {
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// Thumb
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DEBUG ((EFI_D_ERROR, "\nFaulting Instruction 0x%04x", *(UINT16 *)(UINTN)SystemContext.SystemContextArm->PC));
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}
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}
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DEBUG_CODE_END ();
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DEBUG ((EFI_D_ERROR, "\n R0 0x%08x R1 0x%08x R2 0x%08x R3 0x%08x\n", SystemContext.SystemContextArm->R0, SystemContext.SystemContextArm->R1, SystemContext.SystemContextArm->R2, SystemContext.SystemContextArm->R3));
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@ -440,36 +440,37 @@ UpdatePageEntries (
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// EntryMask: bitmask of values to change (1 = change this value, 0 = leave alone)
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// EntryValue: values at bit positions specified by EntryMask
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EntryMask = ARM_PAGE_DESC_TYPE_MASK;
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EntryValue = ARM_PAGE_TYPE_SMALL;
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// Although the PI spec is unclear on this the GCD guarantees that only
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// one Attribute bit is set at a time, so we can safely use a switch statement
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switch (Attributes) {
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case EFI_MEMORY_UC:
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// modify cacheability attributes
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EntryMask = ARM_SMALL_PAGE_TEX_MASK | ARM_PAGE_C | ARM_PAGE_B;
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EntryMask |= ARM_SMALL_PAGE_TEX_MASK | ARM_PAGE_C | ARM_PAGE_B;
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// map to strongly ordered
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EntryValue = 0; // TEX[2:0] = 0, C=0, B=0
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EntryValue |= 0; // TEX[2:0] = 0, C=0, B=0
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break;
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case EFI_MEMORY_WC:
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// modify cacheability attributes
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EntryMask = ARM_SMALL_PAGE_TEX_MASK | ARM_PAGE_C | ARM_PAGE_B;
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EntryMask |= ARM_SMALL_PAGE_TEX_MASK | ARM_PAGE_C | ARM_PAGE_B;
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// map to normal non-cachable
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EntryValue = (0x1 << ARM_SMALL_PAGE_TEX_SHIFT); // TEX [2:0]= 001 = 0x2, B=0, C=0
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EntryValue |= (0x1 << ARM_SMALL_PAGE_TEX_SHIFT); // TEX [2:0]= 001 = 0x2, B=0, C=0
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break;
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case EFI_MEMORY_WT:
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// modify cacheability attributes
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EntryMask = ARM_SMALL_PAGE_TEX_MASK | ARM_PAGE_C | ARM_PAGE_B;
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EntryMask |= ARM_SMALL_PAGE_TEX_MASK | ARM_PAGE_C | ARM_PAGE_B;
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// write through with no-allocate
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EntryValue = ARM_PAGE_C; // TEX [2:0] = 0, C=1, B=0
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EntryValue |= ARM_PAGE_C; // TEX [2:0] = 0, C=1, B=0
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break;
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case EFI_MEMORY_WB:
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// modify cacheability attributes
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EntryMask = ARM_SMALL_PAGE_TEX_MASK | ARM_PAGE_C | ARM_PAGE_B;
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EntryMask |= ARM_SMALL_PAGE_TEX_MASK | ARM_PAGE_C | ARM_PAGE_B;
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// write back (with allocate)
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EntryValue = (0x1 << ARM_SMALL_PAGE_TEX_SHIFT) | ARM_PAGE_C | ARM_PAGE_B; // TEX [2:0] = 001, C=1, B=1
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EntryValue |= (0x1 << ARM_SMALL_PAGE_TEX_SHIFT) | ARM_PAGE_C | ARM_PAGE_B; // TEX [2:0] = 001, C=1, B=1
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break;
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case EFI_MEMORY_WP:
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@ -477,8 +478,7 @@ UpdatePageEntries (
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case EFI_MEMORY_UCE:
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// cannot be implemented UEFI definition unclear for ARM
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// Cause a page fault if these ranges are accessed.
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EntryMask = 0x3;
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EntryValue = 0;
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EntryValue = ARM_PAGE_TYPE_FAULT;
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DEBUG ((EFI_D_PAGE, "SetMemoryAttributes(): setting page %lx with unsupported attribute %x will page fault on access\n", BaseAddress, Attributes));
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break;
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@ -861,8 +861,9 @@ CpuReconvertPagesPages (
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)
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{
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EFI_STATUS Status;
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//
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DEBUG ((EFI_D_ERROR, "CpuReconvertPagesPages(%lx, %x, %lx, %lx)\n", Address, Length, VirtualMask, Attributes));
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ASSERT (FALSE);
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//
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// Unmap the alaised Address
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//
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Status = SetMemoryAttributes (Address | VirtualMask, Length, EFI_MEMORY_WP, 0);
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@ -292,7 +292,7 @@ UncachedFreeAlignedPages (
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Status = gVirtualUncachedPages->RevertPages (gVirtualUncachedPages, Memory, Pages * EFI_PAGE_SIZE, PcdGet64 (PcdArmUncachedMemoryMask), gAttributes);
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Status = gBS->FreePages ((EFI_PHYSICAL_ADDRESS) (UINTN) Buffer, Pages);
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Status = gBS->FreePages ((EFI_PHYSICAL_ADDRESS) (UINTN) Memory, Pages);
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ASSERT_EFI_ERROR (Status);
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}
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@ -207,7 +207,7 @@ UncachedInternalAllocateAlignedPages (
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}
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if (AlignedMemory != 0) {
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FlushCache(AlignedMemory, EFI_PAGES_TO_SIZE(Pages));
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FlushCache (AlignedMemory, EFI_PAGES_TO_SIZE(Pages));
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AlignedMemory = (UINTN)ConvertToUncachedAddress((VOID *)AlignedMemory);
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}
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@ -318,7 +318,7 @@ UncachedInternalAllocateAlignedPool (
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*FreePointer = RawAddress;
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if (AlignedAddress != 0) {
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FlushCache(AlignedAddress, AllocationSize);
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FlushCache (AlignedAddress, AllocationSize);
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AlignedAddress = (UINTN)ConvertToUncachedAddress((VOID *)AlignedAddress);
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}
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@ -318,12 +318,7 @@ PciIoUnmap (
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// Make sure we read buffer from uncached memory and not the cache
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//
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gCpu->FlushDataCache (gCpu, Map->HostAddress, Map->NumberOfBytes, EfiCpuFlushTypeInvalidate);
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} else if (Map->Operation == EfiPciOperationBusMasterCommonBuffer) {
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//
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// CPU was using uncached address, so anything in the cached range is bogus
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//
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gCpu->FlushDataCache (gCpu, Map->DeviceAddress, Map->NumberOfBytes, EfiCpuFlushTypeInvalidate);
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}
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}
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FreePool (Map);
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