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ArmPkg/PL390Gic: Fixed initialization when the primary core is not (Cluster0,Cpu0)

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git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@13488 6f19259b-4bc3-4df7-8a09-765794883524
This commit is contained in:
oliviermartin 2012-07-04 19:58:54 +00:00
parent 4e7d855f42
commit d69503998a
2 changed files with 15 additions and 2 deletions
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14
ArmPkg/Drivers/PL390Gic/PL390GicDxe.c
View File

@ -343,7 +343,15 @@ InterruptDxeInitialize (
UINT32 RegOffset;
UINTN RegShift;
EFI_CPU_ARCH_PROTOCOL *Cpu;
UINT32 CpuTarget;
// Check PcdGicPrimaryCoreId has been set in case the Primary Core is not the core 0 of Cluster 0
DEBUG_CODE_BEGIN();
if ((PcdGet32(PcdArmPrimaryCore) != 0) && (PcdGet32 (PcdGicPrimaryCoreId) == 0)) {
DEBUG((EFI_D_WARN,"Warning: the PCD PcdGicPrimaryCoreId does not seem to be set up for the configuration.\n"));
}
DEBUG_CODE_END();
// Make sure the Interrupt Controller Protocol is not already installed in the system.
ASSERT_PROTOCOL_ALREADY_INSTALLED (NULL, &gHardwareInterruptProtocolGuid);
@ -362,9 +370,11 @@ InterruptDxeInitialize (
);
}
// Configure interrupts for cpu 0
// Configure interrupts for Primary Cpu
CpuTarget = (1 << PcdGet32 (PcdGicPrimaryCoreId));
CpuTarget |= (CpuTarget << 24) | (CpuTarget << 16) | (CpuTarget << 8);
for (Index = 0; Index < (mGicNumInterrupts / 4); Index++) {
MmioWrite32 (PcdGet32(PcdGicDistributorBase) + ARM_GIC_ICDIPTR + (Index*4), 0x01010101);
MmioWrite32 (PcdGet32(PcdGicDistributorBase) + ARM_GIC_ICDIPTR + (Index*4), CpuTarget);
}
// Set binary point reg to 0x7 (no preemption)

3
ArmPkg/Drivers/PL390Gic/PL390GicDxe.inf
View File

@ -49,6 +49,9 @@
[FixedPcd.common]
gArmTokenSpaceGuid.PcdGicDistributorBase
gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase
gArmTokenSpaceGuid.PcdArmPrimaryCore
gArmTokenSpaceGuid.PcdGicPrimaryCoreId
[Depex]
gEfiCpuArchProtocolGuid