From d7e71b2925012c9706d1d044ca466173aac802a8 Mon Sep 17 00:00:00 2001 From: Paolo Bonzini Date: Mon, 30 Nov 2015 18:46:32 +0000 Subject: [PATCH] OvmfPkg: SmmCpuFeaturesLib: remove unnecessary bits SMRR, MTRR, and SMM Feature Control support is not needed on a virtual platform. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Paolo Bonzini Acked-by: Laszlo Ersek [lersek@redhat.com: insert space between ASSERT and (), convert to CRLF, refresh against SVN r18958] Cc: Paolo Bonzini Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Laszlo Ersek Reviewed-by: Michael Kinney git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@19055 6f19259b-4bc3-4df7-8a09-765794883524 --- .../SmmCpuFeaturesLib/SmmCpuFeaturesLib.c | 233 ++---------------- .../SmmCpuFeaturesLib/SmmCpuFeaturesLib.inf | 4 - 2 files changed, 17 insertions(+), 220 deletions(-) diff --git a/OvmfPkg/Library/SmmCpuFeaturesLib/SmmCpuFeaturesLib.c b/OvmfPkg/Library/SmmCpuFeaturesLib/SmmCpuFeaturesLib.c index 3e480e1761..3b6f186ee8 100644 --- a/OvmfPkg/Library/SmmCpuFeaturesLib/SmmCpuFeaturesLib.c +++ b/OvmfPkg/Library/SmmCpuFeaturesLib/SmmCpuFeaturesLib.c @@ -15,58 +15,11 @@ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. #include #include #include -#include #include #include #include -#include #include -// -// Machine Specific Registers (MSRs) -// -#define SMM_FEATURES_LIB_IA32_MTRR_CAP 0x0FE -#define SMM_FEATURES_LIB_IA32_FEATURE_CONTROL 0x03A -#define SMM_FEATURES_LIB_IA32_SMRR_PHYSBASE 0x1F2 -#define SMM_FEATURES_LIB_IA32_SMRR_PHYSMASK 0x1F3 -#define SMM_FEATURES_LIB_IA32_CORE_SMRR_PHYSBASE 0x0A0 -#define SMM_FEATURES_LIB_IA32_CORE_SMRR_PHYSMASK 0x0A1 -#define EFI_MSR_SMRR_MASK 0xFFFFF000 -#define EFI_MSR_SMRR_PHYS_MASK_VALID BIT11 -#define SMM_FEATURES_LIB_SMM_FEATURE_CONTROL 0x4E0 - -// -// MSRs required for configuration of SMM Code Access Check -// -#define SMM_FEATURES_LIB_IA32_MCA_CAP 0x17D -#define SMM_CODE_ACCESS_CHK_BIT BIT58 - -// -// Set default value to assume SMRR is not supported -// -BOOLEAN mSmrrSupported = FALSE; - -// -// Set default value to assume MSR_SMM_FEATURE_CONTROL is not supported -// -BOOLEAN mSmmFeatureControlSupported = FALSE; - -// -// Set default value to assume IA-32 Architectural MSRs are used -// -UINT32 mSmrrPhysBaseMsr = SMM_FEATURES_LIB_IA32_SMRR_PHYSBASE; -UINT32 mSmrrPhysMaskMsr = SMM_FEATURES_LIB_IA32_SMRR_PHYSMASK; - -// -// Set default value to assume MTRRs need to be configured on each SMI -// -BOOLEAN mNeedConfigureMtrrs = TRUE; - -// -// Array for state of SMRR enable on all CPUs -// -BOOLEAN *mSmrrEnabled; - /** The constructor function @@ -83,91 +36,9 @@ SmmCpuFeaturesLibConstructor ( IN EFI_SYSTEM_TABLE *SystemTable ) { - UINT32 RegEax; - UINT32 RegEdx; - UINTN FamilyId; - UINTN ModelId; - // - // Retrieve CPU Family and Model + // No need to program SMRRs on our virtual platform. // - AsmCpuid (CPUID_VERSION_INFO, &RegEax, NULL, NULL, &RegEdx); - FamilyId = (RegEax >> 8) & 0xf; - ModelId = (RegEax >> 4) & 0xf; - if (FamilyId == 0x06 || FamilyId == 0x0f) { - ModelId = ModelId | ((RegEax >> 12) & 0xf0); - } - - // - // Check CPUID(CPUID_VERSION_INFO).EDX[12] for MTRR capability - // - if ((RegEdx & BIT12) != 0) { - // - // Check MTRR_CAP MSR bit 11 for SMRR support - // - if ((AsmReadMsr64 (SMM_FEATURES_LIB_IA32_MTRR_CAP) & BIT11) != 0) { - mSmrrSupported = TRUE; - } - } - - // - // Intel(R) 64 and IA-32 Architectures Software Developer's Manual - // Volume 3C, Section 35.3 MSRs in the Intel(R) Atom(TM) Processor Family - // - // If CPU Family/Model is 06_1CH, 06_26H, 06_27H, 06_35H or 06_36H, then - // SMRR Physical Base and SMM Physical Mask MSRs are not available. - // - if (FamilyId == 0x06) { - if (ModelId == 0x1C || ModelId == 0x26 || ModelId == 0x27 || ModelId == 0x35 || ModelId == 0x36) { - mSmrrSupported = FALSE; - } - } - - // - // Intel(R) 64 and IA-32 Architectures Software Developer's Manual - // Volume 3C, Section 35.2 MSRs in the Intel(R) Core(TM) 2 Processor Family - // - // If CPU Family/Model is 06_0F or 06_17, then use Intel(R) Core(TM) 2 - // Processor Family MSRs - // - if (FamilyId == 0x06) { - if (ModelId == 0x17 || ModelId == 0x0f) { - mSmrrPhysBaseMsr = SMM_FEATURES_LIB_IA32_CORE_SMRR_PHYSBASE; - mSmrrPhysMaskMsr = SMM_FEATURES_LIB_IA32_CORE_SMRR_PHYSMASK; - } - } - - // - // Intel(R) 64 and IA-32 Architectures Software Developer's Manual - // Volume 3C, Section 34.4.2 SMRAM Caching - // An IA-32 processor does not automatically write back and invalidate its - // caches before entering SMM or before exiting SMM. Because of this behavior, - // care must be taken in the placement of the SMRAM in system memory and in - // the caching of the SMRAM to prevent cache incoherence when switching back - // and forth between SMM and protected mode operation. - // - // An IA-32 processor is a processor that does not support the Intel 64 - // Architecture. Support for the Intel 64 Architecture can be detected from - // CPUID(CPUID_EXTENDED_CPU_SIG).EDX[29] - // - // If an IA-32 processor is detected, then set mNeedConfigureMtrrs to TRUE, - // so caches are flushed on SMI entry and SMI exit, the interrupted code - // MTRRs are saved/restored, and MTRRs for SMM are loaded. - // - AsmCpuid (CPUID_EXTENDED_FUNCTION, &RegEax, NULL, NULL, NULL); - if (RegEax >= CPUID_EXTENDED_CPU_SIG) { - AsmCpuid (CPUID_EXTENDED_CPU_SIG, NULL, NULL, NULL, &RegEdx); - if ((RegEdx & BIT29) != 0) { - mNeedConfigureMtrrs = FALSE; - } - } - - // - // Allocate array for state of SMRR enable on all CPUs - // - mSmrrEnabled = (BOOLEAN *)AllocatePool (sizeof (BOOLEAN) * PcdGet32 (PcdCpuMaxLogicalProcessorNumber)); - ASSERT (mSmrrEnabled != NULL); - return EFI_SUCCESS; } @@ -205,11 +76,6 @@ SmmCpuFeaturesInitializeProcessor ( ) { SMRAM_SAVE_STATE_MAP *CpuState; - UINT64 FeatureControl; - UINT32 RegEax; - UINT32 RegEdx; - UINTN FamilyId; - UINTN ModelId; // // Configure SMBASE. @@ -218,67 +84,8 @@ SmmCpuFeaturesInitializeProcessor ( CpuState->x86.SMBASE = (UINT32)CpuHotPlugData->SmBase[CpuIndex]; // - // Intel(R) 64 and IA-32 Architectures Software Developer's Manual - // Volume 3C, Section 35.2 MSRs in the Intel(R) Core(TM) 2 Processor Family + // No need to program SMRRs on our virtual platform. // - // If Intel(R) Core(TM) Core(TM) 2 Processor Family MSRs are being used, then - // make sure SMRR Enable(BIT3) of MSR_FEATURE_CONTROL MSR(0x3A) is set before - // accessing SMRR base/mask MSRs. If Lock(BIT0) of MSR_FEATURE_CONTROL MSR(0x3A) - // is set, then the MSR is locked and can not be modified. - // - if (mSmrrSupported && mSmrrPhysBaseMsr == SMM_FEATURES_LIB_IA32_CORE_SMRR_PHYSBASE) { - FeatureControl = AsmReadMsr64 (SMM_FEATURES_LIB_IA32_FEATURE_CONTROL); - if ((FeatureControl & BIT3) == 0) { - if ((FeatureControl & BIT0) == 0) { - AsmWriteMsr64 (SMM_FEATURES_LIB_IA32_FEATURE_CONTROL, FeatureControl | BIT3); - } else { - mSmrrSupported = FALSE; - } - } - } - - // - // If SMRR is supported, then program SMRR base/mask MSRs. - // The EFI_MSR_SMRR_PHYS_MASK_VALID bit is not set until the first normal SMI. - // The code that initializes SMM environment is running in normal mode - // from SMRAM region. If SMRR is enabled here, then the SMRAM region - // is protected and the normal mode code execution will fail. - // - if (mSmrrSupported) { - AsmWriteMsr64 (mSmrrPhysBaseMsr, CpuHotPlugData->SmrrBase | MTRR_CACHE_WRITE_BACK); - AsmWriteMsr64 (mSmrrPhysMaskMsr, (~(CpuHotPlugData->SmrrSize - 1) & EFI_MSR_SMRR_MASK)); - mSmrrEnabled[CpuIndex] = FALSE; - } - - // - // Retrieve CPU Family and Model - // - AsmCpuid (CPUID_VERSION_INFO, &RegEax, NULL, NULL, &RegEdx); - FamilyId = (RegEax >> 8) & 0xf; - ModelId = (RegEax >> 4) & 0xf; - if (FamilyId == 0x06 || FamilyId == 0x0f) { - ModelId = ModelId | ((RegEax >> 12) & 0xf0); - } - - // - // Intel(R) 64 and IA-32 Architectures Software Developer's Manual - // Volume 3C, Section 35.10.1 MSRs in 4th Generation Intel(R) Core(TM) - // Processor Family. - // - // If CPU Family/Model is 06_3C, 06_45, or 06_46 then use 4th Generation - // Intel(R) Core(TM) Processor Family MSRs. - // - if (FamilyId == 0x06) { - if (ModelId == 0x3C || ModelId == 0x45 || ModelId == 0x46) { - // - // Check to see if the CPU supports the SMM Code Access Check feature - // Do not access this MSR unless the CPU supports the SmmRegFeatureControl - // - if ((AsmReadMsr64 (SMM_FEATURES_LIB_IA32_MCA_CAP) & SMM_CODE_ACCESS_CHK_BIT) != 0) { - mSmmFeatureControlSupported = TRUE; - } - } - } } /** @@ -413,7 +220,7 @@ SmmCpuFeaturesNeedConfigureMtrrs ( VOID ) { - return mNeedConfigureMtrrs; + return FALSE; } /** @@ -426,9 +233,9 @@ SmmCpuFeaturesDisableSmrr ( VOID ) { - if (mSmrrSupported && mNeedConfigureMtrrs) { - AsmWriteMsr64 (mSmrrPhysMaskMsr, AsmReadMsr64(mSmrrPhysMaskMsr) & ~EFI_MSR_SMRR_PHYS_MASK_VALID); - } + // + // No SMRR support, nothing to do + // } /** @@ -441,9 +248,9 @@ SmmCpuFeaturesReenableSmrr ( VOID ) { - if (mSmrrSupported && mNeedConfigureMtrrs) { - AsmWriteMsr64 (mSmrrPhysMaskMsr, AsmReadMsr64(mSmrrPhysMaskMsr) | EFI_MSR_SMRR_PHYS_MASK_VALID); - } + // + // No SMRR support, nothing to do + // } /** @@ -460,12 +267,8 @@ SmmCpuFeaturesRendezvousEntry ( ) { // - // If SMRR is supported and this is the first normal SMI, then enable SMRR + // No SMRR support, nothing to do // - if (mSmrrSupported && !mSmrrEnabled[CpuIndex]) { - AsmWriteMsr64 (mSmrrPhysMaskMsr, AsmReadMsr64 (mSmrrPhysMaskMsr) | EFI_MSR_SMRR_PHYS_MASK_VALID); - mSmrrEnabled[CpuIndex] = TRUE; - } } /** @@ -503,9 +306,7 @@ SmmCpuFeaturesIsSmmRegisterSupported ( IN SMM_REG_NAME RegName ) { - if (mSmmFeatureControlSupported && RegName == SmmRegFeatureControl) { - return TRUE; - } + ASSERT (RegName == SmmRegFeatureControl); return FALSE; } @@ -528,9 +329,11 @@ SmmCpuFeaturesGetSmmRegister ( IN SMM_REG_NAME RegName ) { - if (mSmmFeatureControlSupported && RegName == SmmRegFeatureControl) { - return AsmReadMsr64 (SMM_FEATURES_LIB_SMM_FEATURE_CONTROL); - } + // + // This is called for SmmRegSmmDelayed, SmmRegSmmBlocked, SmmRegSmmEnable. + // The last of these should actually be SmmRegSmmDisable, so we can just + // return FALSE. + // return 0; } @@ -553,9 +356,7 @@ SmmCpuFeaturesSetSmmRegister ( IN UINT64 Value ) { - if (mSmmFeatureControlSupported && RegName == SmmRegFeatureControl) { - AsmWriteMsr64 (SMM_FEATURES_LIB_SMM_FEATURE_CONTROL, Value); - } + ASSERT (FALSE); } /** diff --git a/OvmfPkg/Library/SmmCpuFeaturesLib/SmmCpuFeaturesLib.inf b/OvmfPkg/Library/SmmCpuFeaturesLib/SmmCpuFeaturesLib.inf index deb08bfe1d..aa4792c5f1 100644 --- a/OvmfPkg/Library/SmmCpuFeaturesLib/SmmCpuFeaturesLib.inf +++ b/OvmfPkg/Library/SmmCpuFeaturesLib/SmmCpuFeaturesLib.inf @@ -32,8 +32,4 @@ [LibraryClasses] BaseLib PcdLib - MemoryAllocationLib DebugLib - -[Pcd] - gUefiCpuPkgTokenSpaceGuid.PcdCpuMaxLogicalProcessorNumber ## SOMETIMES_CONSUMES