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IntelFrameworkModulePkg: Add IsaFloppyPei driver

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Signed-off-by: jljusten
Reviewed-by: mdkinney

git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@11845 6f19259b-4bc3-4df7-8a09-765794883524
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jljusten 2011-06-17 17:42:49 +00:00
parent a1e23d485b
commit d8387fa4af
6 changed files with 2325 additions and 0 deletions
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235
IntelFrameworkModulePkg/Bus/Isa/IsaFloppyPei/Fdc.h Normal file
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/** @file
Definition of FDC registers and structures.
Copyright (c) 2006 - 2010, Intel Corporation. All rights reserved.<BR>
This program and the accompanying materials
are licensed and made available under the terms and conditions
of the BSD License which accompanies this distribution. The
full text of the license may be found at
http://opensource.org/licenses/bsd-license.php
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
**/
#ifndef _PEI_RECOVERY_FDC_H_
#define _PEI_RECOVERY_FDC_H_
//
// FDC Registers
//
#define FDC_REGISTER_DOR 2 //Digital Output Register
#define FDC_REGISTER_MSR 4 //Main Status Register
#define FDC_REGISTER_DTR 5 //Data Register
#define FDC_REGISTER_CCR 7 //Configuration Control Register(data rate select)
#define FDC_REGISTER_DIR 7 //Digital Input Register(diskchange)
//
// FDC Register Bit Definitions
//
//
// Digital Out Register(WO)
//
#define SELECT_DRV BIT0 // Select Drive: 0=A 1=B
#define RESET_FDC BIT2 // Reset FDC
#define INT_DMA_ENABLE BIT3 // Enable Int & DMA
#define DRVA_MOTOR_ON BIT4 // Turn On Drive A Motor
#define DRVB_MOTOR_ON BIT5 // Turn On Drive B Motor
//
// Main Status Register(RO)
//
#define MSR_DAB BIT0 // Drive A Busy
#define MSR_DBB BIT1 // Drive B Busy
#define MSR_CB BIT4 // FDC Busy
#define MSR_NDM BIT5 // Non-DMA Mode
#define MSR_DIO BIT6 // Data Input/Output
#define MSR_RQM BIT7 // Request For Master
//
// Configuration Control Register(WO)
//
#define CCR_DRC (BIT0 | BIT1) // Data Rate select
//
// Digital Input Register(RO)
//
#define DIR_DCL BIT7 // Disk change line
#define DRC_500KBS 0x0 // 500K
#define DRC_300KBS 0x01 // 300K
#define DRC_250KBS 0x02 // 250K
//
// FDC Command Code
//
#define READ_DATA_CMD 0x06
#define SEEK_CMD 0x0F
#define RECALIBRATE_CMD 0x07
#define SENSE_INT_STATUS_CMD 0x08
#define SPECIFY_CMD 0x03
#define SENSE_DRV_STATUS_CMD 0x04
///
/// CMD_MT: Multi_Track Selector
/// when set , this flag selects the multi-track operating mode.
/// In this mode, the FDC treats a complete cylinder under head0 and 1 as a single track
///
#define CMD_MT BIT7
///
/// CMD_MFM: MFM/FM Mode Selector
/// A one selects the double density(MFM) mode
/// A zero selects single density (FM) mode
///
#define CMD_MFM BIT6
///
/// CMD_SK: Skip Flag
/// When set to 1, sectors containing a deleted data address mark will automatically be skipped
/// during the execution of Read Data.
/// When set to 0, the sector is read or written the same as the read and write commands.
///
#define CMD_SK BIT5
//
// FDC Status Register Bit Definitions
//
//
// Status Register 0
//
#define STS0_IC (BIT7 | BIT6) // Interrupt Code
#define STS0_SE BIT5 // Seek End: the FDC completed a seek or recalibrate command
#define STS0_EC BIT4 // Equipment Check
#define STS0_NR BIT3 // Not Ready(unused), this bit is always 0
#define STS0_HA BIT2 // Head Address: the current head address
//
// STS0_US1 & STS0_US0: Drive Select(the current selected drive)
//
#define STS0_US1 BIT1 // Unit Select1
#define STS0_US0 BIT0 // Unit Select0
//
// Status Register 1
//
#define STS1_EN BIT7 // End of Cylinder
//
// BIT6 is unused
//
#define STS1_DE BIT5 // Data Error: The FDC detected a CRC error in either the ID field or data field of a sector
#define STS1_OR BIT4 // Overrun/Underrun: Becomes set if FDC does not receive CPU or DMA service within the required time interval
//
// BIT3 is unused
//
#define STS1_ND BIT2 // No data
#define STS1_NW BIT1 // Not Writable
#define STS1_MA BIT0 // Missing Address Mark
//
// Status Register 2
//
// BIT7 is unused
//
#define STS2_CM BIT6 // Control Mark
#define STS2_DD BIT5 // Data Error in Data Field: The FDC detected a CRC error in the data field
#define STS2_WC BIT4 // Wrong Cylinder: The track address from sector ID field is different from the track address maintained inside FDC
//
// BIT3 is unused
// BIT2 is unused
//
#define STS2_BC BIT1 // Bad Cylinder
#define STS2_MD BIT0 // Missing Address Mark in DataField
//
// Status Register 3
//
// BIT7 is unused
//
#define STS3_WP BIT6 // Write Protected
//
// BIT5 is unused
//
#define STS3_T0 BIT4 // Track 0
//
// BIT3 is unused
//
#define STS3_HD BIT2 // Head Address
//
// STS3_US1 & STS3_US0 : Drive Select
//
#define STS3_US1 BIT1 // Unit Select1
#define STS3_US0 BIT0 // Unit Select0
//
// Status Register 0 Interrupt Code Description
//
#define IC_NT 0x0 // Normal Termination of Command
#define IC_AT 0x40 // Abnormal Termination of Command
#define IC_IC 0x80 // Invalid Command
#define IC_ATRC 0xC0 // Abnormal Termination caused by Polling
///
/// Table of parameters for diskette
///
typedef struct {
UINT8 EndOfTrack; ///< End of track
UINT8 GapLength; ///< Gap length
UINT8 DataLength; ///< Data length
UINT8 Number; ///< Number of bytes per sector
UINT8 MaxTrackNum;
UINT8 MotorStartTime;
UINT8 MotorOffTime;
UINT8 HeadSettlingTime;
UINT8 DataTransferRate;
} DISKET_PARA_TABLE;
///
/// Structure for FDC Command Packet 1
///
typedef struct {
UINT8 CommandCode;
UINT8 DiskHeadSel;
UINT8 Cylinder;
UINT8 Head;
UINT8 Sector;
UINT8 Number;
UINT8 EndOfTrack;
UINT8 GapLength;
UINT8 DataLength;
} FDC_COMMAND_PACKET1;
///
/// Structure for FDC Command Packet 2
///
typedef struct {
UINT8 CommandCode;
UINT8 DiskHeadSel;
} FDC_COMMAND_PACKET2;
///
/// Structure for FDC Specify Command
///
typedef struct {
UINT8 CommandCode;
UINT8 SrtHut;
UINT8 HltNd;
} FDC_SPECIFY_CMD;
///
/// Structure for FDC Seek Command
///
typedef struct {
UINT8 CommandCode;
UINT8 DiskHeadSel;
UINT8 NewCylinder;
} FDC_SEEK_CMD;
///
/// Structure for FDC Result Packet
///
typedef struct {
UINT8 Status0;
UINT8 Status1;
UINT8 Status2;
UINT8 CylinderNumber;
UINT8 HeaderAddress;
UINT8 Record;
UINT8 Number;
} FDC_RESULT_PACKET;
#endif

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IntelFrameworkModulePkg/Bus/Isa/IsaFloppyPei/FloppyPeim.c Normal file
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IntelFrameworkModulePkg/Bus/Isa/IsaFloppyPei/FloppyPeim.h Normal file
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/** @file
Private include file for IsaFloppyPei PEIM.
Copyright (c) 2006 - 2010, Intel Corporation. All rights reserved.<BR>
This program and the accompanying materials
are licensed and made available under the terms and conditions
of the BSD License which accompanies this distribution. The
full text of the license may be found at
http://opensource.org/licenses/bsd-license.php
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
**/
#ifndef _RECOVERY_FLOPPY_H_
#define _RECOVERY_FLOPPY_H_
#include <Ppi/BlockIo.h>
#include <Library/DebugLib.h>
#include <Library/PeimEntryPoint.h>
#include <Library/PeiServicesLib.h>
#include <Library/BaseMemoryLib.h>
#include <Library/ReportStatusCodeLib.h>
#include <Library/TimerLib.h>
#include <Library/IoLib.h>
#include <Library/MemoryAllocationLib.h>
#include <Library/PcdLib.h>
#include "Fdc.h"
//
// Some PC AT Compatible Device definitions
//
//
// 8237 DMA registers
//
#define R_8237_DMA_BASE_CA_CH0 0x00
#define R_8237_DMA_BASE_CA_CH1 0x02
#define R_8237_DMA_BASE_CA_CH2 0x04
#define R_8237_DMA_BASE_CA_CH3 0xd6
#define R_8237_DMA_BASE_CA_CH5 0xc4
#define R_8237_DMA_BASE_CA_CH6 0xc8
#define R_8237_DMA_BASE_CA_CH7 0xcc
#define R_8237_DMA_BASE_CC_CH0 0x01
#define R_8237_DMA_BASE_CC_CH1 0x03
#define R_8237_DMA_BASE_CC_CH2 0x05
#define R_8237_DMA_BASE_CC_CH3 0xd7
#define R_8237_DMA_BASE_CC_CH5 0xc6
#define R_8237_DMA_BASE_CC_CH6 0xca
#define R_8237_DMA_BASE_CC_CH7 0xce
#define R_8237_DMA_MEM_LP_CH0 0x87
#define R_8237_DMA_MEM_LP_CH1 0x83
#define R_8237_DMA_MEM_LP_CH2 0x81
#define R_8237_DMA_MEM_LP_CH3 0x82
#define R_8237_DMA_MEM_LP_CH5 0x8B
#define R_8237_DMA_MEM_LP_CH6 0x89
#define R_8237_DMA_MEM_LP_CH7 0x8A
#define R_8237_DMA_COMMAND_CH0_3 0x08
#define R_8237_DMA_COMMAND_CH4_7 0xd0
#define B_8237_DMA_COMMAND_GAP 0x10
#define B_8237_DMA_COMMAND_CGE 0x04
#define R_8237_DMA_STA_CH0_3 0x09
#define R_8237_DMA_STA_CH4_7 0xd2
#define R_8237_DMA_WRSMSK_CH0_3 0x0a
#define R_8237_DMA_WRSMSK_CH4_7 0xd4
#define B_8237_DMA_WRSMSK_CMS 0x04
#define R_8237_DMA_CHMODE_CH0_3 0x0b
#define R_8237_DMA_CHMODE_CH4_7 0xd6
#define V_8237_DMA_CHMODE_DEMAND 0x00
#define V_8237_DMA_CHMODE_SINGLE 0x40
#define V_8237_DMA_CHMODE_CASCADE 0xc0
#define B_8237_DMA_CHMODE_DECREMENT 0x20
#define B_8237_DMA_CHMODE_INCREMENT 0x00
#define B_8237_DMA_CHMODE_AE 0x10
#define V_8237_DMA_CHMODE_VERIFY 0
#define V_8237_DMA_CHMODE_IO2MEM 0x04
#define V_8237_DMA_CHMODE_MEM2IO 0x08
#define R_8237_DMA_CBPR_CH0_3 0x0c
#define R_8237_DMA_CBPR_CH4_7 0xd8
#define R_8237_DMA_MCR_CH0_3 0x0d
#define R_8237_DMA_MCR_CH4_7 0xda
#define R_8237_DMA_CLMSK_CH0_3 0x0e
#define R_8237_DMA_CLMSK_CH4_7 0xdc
#define R_8237_DMA_WRMSK_CH0_3 0x0f
#define R_8237_DMA_WRMSK_CH4_7 0xde
///
/// ISA memory range
///
#define ISA_MAX_MEMORY_ADDRESS 0x1000000
//
// Macro for time delay & interval
//
#define STALL_1_SECOND 1000000
#define STALL_1_MSECOND 1000
#define FDC_CHECK_INTERVAL 50
#define FDC_SHORT_DELAY 50
#define FDC_MEDIUM_DELAY 100
#define FDC_LONG_DELAY 4000
#define FDC_RESET_DELAY 2000
#define FDC_RECALIBRATE_DELAY 250000
typedef enum {
FdcType360K360K = 0,
FdcType360K1200K,
FdcType1200K1200K,
FdcType720K720K,
FdcType720K1440K,
FdcType1440K1440K,
FdcType720K2880K,
FdcType1440K2880K,
FdcType2880K2880K
} FDC_DISKET_TYPE;
typedef struct {
UINT8 Register;
UINT8 Value;
} PEI_DMA_TABLE;
typedef struct {
UINT8 DevPos;
UINT8 Pcn;
BOOLEAN MotorOn;
BOOLEAN NeedRecalibrate;
FDC_DISKET_TYPE Type;
EFI_PEI_BLOCK_IO_MEDIA MediaInfo;
} PEI_FLOPPY_DEVICE_INFO;
#define FDC_BLK_IO_DEV_SIGNATURE SIGNATURE_32 ('F', 'b', 'i', 'o')
typedef struct {
UINTN Signature;
EFI_PEI_RECOVERY_BLOCK_IO_PPI FdcBlkIo;
EFI_PEI_PPI_DESCRIPTOR PpiDescriptor;
UINTN DeviceCount;
PEI_FLOPPY_DEVICE_INFO DeviceInfo[2];
} FDC_BLK_IO_DEV;
#define PEI_RECOVERY_FDC_FROM_BLKIO_THIS(a) CR (a, FDC_BLK_IO_DEV, FdcBlkIo, FDC_BLK_IO_DEV_SIGNATURE)
//
// PEI Recovery Block I/O PPI
//
/**
Get the number of FDC devices.
This function implements EFI_PEI_RECOVERY_BLOCK_IO_PPI.GetNumberOfBlockDevices.
It get the number of FDC devices in the system.
@param PeiServices An indirect pointer to the PEI Services Table published by the PEI Foundation.
@param This Pointer to this PPI instance.
@param NumberBlockDevices Pointer to the the number of FDC devices for output.
@retval EFI_SUCCESS Number of FDC devices is retrieved successfully.
@retval EFI_INVALID_PARAMETER Parameter This is NULL.
**/
EFI_STATUS
EFIAPI
FdcGetNumberOfBlockDevices (
IN EFI_PEI_SERVICES **PeiServices,
IN EFI_PEI_RECOVERY_BLOCK_IO_PPI *This,
OUT UINTN *NumberBlockDevices
);
/**
Get the specified media information.
This function implements EFI_PEI_RECOVERY_BLOCK_IO_PPI.GetBlockDeviceMediaInfo.
It gets the specified media information.
@param PeiServices An indirect pointer to the PEI Services Table published by the PEI Foundation.
@param This Pointer to this PPI instance.
@param DeviceIndex Index of FDC device to get information.
@param MediaInfo Pointer to the media info buffer for output.
@retval EFI_SUCCESS Number of FDC devices is retrieved successfully.
@retval EFI_INVALID_PARAMETER Parameter This is NULL.
@retval EFI_INVALID_PARAMETER Parameter MediaInfo is NULL.
@retval EFI_INVALID_PARAMETER DeviceIndex is not valid.
@retval EFI_DEVICE_ERROR FDC device does not exist or has errors.
**/
EFI_STATUS
EFIAPI
FdcGetBlockDeviceMediaInfo (
IN EFI_PEI_SERVICES **PeiServices,
IN EFI_PEI_RECOVERY_BLOCK_IO_PPI *This,
IN UINTN DeviceIndex,
OUT EFI_PEI_BLOCK_IO_MEDIA *MediaInfo
);
/**
Get the requested number of blocks from the specified FDC device.
This function implements EFI_PEI_RECOVERY_BLOCK_IO_PPI.ReadBlocks.
It reads the requested number of blocks from the specified FDC device.
@param PeiServices An indirect pointer to the PEI Services Table published by the PEI Foundation.
@param This Pointer to this PPI instance.
@param DeviceIndex Index of FDC device to get information.
@param StartLba The start LBA to read from.
@param BufferSize The size of range to read.
@param Buffer Buffer to hold the data read from FDC.
@retval EFI_SUCCESS Number of FDC devices is retrieved successfully.
@retval EFI_INVALID_PARAMETER Parameter This is NULL.
@retval EFI_INVALID_PARAMETER Parameter Buffer is NULL.
@retval EFI_INVALID_PARAMETER Parameter BufferSize cannot be divided by block size of FDC device.
@retval EFI_NO_MEDIA No media present.
@retval EFI_DEVICE_ERROR FDC device has error.
@retval Others Fail to read blocks.
**/
EFI_STATUS
EFIAPI
FdcReadBlocks (
IN EFI_PEI_SERVICES **PeiServices,
IN EFI_PEI_RECOVERY_BLOCK_IO_PPI *This,
IN UINTN DeviceIndex,
IN EFI_PEI_LBA StartLba,
IN UINTN BufferSize,
OUT VOID *Buffer
);
#endif

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IntelFrameworkModulePkg/Bus/Isa/IsaFloppyPei/IsaFloppyPei.inf Normal file
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## @file
# ISA Floppy PEIM to support recovery boot via floppy disk.
#
# This module detects Floppy devices. If found, it will install BlockIo PPI.
# This module is only dispatched in Recovery Boot mode.
#
# Copyright (c) 2006 - 2011, Intel Corporation. All rights reserved.<BR>
#
# This program and the accompanying materials
# are licensed and made available under the terms and conditions
# of the BSD License which accompanies this distribution. The
# full text of the license may be found at
# http://opensource.org/licenses/bsd-license.php
#
# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
#
##
################################################################################
#
# Defines Section - statements that will be processed to create a Makefile.
#
################################################################################
[Defines]
INF_VERSION = 0x00010005
BASE_NAME = IsaFloppyPei
FILE_GUID = 7F6E0A24-DBFD-43df-9755-0292D7D3DD48
MODULE_TYPE = PEIM
VERSION_STRING = 1.0
ENTRY_POINT = FdcPeimEntry
#
# The following information is for reference only and not required by the build tools.
#
# VALID_ARCHITECTURES = IA32 X64 IPF EBC (EBC is for build only)
#
[Sources]
FloppyPeim.c
FloppyPeim.h
Fdc.h
[Packages]
IntelFrameworkModulePkg/IntelFrameworkModulePkg.dec
MdePkg/MdePkg.dec
[LibraryClasses]
IoLib
TimerLib
ReportStatusCodeLib
BaseMemoryLib
PeiServicesLib
PeimEntryPoint
DebugLib
MemoryAllocationLib
PcdLib
[Ppis]
gEfiPeiVirtualBlockIoPpiGuid # PPI ALWAYS_PRODUCED
[Pcd]
gEfiIntelFrameworkModulePkgTokenSpaceGuid.PcdFdcBaseAddress
[Depex]
gEfiPeiMemoryDiscoveredPpiGuid AND gEfiPeiBootInRecoveryModePpiGuid

6
IntelFrameworkModulePkg/IntelFrameworkModulePkg.dec
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@ -103,3 +103,9 @@
## Error level for hardware recorder. If value 0, platform does not support feature of hardware error record.
# This PCD should be set as HII type PCD by platform integrator mapped to variable L"HwErrRecSupport"
gEfiIntelFrameworkModulePkgTokenSpaceGuid.PcdHardwareErrorRecordLevel|0|UINT16|0x40000002
[PcdsFixedAtBuild, PcdsDynamic, PcdsDynamicEx, PcdsPatchableInModule]
## I/O Base address of floppy device controller.
gEfiIntelFrameworkModulePkgTokenSpaceGuid.PcdFdcBaseAddress|0x3f0|UINT16|0x30000000

2
IntelFrameworkModulePkg/IntelFrameworkModulePkg.dsc
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@ -68,6 +68,7 @@
DxeServicesTableLib|MdePkg/Library/DxeServicesTableLib/DxeServicesTableLib.inf
UefiRuntimeLib|MdePkg/Library/UefiRuntimeLib/UefiRuntimeLib.inf
PcdLib|MdePkg/Library/DxePcdLib/DxePcdLib.inf
IoLib|MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsic.inf
[LibraryClasses.common.PEIM]
HobLib|MdePkg/Library/PeiHobLib/PeiHobLib.inf
@ -130,6 +131,7 @@
IntelFrameworkModulePkg/Bus/Pci/IdeBusDxe/IdeBusDxe.inf
IntelFrameworkModulePkg/Bus/Isa/IsaBusDxe/IsaBusDxe.inf
IntelFrameworkModulePkg/Bus/Isa/IsaIoDxe/IsaIoDxe.inf
IntelFrameworkModulePkg/Bus/Isa/IsaFloppyPei/IsaFloppyPei.inf
IntelFrameworkModulePkg/Bus/Isa/IsaFloppyDxe/IsaFloppyDxe.inf
IntelFrameworkModulePkg/Bus/Isa/IsaSerialDxe/IsaSerialDxe.inf
IntelFrameworkModulePkg/Bus/Isa/Ps2KeyboardDxe/Ps2keyboardDxe.inf