mirror of https://github.com/acidanthera/audk.git
ArmPkg/CpuDxe: drop ARMv4 exception handling code
Since we do not support anything below ARMv7, let's promote the ARMv6 exception handling code in CpuDxe to the only version we provide for ARM. This means we can drop the unused ARMv4 version. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@19273 6f19259b-4bc3-4df7-8a09-765794883524
This commit is contained in:
Ard Biesheuvel
abiesheuvel
parent
e59a797ffb
commit
d9ac8a4576
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@ -1,191 +0,0 @@
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#------------------------------------------------------------------------------
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#
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# Copyright (c) 2008 - 2010, Apple Inc. All rights reserved.<BR>
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#
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# This program and the accompanying materials
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# are licensed and made available under the terms and conditions of the BSD License
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# which accompanies this distribution. The full text of the license may be found at
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# http://opensource.org/licenses/bsd-license.php
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#
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# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
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# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
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#
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#------------------------------------------------------------------------------
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.text
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.align 3
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GCC_ASM_EXPORT(ExceptionHandlersStart)
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GCC_ASM_EXPORT(ExceptionHandlersEnd)
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GCC_ASM_EXPORT(CommonExceptionEntry)
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GCC_ASM_EXPORT(AsmCommonExceptionEntry)
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GCC_ASM_EXPORT(CommonCExceptionHandler)
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ASM_PFX(ExceptionHandlersStart):
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ASM_PFX(Reset):
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b ASM_PFX(ResetEntry)
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ASM_PFX(UndefinedInstruction):
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b ASM_PFX(UndefinedInstructionEntry)
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ASM_PFX(SoftwareInterrupt):
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b ASM_PFX(SoftwareInterruptEntry)
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ASM_PFX(PrefetchAbort):
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b ASM_PFX(PrefetchAbortEntry)
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ASM_PFX(DataAbort):
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b ASM_PFX(DataAbortEntry)
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ASM_PFX(ReservedException):
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b ASM_PFX(ReservedExceptionEntry)
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ASM_PFX(Irq):
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b ASM_PFX(IrqEntry)
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ASM_PFX(Fiq):
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b ASM_PFX(FiqEntry)
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ASM_PFX(ResetEntry):
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srsdb #0x13! @ Store return state on SVC stack
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stmfd SP!,{LR} @ Store the link register for the current mode
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sub SP,SP,#0x20 @ Save space for SP, LR, PC, IFAR - CPSR
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stmfd SP!,{R0-R12} @ Store the register state
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mov R0,#0
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ldr R1,ASM_PFX(CommonExceptionEntry)
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bx R1
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ASM_PFX(UndefinedInstructionEntry):
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srsdb #0x13! @ Store return state on SVC stack
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cps #0x13 @ Switch to SVC for common stack
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stmfd SP!,{LR} @ Store the link register for the current mode
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sub SP,SP,#0x20 @ Save space for SP, LR, PC, IFAR - CPSR
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stmfd SP!,{R0-R12} @ Store the register state
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mov r0,#1
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ldr r1,ASM_PFX(CommonExceptionEntry)
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bx r1
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ASM_PFX(SoftwareInterruptEntry):
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srsdb #0x13! @ Store return state on SVC stack
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stmfd SP!,{LR} @ Store the link register for the current mode
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sub SP,SP,#0x20 @ Save space for SP, LR, PC, IFAR - CPSR
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stmfd SP!,{R0-R12} @ Store the register state
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mov r0,#2
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ldr r1,ASM_PFX(CommonExceptionEntry)
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bx r1
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ASM_PFX(PrefetchAbortEntry):
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sub LR,LR,#4
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srsdb #0x13! @ Store return state on SVC stack
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cps #0x13 @ Switch to SVC for common stack
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stmfd SP!,{LR} @ Store the link register for the current mode
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sub SP,SP,#0x20 @ Save space for SP, LR, PC, IFAR - CPSR
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stmfd SP!,{R0-R12} @ Store the register state
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mov r0,#3
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ldr r1,ASM_PFX(CommonExceptionEntry)
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bx r1
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ASM_PFX(DataAbortEntry):
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sub LR,LR,#8
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srsdb #0x13! @ Store return state on SVC stack
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cps #0x13 @ Switch to SVC for common stack
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stmfd SP!,{LR} @ Store the link register for the current mode
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sub SP,SP,#0x20 @ Save space for SP, LR, PC, IFAR - CPSR
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stmfd SP!,{R0-R12} @ Store the register state
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mov r0,#4
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ldr r1,ASM_PFX(CommonExceptionEntry)
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bx r1
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ASM_PFX(ReservedExceptionEntry):
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srsdb #0x13! @ Store return state on SVC stack
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cps #0x13 @ Switch to SVC for common stack
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stmfd SP!,{LR} @ Store the link register for the current mode
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sub SP,SP,#0x20 @ Save space for SP, LR, PC, IFAR - CPSR
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stmfd SP!,{R0-R12} @ Store the register state
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mov r0,#5
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ldr r1,ASM_PFX(CommonExceptionEntry)
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bx r1
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ASM_PFX(IrqEntry):
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sub LR,LR,#4
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srsdb #0x13! @ Store return state on SVC stack
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cps #0x13 @ Switch to SVC for common stack
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stmfd SP!,{LR} @ Store the link register for the current mode
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sub SP,SP,#0x20 @ Save space for SP, LR, PC, IFAR - CPSR
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stmfd SP!,{R0-R12} @ Store the register state
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mov r0,#6
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ldr r1,ASM_PFX(CommonExceptionEntry)
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bx r1
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ASM_PFX(FiqEntry):
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sub LR,LR,#4
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srsdb #0x13! @ Store return state on SVC stack
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cps #0x13 @ Switch to SVC for common stack
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stmfd SP!,{LR} @ Store the link register for the current mode
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sub SP,SP,#0x20 @ Save space for SP, LR, PC, IFAR - CPSR
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stmfd SP!,{R0-R12} @ Store the register state
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mov r0,#7
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ldr r1,ASM_PFX(CommonExceptionEntry)
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bx r1
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ASM_PFX(CommonExceptionEntry):
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.byte 0x12
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.byte 0x34
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.byte 0x56
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.byte 0x78
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ASM_PFX(ExceptionHandlersEnd):
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ASM_PFX(AsmCommonExceptionEntry):
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mrc p15, 0, R1, c6, c0, 2 @ Read IFAR
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str R1, [SP, #0x50] @ Store it in EFI_SYSTEM_CONTEXT_ARM.IFAR
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mrc p15, 0, R1, c5, c0, 1 @ Read IFSR
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str R1, [SP, #0x4c] @ Store it in EFI_SYSTEM_CONTEXT_ARM.IFSR
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mrc p15, 0, R1, c6, c0, 0 @ Read DFAR
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str R1, [SP, #0x48] @ Store it in EFI_SYSTEM_CONTEXT_ARM.DFAR
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mrc p15, 0, R1, c5, c0, 0 @ Read DFSR
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str R1, [SP, #0x44] @ Store it in EFI_SYSTEM_CONTEXT_ARM.DFSR
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ldr R1, [SP, #0x5c] @ srsdb saved pre-exception CPSR on the stack
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str R1, [SP, #0x40] @ Store it in EFI_SYSTEM_CONTEXT_ARM.CPSR
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and r1, r1, #0x1f @ Check to see if User or System Mode
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cmp r1, #0x1f
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cmpne r1, #0x10
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add R2, SP, #0x38 @ Store it in EFI_SYSTEM_CONTEXT_ARM.LR
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ldmneed r2, {lr}^ @ User or System mode, use unbanked register
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ldmneed r2, {lr} @ All other modes used banked register
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ldr R1, [SP, #0x58] @ PC is the LR pushed by srsdb
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str R1, [SP, #0x3c] @ Store it in EFI_SYSTEM_CONTEXT_ARM.PC
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sub R1, SP, #0x60 @ We pused 0x60 bytes on the stack
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str R1, [SP, #0x34] @ Store it in EFI_SYSTEM_CONTEXT_ARM.SP
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@ R0 is exception type
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mov R1,SP @ Prepare System Context pointer as an argument for the exception handler
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blx ASM_PFX(CommonCExceptionHandler) @ Call exception handler
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ldr R2,[SP,#0x40] @ EFI_SYSTEM_CONTEXT_ARM.CPSR
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str R2,[SP,#0x5c] @ Store it back to srsdb stack slot so it can be restored
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ldr R2,[SP,#0x3c] @ EFI_SYSTEM_CONTEXT_ARM.PC
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str R2,[SP,#0x58] @ Store it back to srsdb stack slot so it can be restored
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ldmfd SP!,{R0-R12} @ Restore general purpose registers
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@ Exception handler can not change SP or LR as we would blow chunks
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add SP,SP,#0x20 @ Clear out the remaining stack space
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ldmfd SP!,{LR} @ restore the link register for this context
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rfefd SP! @ return from exception via srsdb stack slot
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@ -1,152 +0,0 @@
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//------------------------------------------------------------------------------
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//
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// Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
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//
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// This program and the accompanying materials
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// are licensed and made available under the terms and conditions of the BSD License
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// which accompanies this distribution. The full text of the license may be found at
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// http://opensource.org/licenses/bsd-license.php
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//
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// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
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// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
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//
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//------------------------------------------------------------------------------
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EXPORT ExceptionHandlersStart
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EXPORT ExceptionHandlersEnd
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EXPORT CommonExceptionEntry
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EXPORT AsmCommonExceptionEntry
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IMPORT CommonCExceptionHandler
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PRESERVE8
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AREA DxeExceptionHandlers, CODE, READONLY
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ExceptionHandlersStart
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Reset
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b ResetEntry
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UndefinedInstruction
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b UndefinedInstructionEntry
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SoftwareInterrupt
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b SoftwareInterruptEntry
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PrefetchAbort
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b PrefetchAbortEntry
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DataAbort
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b DataAbortEntry
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ReservedException
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b ReservedExceptionEntry
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Irq
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b IrqEntry
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Fiq
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b FiqEntry
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ResetEntry
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stmfd SP!,{R0-R1}
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mov R0,#0
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ldr R1,CommonExceptionEntry
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bx R1
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UndefinedInstructionEntry
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stmfd SP!,{R0-R1}
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mov R0,#1
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ldr R1,CommonExceptionEntry
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bx R1
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SoftwareInterruptEntry
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stmfd SP!,{R0-R1}
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mov R0,#2
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ldr R1,CommonExceptionEntry
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bx R1
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PrefetchAbortEntry
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stmfd SP!,{R0-R1}
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mov R0,#3
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SUB LR,LR,#4
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ldr R1,CommonExceptionEntry
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bx R1
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DataAbortEntry
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stmfd SP!,{R0-R1}
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mov R0,#4
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SUB LR,LR,#8
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ldr R1,CommonExceptionEntry
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bx R1
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ReservedExceptionEntry
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stmfd SP!,{R0-R1}
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mov R0,#5
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ldr R1,CommonExceptionEntry
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bx R1
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IrqEntry
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stmfd SP!,{R0-R1}
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mov R0,#6
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SUB LR,LR,#4
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ldr R1,CommonExceptionEntry
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bx R1
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FiqEntry
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stmfd SP!,{R0-R1}
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mov R0,#7
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SUB LR,LR,#4
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ldr R1,CommonExceptionEntry
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bx R1
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CommonExceptionEntry
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dcd 0x12345678
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ExceptionHandlersEnd
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AsmCommonExceptionEntry
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mrc p15, 0, r1, c6, c0, 2 ; Read IFAR
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stmfd SP!,{R1} ; Store the IFAR
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mrc p15, 0, r1, c5, c0, 1 ; Read IFSR
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stmfd SP!,{R1} ; Store the IFSR
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mrc p15, 0, r1, c6, c0, 0 ; Read DFAR
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stmfd SP!,{R1} ; Store the DFAR
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mrc p15, 0, r1, c5, c0, 0 ; Read DFSR
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stmfd SP!,{R1} ; Store the DFSR
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mrs R1,SPSR ; Read SPSR (which is the pre-exception CPSR)
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stmfd SP!,{R1} ; Store the SPSR
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stmfd SP!,{LR} ; Store the link register (which is the pre-exception PC)
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stmfd SP,{SP,LR}^ ; Store user/system mode stack pointer and link register
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nop ; Required by ARM architecture
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SUB SP,SP,#0x08 ; Adjust stack pointer
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stmfd SP!,{R2-R12} ; Store general purpose registers
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ldr R3,[SP,#0x50] ; Read saved R1 from the stack (it was saved by the exception entry routine)
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ldr R2,[SP,#0x4C] ; Read saved R0 from the stack (it was saved by the exception entry routine)
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stmfd SP!,{R2-R3} ; Store general purpose registers R0 and R1
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mov R1,SP ; Prepare System Context pointer as an argument for the exception handler
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sub SP,SP,#4 ; Adjust SP to preserve 8-byte alignment
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blx CommonCExceptionHandler ; Call exception handler
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add SP,SP,#4 ; Adjust SP back to where we were
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ldr R2,[SP,#0x40] ; Load CPSR from context, in case it has changed
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MSR SPSR_cxsf,R2 ; Store it back to the SPSR to be restored when exiting this handler
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ldmfd SP!,{R0-R12} ; Restore general purpose registers
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ldm SP,{SP,LR}^ ; Restore user/system mode stack pointer and link register
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nop ; Required by ARM architecture
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add SP,SP,#0x08 ; Adjust stack pointer
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ldmfd SP!,{LR} ; Restore the link register (which is the pre-exception PC)
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add SP,SP,#0x1C ; Clear out the remaining stack space
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movs PC,LR ; Return from exception
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END
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@ -30,21 +30,11 @@
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CpuMpCore.c
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CpuMpCore.c
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CpuMmuCommon.c
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CpuMmuCommon.c
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#
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# Prior to ARMv6 we have multiple stacks, one per mode
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#
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# ArmV4/ExceptionSupport.asm | RVCT
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# ArmV4/ExceptionSupport.S | GCC
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#
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# ARMv6 or later uses a single stack via srs/stm instructions
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#
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[Sources.ARM]
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[Sources.ARM]
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ArmV6/Mmu.c
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Arm/Mmu.c
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ArmV6/Exception.c
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Arm/Exception.c
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ArmV6/ExceptionSupport.asm | RVCT
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Arm/ExceptionSupport.asm | RVCT
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ArmV6/ExceptionSupport.S | GCC
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Arm/ExceptionSupport.S | GCC
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[Sources.AARCH64]
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[Sources.AARCH64]
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AArch64/Mmu.c
|
AArch64/Mmu.c
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Reference in New Issue