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MdePkg/Library/BaseLib: Enable VS2017/ARM64 builds
Required GCC assembly files are converted for the MSFT assembler Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Pete Batard <pete@akeo.ie> Reviewed-by: Liming Gao <liming.gao@intel.com>
This commit is contained in:
Pete Batard
Liming Gao
parent
9033652979
commit
da351bdbe2
39
MdePkg/Library/BaseLib/AArch64/CpuBreakpoint.asm
Normal file
39
MdePkg/Library/BaseLib/AArch64/CpuBreakpoint.asm
Normal file
@ -0,0 +1,39 @@
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;------------------------------------------------------------------------------
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;
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; CpuBreakpoint() for AArch64
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;
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; Copyright (c) 2006 - 2009, Intel Corporation. All rights reserved.<BR>
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; Portions copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
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; Portions copyright (c) 2011 - 2013, ARM Ltd. All rights reserved.<BR>
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; This program and the accompanying materials
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; are licensed and made available under the terms and conditions of the BSD License
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; which accompanies this distribution. The full text of the license may be found at
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; http://opensource.org/licenses/bsd-license.php.
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;
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; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
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; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
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;
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;------------------------------------------------------------------------------
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EXPORT CpuBreakpoint
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AREA BaseLib_LowLevel, CODE, READONLY
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;/**
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; Generates a breakpoint on the CPU.
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;
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; Generates a breakpoint on the CPU. The breakpoint must be implemented such
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; that code can resume normal execution after the breakpoint.
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;
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;**/
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;VOID
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;EFIAPI
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;CpuBreakpoint (
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; VOID
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; );
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;
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CpuBreakpoint
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svc 0xdbdb // Superviser exception. Takes 16bit arg -> Armv7 had 'swi' here.
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ret
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END
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37
MdePkg/Library/BaseLib/AArch64/DisableInterrupts.asm
Normal file
37
MdePkg/Library/BaseLib/AArch64/DisableInterrupts.asm
Normal file
@ -0,0 +1,37 @@
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;------------------------------------------------------------------------------
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;
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; DisableInterrupts() for AArch64
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;
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; Copyright (c) 2006 - 2009, Intel Corporation. All rights reserved.<BR>
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; Portions copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
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; Portions copyright (c) 2011 - 2013, ARM Ltd. All rights reserved.<BR>
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; This program and the accompanying materials
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; are licensed and made available under the terms and conditions of the BSD License
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; which accompanies this distribution. The full text of the license may be found at
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; http://opensource.org/licenses/bsd-license.php.
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;
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; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
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; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
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;
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;------------------------------------------------------------------------------
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EXPORT DisableInterrupts
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AREA BaseLib_LowLevel, CODE, READONLY
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DAIF_WR_IRQ_BIT EQU (1 << 1)
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;/**
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; Disables CPU interrupts.
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;
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;**/
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;VOID
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;EFIAPI
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;DisableInterrupts (
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; VOID
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; );
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;
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DisableInterrupts
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msr daifset, #DAIF_WR_IRQ_BIT
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ret
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END
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37
MdePkg/Library/BaseLib/AArch64/EnableInterrupts.asm
Normal file
37
MdePkg/Library/BaseLib/AArch64/EnableInterrupts.asm
Normal file
@ -0,0 +1,37 @@
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;------------------------------------------------------------------------------
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;
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; EnableInterrupts() for AArch64
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;
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; Copyright (c) 2006 - 2009, Intel Corporation. All rights reserved.<BR>
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; Portions copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
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; Portions copyright (c) 2011 - 2013, ARM Ltd. All rights reserved.<BR>
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; This program and the accompanying materials
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; are licensed and made available under the terms and conditions of the BSD License
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; which accompanies this distribution. The full text of the license may be found at
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; http://opensource.org/licenses/bsd-license.php.
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;
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; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
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; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
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;
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;------------------------------------------------------------------------------
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EXPORT EnableInterrupts
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AREA BaseLib_LowLevel, CODE, READONLY
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DAIF_WR_IRQ_BIT EQU (1 << 1)
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;/**
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; Enables CPU interrupts.
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;
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;**/
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;VOID
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;EFIAPI
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;EnableInterrupts (
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; VOID
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; );
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;
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EnableInterrupts
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msr daifclr, #DAIF_WR_IRQ_BIT
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ret
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END
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49
MdePkg/Library/BaseLib/AArch64/GetInterruptsState.asm
Normal file
49
MdePkg/Library/BaseLib/AArch64/GetInterruptsState.asm
Normal file
@ -0,0 +1,49 @@
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;------------------------------------------------------------------------------
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;
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; GetInterruptState() function for AArch64
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;
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; Copyright (c) 2006 - 2009, Intel Corporation. All rights reserved.<BR>
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; Portions copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
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; Portions copyright (c) 2011 - 2013, ARM Ltd. All rights reserved.<BR>
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; This program and the accompanying materials
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; are licensed and made available under the terms and conditions of the BSD License
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; which accompanies this distribution. The full text of the license may be found at
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; http://opensource.org/licenses/bsd-license.php.
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;
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; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
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; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
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;
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;------------------------------------------------------------------------------
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EXPORT GetInterruptState
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AREA BaseLib_LowLevel, CODE, READONLY
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DAIF_RD_IRQ_BIT EQU (1 << 7)
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;/**
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; Retrieves the current CPU interrupt state.
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;
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; Returns TRUE is interrupts are currently enabled. Otherwise
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; returns FALSE.
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;
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; @retval TRUE CPU interrupts are enabled.
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; @retval FALSE CPU interrupts are disabled.
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;
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;**/
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;
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;BOOLEAN
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;EFIAPI
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;GetInterruptState (
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; VOID
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; );
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;
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GetInterruptState
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mrs x0, daif
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mov w0, wzr
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tst x0, #DAIF_RD_IRQ_BIT // Check IRQ mask; set Z=1 if clear/unmasked
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bne exit // if Z=1 (eq) return 1, else 0
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mov w0, #1
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exit
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ret
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END
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38
MdePkg/Library/BaseLib/AArch64/MemoryFence.asm
Normal file
38
MdePkg/Library/BaseLib/AArch64/MemoryFence.asm
Normal file
@ -0,0 +1,38 @@
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;------------------------------------------------------------------------------
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;
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; MemoryFence() for AArch64
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;
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; Copyright (c) 2013, ARM Ltd. All rights reserved.
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;
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; This program and the accompanying materials
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; are licensed and made available under the terms and conditions of the BSD License
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; which accompanies this distribution. The full text of the license may be found at
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; http://opensource.org/licenses/bsd-license.php.
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;
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; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
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; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
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;
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;------------------------------------------------------------------------------
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EXPORT MemoryFence
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AREA BaseLib_LowLevel, CODE, READONLY
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;/**
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; Used to serialize load and store operations.
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;
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; All loads and stores that proceed calls to this function are guaranteed to be
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; globally visible when this function returns.
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;
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;**/
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;VOID
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;EFIAPI
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;MemoryFence (
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; VOID
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; );
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;
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MemoryFence
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// System wide Data Memory Barrier.
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dmb sy
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ret
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END
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101
MdePkg/Library/BaseLib/AArch64/SetJumpLongJump.asm
Normal file
101
MdePkg/Library/BaseLib/AArch64/SetJumpLongJump.asm
Normal file
@ -0,0 +1,101 @@
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;------------------------------------------------------------------------------
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;
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; Copyright (c) 2009-2013, ARM Ltd. All rights reserved.
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; This program and the accompanying materials
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; are licensed and made available under the terms and conditions of the BSD License
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; which accompanies this distribution. The full text of the license may be found at
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; http://opensource.org/licenses/bsd-license.php.
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;
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; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
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; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
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;
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;------------------------------------------------------------------------------
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EXPORT SetJump
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EXPORT InternalLongJump
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AREA BaseLib_LowLevel, CODE, READONLY
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#define GPR_LAYOUT \
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REG_PAIR (x19, x20, #0); \
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REG_PAIR (x21, x22, #16); \
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REG_PAIR (x23, x24, #32); \
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REG_PAIR (x25, x26, #48); \
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REG_PAIR (x27, x28, #64); \
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REG_PAIR (x29, x30, #80);/*FP, LR*/ \
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REG_ONE (x16, #96) /*IP0*/
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#define FPR_LAYOUT \
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REG_PAIR ( d8, d9, #112); \
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REG_PAIR (d10, d11, #128); \
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REG_PAIR (d12, d13, #144); \
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REG_PAIR (d14, d15, #160);
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|
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;/**
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; Saves the current CPU context that can be restored with a call to LongJump() and returns 0.#
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|
;
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; Saves the current CPU context in the buffer specified by JumpBuffer and returns 0. The initial
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|
; call to SetJump() must always return 0. Subsequent calls to LongJump() cause a non-zero
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||||||
|
; value to be returned by SetJump().
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|
;
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||||||
|
; If JumpBuffer is NULL, then ASSERT().
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||||||
|
; For IPF CPUs, if JumpBuffer is not aligned on a 16-byte boundary, then ASSERT().
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|
;
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||||||
|
; @param JumpBuffer A pointer to CPU context buffer.
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|
;
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||||||
|
;**/
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||||||
|
;
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|
;UINTN
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|
;EFIAPI
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|
;SetJump (
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||||||
|
; IN BASE_LIBRARY_JUMP_BUFFER *JumpBuffer // X0
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|
; );
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||||||
|
;
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|
SetJump
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|
mov x16, sp // use IP0 so save SP
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||||||
|
#define REG_PAIR(REG1, REG2, OFFS) stp REG1, REG2, [x0, OFFS]
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|
#define REG_ONE(REG1, OFFS) str REG1, [x0, OFFS]
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|
GPR_LAYOUT
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|
FPR_LAYOUT
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||||||
|
#undef REG_PAIR
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||||||
|
#undef REG_ONE
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||||||
|
mov w0, #0
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||||||
|
ret
|
||||||
|
|
||||||
|
;/**
|
||||||
|
; Restores the CPU context that was saved with SetJump().#
|
||||||
|
;
|
||||||
|
; Restores the CPU context from the buffer specified by JumpBuffer.
|
||||||
|
; This function never returns to the caller.
|
||||||
|
; Instead is resumes execution based on the state of JumpBuffer.
|
||||||
|
;
|
||||||
|
; @param JumpBuffer A pointer to CPU context buffer.
|
||||||
|
; @param Value The value to return when the SetJump() context is restored.
|
||||||
|
;
|
||||||
|
;**/
|
||||||
|
;VOID
|
||||||
|
;EFIAPI
|
||||||
|
;InternalLongJump (
|
||||||
|
; IN BASE_LIBRARY_JUMP_BUFFER *JumpBuffer, // X0
|
||||||
|
; IN UINTN Value // X1
|
||||||
|
; );
|
||||||
|
;
|
||||||
|
InternalLongJump
|
||||||
|
#define REG_PAIR(REG1, REG2, OFFS) ldp REG1, REG2, [x0, OFFS]
|
||||||
|
#define REG_ONE(REG1, OFFS) ldr REG1, [x0, OFFS]
|
||||||
|
GPR_LAYOUT
|
||||||
|
FPR_LAYOUT
|
||||||
|
#undef REG_PAIR
|
||||||
|
#undef REG_ONE
|
||||||
|
mov sp, x16
|
||||||
|
cmp w1, #0
|
||||||
|
mov w0, #1
|
||||||
|
beq exit
|
||||||
|
mov w0, w1
|
||||||
|
exit
|
||||||
|
// use br not ret, as ret is guaranteed to mispredict
|
||||||
|
br x30
|
||||||
|
|
||||||
|
ASM_FUNCTION_REMOVE_IF_UNREFERENCED
|
||||||
|
|
||||||
|
END
|
||||||
|
|
||||||
69
MdePkg/Library/BaseLib/AArch64/SwitchStack.asm
Normal file
69
MdePkg/Library/BaseLib/AArch64/SwitchStack.asm
Normal file
@ -0,0 +1,69 @@
|
|||||||
|
//------------------------------------------------------------------------------
|
||||||
|
//
|
||||||
|
// Copyright (c) 2006 - 2009, Intel Corporation. All rights reserved.<BR>
|
||||||
|
// Portions copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
|
||||||
|
// Portions copyright (c) 2011 - 2013, ARM Limited. All rights reserved.<BR>
|
||||||
|
// This program and the accompanying materials
|
||||||
|
// are licensed and made available under the terms and conditions of the BSD License
|
||||||
|
// which accompanies this distribution. The full text of the license may be found at
|
||||||
|
// http://opensource.org/licenses/bsd-license.php.
|
||||||
|
//
|
||||||
|
// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
|
||||||
|
// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
|
||||||
|
//
|
||||||
|
//------------------------------------------------------------------------------
|
||||||
|
|
||||||
|
EXPORT InternalSwitchStackAsm
|
||||||
|
EXPORT CpuPause
|
||||||
|
AREA BaseLib_LowLevel, CODE, READONLY
|
||||||
|
|
||||||
|
/**
|
||||||
|
//
|
||||||
|
// This allows the caller to switch the stack and goes to the new entry point
|
||||||
|
//
|
||||||
|
// @param EntryPoint The pointer to the location to enter
|
||||||
|
// @param Context Parameter to pass in
|
||||||
|
// @param Context2 Parameter2 to pass in
|
||||||
|
// @param NewStack New Location of the stack
|
||||||
|
//
|
||||||
|
// @return Nothing. Goes to the Entry Point passing in the new parameters
|
||||||
|
//
|
||||||
|
VOID
|
||||||
|
EFIAPI
|
||||||
|
InternalSwitchStackAsm (
|
||||||
|
SWITCH_STACK_ENTRY_POINT EntryPoint,
|
||||||
|
VOID *Context,
|
||||||
|
VOID *Context2,
|
||||||
|
VOID *NewStack
|
||||||
|
);
|
||||||
|
**/
|
||||||
|
InternalSwitchStackAsm
|
||||||
|
mov x29, #0
|
||||||
|
mov x30, x0
|
||||||
|
mov sp, x3
|
||||||
|
mov x0, x1
|
||||||
|
mov x1, x2
|
||||||
|
ret
|
||||||
|
|
||||||
|
/**
|
||||||
|
//
|
||||||
|
// Requests CPU to pause for a short period of time.
|
||||||
|
//
|
||||||
|
// Requests CPU to pause for a short period of time. Typically used in MP
|
||||||
|
// systems to prevent memory starvation while waiting for a spin lock.
|
||||||
|
//
|
||||||
|
VOID
|
||||||
|
EFIAPI
|
||||||
|
CpuPause (
|
||||||
|
VOID
|
||||||
|
)
|
||||||
|
**/
|
||||||
|
CpuPause
|
||||||
|
nop
|
||||||
|
nop
|
||||||
|
nop
|
||||||
|
nop
|
||||||
|
nop
|
||||||
|
ret
|
||||||
|
|
||||||
|
END
|
||||||
@ -867,6 +867,14 @@
|
|||||||
AArch64/SetJumpLongJump.S | GCC
|
AArch64/SetJumpLongJump.S | GCC
|
||||||
AArch64/CpuBreakpoint.S | GCC
|
AArch64/CpuBreakpoint.S | GCC
|
||||||
|
|
||||||
|
AArch64/MemoryFence.asm | MSFT
|
||||||
|
AArch64/SwitchStack.asm | MSFT
|
||||||
|
AArch64/EnableInterrupts.asm | MSFT
|
||||||
|
AArch64/DisableInterrupts.asm | MSFT
|
||||||
|
AArch64/GetInterruptsState.asm | MSFT
|
||||||
|
AArch64/SetJumpLongJump.asm | MSFT
|
||||||
|
AArch64/CpuBreakpoint.asm | MSFT
|
||||||
|
|
||||||
[Packages]
|
[Packages]
|
||||||
MdePkg/MdePkg.dec
|
MdePkg/MdePkg.dec
|
||||||
|
|
||||||
|
|||||||
Loading…
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Reference in New Issue
Block a user