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OvmfPkg: consolidate POWER_MGMT_REGISTER_PIIX4() on "I440FxPiix4.h" macros 

All POWER_MGMT_REGISTER_PIIX4() macro invocations in OvmfPkg should use
the macros in "I440FxPiix4.h" as arguments.

Cc: Gabriel Somlo <somlo@cmu.edu>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Laszlo Ersek <lersek@redhat.com>
Acked-by: Gabriel Somlo <somlo@cmu.edu>
Tested-by: Gabriel Somlo <somlo@cmu.edu>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>

git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@17435 6f19259b-4bc3-4df7-8a09-765794883524
This commit is contained in:
Laszlo Ersek 2015-05-13 09:31:49 +00:00 committed by lersek
parent bc9d05d6f2
commit da37216768
5 changed files with 12 additions and 14 deletions
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7
OvmfPkg/Library/AcpiTimerLib/BaseAcpiTimerLib.c
View File

@ -22,7 +22,6 @@
// Power Management PCI Configuration Register fields // Power Management PCI Configuration Register fields
// //
#define PMBA_RTE BIT0 #define PMBA_RTE BIT0
#define PIIX4_PMIOSE BIT0
// //
// Offset in the Power Management Base Address to the ACPI Timer // Offset in the Power Management Base Address to the ACPI Timer
@ -58,9 +57,9 @@ AcpiTimerLibConstructor (
HostBridgeDevId = PciRead16 (OVMF_HOSTBRIDGE_DID); HostBridgeDevId = PciRead16 (OVMF_HOSTBRIDGE_DID);
switch (HostBridgeDevId) { switch (HostBridgeDevId) {
case INTEL_82441_DEVICE_ID: case INTEL_82441_DEVICE_ID:
Pmba = POWER_MGMT_REGISTER_PIIX4 (0x40); Pmba = POWER_MGMT_REGISTER_PIIX4 (PIIX4_PMBA);
AcpiCtlReg = POWER_MGMT_REGISTER_PIIX4 (0x80); // PMREGMISC AcpiCtlReg = POWER_MGMT_REGISTER_PIIX4 (PIIX4_PMREGMISC);
AcpiEnBit = PIIX4_PMIOSE; AcpiEnBit = PIIX4_PMREGMISC_PMIOSE;
break; break;
case INTEL_Q35_MCH_DEVICE_ID: case INTEL_Q35_MCH_DEVICE_ID:
Pmba = POWER_MGMT_REGISTER_Q35 (ICH9_PMBASE); Pmba = POWER_MGMT_REGISTER_Q35 (ICH9_PMBASE);

9
OvmfPkg/Library/AcpiTimerLib/BaseRomAcpiTimerLib.c
View File

@ -23,7 +23,6 @@
// Power Management PCI Configuration Register fields // Power Management PCI Configuration Register fields
// //
#define PMBA_RTE BIT0 #define PMBA_RTE BIT0
#define PIIX4_PMIOSE BIT0
// //
// Offset in the Power Management Base Address to the ACPI Timer // Offset in the Power Management Base Address to the ACPI Timer
@ -56,9 +55,9 @@ AcpiTimerLibConstructor (
HostBridgeDevId = PciRead16 (OVMF_HOSTBRIDGE_DID); HostBridgeDevId = PciRead16 (OVMF_HOSTBRIDGE_DID);
switch (HostBridgeDevId) { switch (HostBridgeDevId) {
case INTEL_82441_DEVICE_ID: case INTEL_82441_DEVICE_ID:
Pmba = POWER_MGMT_REGISTER_PIIX4 (0x40); Pmba = POWER_MGMT_REGISTER_PIIX4 (PIIX4_PMBA);
AcpiCtlReg = POWER_MGMT_REGISTER_PIIX4 (0x80); // PMREGMISC AcpiCtlReg = POWER_MGMT_REGISTER_PIIX4 (PIIX4_PMREGMISC);
AcpiEnBit = PIIX4_PMIOSE; AcpiEnBit = PIIX4_PMREGMISC_PMIOSE;
break; break;
case INTEL_Q35_MCH_DEVICE_ID: case INTEL_Q35_MCH_DEVICE_ID:
Pmba = POWER_MGMT_REGISTER_Q35 (ICH9_PMBASE); Pmba = POWER_MGMT_REGISTER_Q35 (ICH9_PMBASE);
@ -114,7 +113,7 @@ InternalAcpiGetTimerTick (
HostBridgeDevId = PciRead16 (OVMF_HOSTBRIDGE_DID); HostBridgeDevId = PciRead16 (OVMF_HOSTBRIDGE_DID);
switch (HostBridgeDevId) { switch (HostBridgeDevId) {
case INTEL_82441_DEVICE_ID: case INTEL_82441_DEVICE_ID:
Pmba = POWER_MGMT_REGISTER_PIIX4 (0x40); Pmba = POWER_MGMT_REGISTER_PIIX4 (PIIX4_PMBA);
break; break;
case INTEL_Q35_MCH_DEVICE_ID: case INTEL_Q35_MCH_DEVICE_ID:
Pmba = POWER_MGMT_REGISTER_Q35 (ICH9_PMBASE); Pmba = POWER_MGMT_REGISTER_Q35 (ICH9_PMBASE);

2
OvmfPkg/Library/AcpiTimerLib/DxeAcpiTimerLib.c
View File

@ -61,7 +61,7 @@ AcpiTimerLibConstructor (
HostBridgeDevId = PcdGet16 (PcdOvmfHostBridgePciDevId); HostBridgeDevId = PcdGet16 (PcdOvmfHostBridgePciDevId);
switch (HostBridgeDevId) { switch (HostBridgeDevId) {
case INTEL_82441_DEVICE_ID: case INTEL_82441_DEVICE_ID:
Pmba = POWER_MGMT_REGISTER_PIIX4 (0x40); Pmba = POWER_MGMT_REGISTER_PIIX4 (PIIX4_PMBA);
break; break;
case INTEL_Q35_MCH_DEVICE_ID: case INTEL_Q35_MCH_DEVICE_ID:
Pmba = POWER_MGMT_REGISTER_Q35 (ICH9_PMBASE); Pmba = POWER_MGMT_REGISTER_Q35 (ICH9_PMBASE);

2
OvmfPkg/Library/PlatformBdsLib/BdsPlatform.c
View File

@ -860,7 +860,7 @@ PciAcpiInitialization (
mHostBridgeDevId = PcdGet16 (PcdOvmfHostBridgePciDevId); mHostBridgeDevId = PcdGet16 (PcdOvmfHostBridgePciDevId);
switch (mHostBridgeDevId) { switch (mHostBridgeDevId) {
case INTEL_82441_DEVICE_ID: case INTEL_82441_DEVICE_ID:
Pmba = POWER_MGMT_REGISTER_PIIX4 (0x40); Pmba = POWER_MGMT_REGISTER_PIIX4 (PIIX4_PMBA);
// //
// 00:01.0 ISA Bridge (PIIX4) LNK routing targets // 00:01.0 ISA Bridge (PIIX4) LNK routing targets
// //

6
OvmfPkg/PlatformPei/Platform.c
View File

@ -252,9 +252,9 @@ MiscInitialization (
switch (HostBridgeDevId) { switch (HostBridgeDevId) {
case INTEL_82441_DEVICE_ID: case INTEL_82441_DEVICE_ID:
PmCmd = POWER_MGMT_REGISTER_PIIX4 (PCI_COMMAND_OFFSET); PmCmd = POWER_MGMT_REGISTER_PIIX4 (PCI_COMMAND_OFFSET);
Pmba = POWER_MGMT_REGISTER_PIIX4 (0x40); Pmba = POWER_MGMT_REGISTER_PIIX4 (PIIX4_PMBA);
AcpiCtlReg = POWER_MGMT_REGISTER_PIIX4 (0x80); // PMREGMISC AcpiCtlReg = POWER_MGMT_REGISTER_PIIX4 (PIIX4_PMREGMISC);
AcpiEnBit = BIT0; // PIIX4_PMIOSE AcpiEnBit = PIIX4_PMREGMISC_PMIOSE;
break; break;
case INTEL_Q35_MCH_DEVICE_ID: case INTEL_Q35_MCH_DEVICE_ID:
PmCmd = POWER_MGMT_REGISTER_Q35 (PCI_COMMAND_OFFSET); PmCmd = POWER_MGMT_REGISTER_Q35 (PCI_COMMAND_OFFSET);