mirror of https://github.com/acidanthera/audk.git
ArmPkg: Add ARM Architectural Timer support
ARM Architectural Timer support is defined by the ARM Generic Timer Specification. git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@12455 6f19259b-4bc3-4df7-8a09-765794883524
This commit is contained in:
oliviermartin
parent
0c0e7ef451
commit
da9675a241
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@ -133,3 +133,10 @@
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# The Linux ATAGs are expected to be under 0x4000 (16KB) from the beginning of the System Memory
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gArmTokenSpaceGuid.PcdArmLinuxAtagMaxOffset|0x4000|UINT32|0x00000020
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#
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# ARM Architectural Timer
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#
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gArmTokenSpaceGuid.PcdArmArchTimerFreqInHz|0|UINT32|0x00000034
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# ARM Architectural Timer Interrupt(GIC PPI) number
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gArmTokenSpaceGuid.PcdArmArchTimerSecIntrNum|29|UINT32|0x00000035
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gArmTokenSpaceGuid.PcdArmArchTimerIntrNum|30|UINT32|0x00000036
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@ -0,0 +1,379 @@
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/** @file
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Timer Architecture Protocol driver of the ARM flavor
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Copyright (c) 2011 ARM Ltd. All rights reserved.<BR>
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This program and the accompanying materials
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are licensed and made available under the terms and conditions of the BSD License
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which accompanies this distribution. The full text of the license may be found at
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http://opensource.org/licenses/bsd-license.php
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THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
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WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
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**/
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#include <PiDxe.h>
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#include <Library/BaseLib.h>
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#include <Library/DebugLib.h>
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#include <Library/BaseMemoryLib.h>
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#include <Library/UefiBootServicesTableLib.h>
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#include <Library/UefiLib.h>
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#include <Library/PcdLib.h>
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#include <Library/IoLib.h>
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#include <Library/ArmV7ArchTimerLib.h>
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#include <Protocol/Timer.h>
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#include <Protocol/HardwareInterrupt.h>
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// The notification function to call on every timer interrupt.
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EFI_TIMER_NOTIFY mTimerNotifyFunction = (EFI_TIMER_NOTIFY)NULL;
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EFI_EVENT EfiExitBootServicesEvent = (EFI_EVENT)NULL;
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// The current period of the timer interrupt
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UINT64 mTimerPeriod = 0;
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// Cached copy of the Hardware Interrupt protocol instance
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EFI_HARDWARE_INTERRUPT_PROTOCOL *gInterrupt = NULL;
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/**
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This function registers the handler NotifyFunction so it is called every time
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the timer interrupt fires. It also passes the amount of time since the last
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handler call to the NotifyFunction. If NotifyFunction is NULL, then the
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handler is unregistered. If the handler is registered, then EFI_SUCCESS is
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returned. If the CPU does not support registering a timer interrupt handler,
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then EFI_UNSUPPORTED is returned. If an attempt is made to register a handler
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when a handler is already registered, then EFI_ALREADY_STARTED is returned.
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If an attempt is made to unregister a handler when a handler is not registered,
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then EFI_INVALID_PARAMETER is returned. If an error occurs attempting to
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register the NotifyFunction with the timer interrupt, then EFI_DEVICE_ERROR
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is returned.
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@param This The EFI_TIMER_ARCH_PROTOCOL instance.
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@param NotifyFunction The function to call when a timer interrupt fires. This
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function executes at TPL_HIGH_LEVEL. The DXE Core will
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register a handler for the timer interrupt, so it can know
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how much time has passed. This information is used to
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signal timer based events. NULL will unregister the handler.
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@retval EFI_SUCCESS The timer handler was registered.
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@retval EFI_UNSUPPORTED The platform does not support timer interrupts.
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@retval EFI_ALREADY_STARTED NotifyFunction is not NULL, and a handler is already
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registered.
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@retval EFI_INVALID_PARAMETER NotifyFunction is NULL, and a handler was not
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previously registered.
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@retval EFI_DEVICE_ERROR The timer handler could not be registered.
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**/
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EFI_STATUS
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EFIAPI
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TimerDriverRegisterHandler (
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IN EFI_TIMER_ARCH_PROTOCOL *This,
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IN EFI_TIMER_NOTIFY NotifyFunction
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)
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{
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if ((NotifyFunction == NULL) && (mTimerNotifyFunction == NULL)) {
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return EFI_INVALID_PARAMETER;
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}
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if ((NotifyFunction != NULL) && (mTimerNotifyFunction != NULL)) {
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return EFI_ALREADY_STARTED;
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}
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mTimerNotifyFunction = NotifyFunction;
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return EFI_SUCCESS;
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}
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/**
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Disable the timer
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**/
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VOID
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EFIAPI
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ExitBootServicesEvent (
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IN EFI_EVENT Event,
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IN VOID *Context
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)
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{
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ArmArchTimerDisableTimer ();
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}
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/**
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This function adjusts the period of timer interrupts to the value specified
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by TimerPeriod. If the timer period is updated, then the selected timer
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period is stored in EFI_TIMER.TimerPeriod, and EFI_SUCCESS is returned. If
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the timer hardware is not programmable, then EFI_UNSUPPORTED is returned.
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If an error occurs while attempting to update the timer period, then the
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timer hardware will be put back in its state prior to this call, and
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EFI_DEVICE_ERROR is returned. If TimerPeriod is 0, then the timer interrupt
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is disabled. This is not the same as disabling the CPU's interrupts.
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Instead, it must either turn off the timer hardware, or it must adjust the
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interrupt controller so that a CPU interrupt is not generated when the timer
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interrupt fires.
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@param This The EFI_TIMER_ARCH_PROTOCOL instance.
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@param TimerPeriod The rate to program the timer interrupt in 100 nS units. If
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the timer hardware is not programmable, then EFI_UNSUPPORTED is
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returned. If the timer is programmable, then the timer period
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will be rounded up to the nearest timer period that is supported
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by the timer hardware. If TimerPeriod is set to 0, then the
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timer interrupts will be disabled.
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@retval EFI_SUCCESS The timer period was changed.
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@retval EFI_UNSUPPORTED The platform cannot change the period of the timer interrupt.
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@retval EFI_DEVICE_ERROR The timer period could not be changed due to a device error.
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**/
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EFI_STATUS
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EFIAPI
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TimerDriverSetTimerPeriod (
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IN EFI_TIMER_ARCH_PROTOCOL *This,
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IN UINT64 TimerPeriod
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)
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{
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UINT64 TimerTicks;
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// always disable the timer
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ArmArchTimerDisableTimer ();
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if (TimerPeriod != 0) {
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// Convert TimerPeriod to micro sec units
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TimerTicks = DivU64x32 (TimerPeriod, 10);
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TimerTicks = MultU64x32 (TimerPeriod, (PcdGet32(PcdArmArchTimerFreqInHz)/1000000));
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ArmArchTimerSetTimerVal((UINTN)TimerTicks);
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// Enable the timer
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ArmArchTimerEnableTimer ();
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}
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// Save the new timer period
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mTimerPeriod = TimerPeriod;
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return EFI_SUCCESS;
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}
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/**
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This function retrieves the period of timer interrupts in 100 ns units,
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returns that value in TimerPeriod, and returns EFI_SUCCESS. If TimerPeriod
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is NULL, then EFI_INVALID_PARAMETER is returned. If a TimerPeriod of 0 is
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returned, then the timer is currently disabled.
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@param This The EFI_TIMER_ARCH_PROTOCOL instance.
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@param TimerPeriod A pointer to the timer period to retrieve in 100 ns units. If
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0 is returned, then the timer is currently disabled.
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@retval EFI_SUCCESS The timer period was returned in TimerPeriod.
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@retval EFI_INVALID_PARAMETER TimerPeriod is NULL.
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**/
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EFI_STATUS
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EFIAPI
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TimerDriverGetTimerPeriod (
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IN EFI_TIMER_ARCH_PROTOCOL *This,
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OUT UINT64 *TimerPeriod
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)
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{
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if (TimerPeriod == NULL) {
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return EFI_INVALID_PARAMETER;
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}
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*TimerPeriod = mTimerPeriod;
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return EFI_SUCCESS;
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}
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/**
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This function generates a soft timer interrupt. If the platform does not support soft
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timer interrupts, then EFI_UNSUPPORTED is returned. Otherwise, EFI_SUCCESS is returned.
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If a handler has been registered through the EFI_TIMER_ARCH_PROTOCOL.RegisterHandler()
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service, then a soft timer interrupt will be generated. If the timer interrupt is
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enabled when this service is called, then the registered handler will be invoked. The
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registered handler should not be able to distinguish a hardware-generated timer
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interrupt from a software-generated timer interrupt.
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@param This The EFI_TIMER_ARCH_PROTOCOL instance.
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@retval EFI_SUCCESS The soft timer interrupt was generated.
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@retval EFI_UNSUPPORTED The platform does not support the generation of soft timer interrupts.
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**/
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EFI_STATUS
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EFIAPI
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TimerDriverGenerateSoftInterrupt (
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IN EFI_TIMER_ARCH_PROTOCOL *This
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)
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{
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return EFI_UNSUPPORTED;
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}
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/**
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Interface structure for the Timer Architectural Protocol.
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@par Protocol Description:
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This protocol provides the services to initialize a periodic timer
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interrupt, and to register a handler that is called each time the timer
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interrupt fires. It may also provide a service to adjust the rate of the
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periodic timer interrupt. When a timer interrupt occurs, the handler is
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passed the amount of time that has passed since the previous timer
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interrupt.
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@param RegisterHandler
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Registers a handler that will be called each time the
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timer interrupt fires. TimerPeriod defines the minimum
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time between timer interrupts, so TimerPeriod will also
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be the minimum time between calls to the registered
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handler.
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@param SetTimerPeriod
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Sets the period of the timer interrupt in 100 nS units.
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This function is optional, and may return EFI_UNSUPPORTED.
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If this function is supported, then the timer period will
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be rounded up to the nearest supported timer period.
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@param GetTimerPeriod
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Retrieves the period of the timer interrupt in 100 nS units.
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@param GenerateSoftInterrupt
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Generates a soft timer interrupt that simulates the firing of
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the timer interrupt. This service can be used to invoke the registered handler if the timer interrupt has been masked for
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a period of time.
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**/
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EFI_TIMER_ARCH_PROTOCOL gTimer = {
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TimerDriverRegisterHandler,
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TimerDriverSetTimerPeriod,
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TimerDriverGetTimerPeriod,
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TimerDriverGenerateSoftInterrupt
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};
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/**
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C Interrupt Handler called in the interrupt context when Source interrupt is active.
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@param Source Source of the interrupt. Hardware routing off a specific platform defines
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what source means.
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@param SystemContext Pointer to system register context. Mostly used by debuggers and will
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update the system context after the return from the interrupt if
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modified. Don't change these values unless you know what you are doing
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**/
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VOID
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EFIAPI
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TimerInterruptHandler (
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IN HARDWARE_INTERRUPT_SOURCE Source,
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IN EFI_SYSTEM_CONTEXT SystemContext
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)
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{
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EFI_TPL OriginalTPL;
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//
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// DXE core uses this callback for the EFI timer tick. The DXE core uses locks
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// that raise to TPL_HIGH and then restore back to current level. Thus we need
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// to make sure TPL level is set to TPL_HIGH while we are handling the timer tick.
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//
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OriginalTPL = gBS->RaiseTPL (TPL_HIGH_LEVEL);
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// Check if the timer interrupt is active
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if ((ArmArchTimerGetTimerCtrlReg () ) & ARM_ARCH_TIMER_ISTATUS) {
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// Signal end of interrupt early to help avoid losing subsequent ticks from long duration handlers
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gInterrupt->EndOfInterrupt (gInterrupt, Source);
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if (mTimerNotifyFunction) {
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mTimerNotifyFunction (mTimerPeriod);
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}
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// Reload the Timer
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TimerDriverSetTimerPeriod (&gTimer, FixedPcdGet32(PcdTimerPeriod));
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}
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// Enable timer interrupts
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gInterrupt->EnableInterruptSource (gInterrupt, Source);
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gBS->RestoreTPL (OriginalTPL);
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}
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/**
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Initialize the state information for the Timer Architectural Protocol and
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the Timer Debug support protocol that allows the debugger to break into a
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running program.
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@param ImageHandle of the loaded driver
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@param SystemTable Pointer to the System Table
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@retval EFI_SUCCESS Protocol registered
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@retval EFI_OUT_OF_RESOURCES Cannot allocate protocol data structure
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@retval EFI_DEVICE_ERROR Hardware problems
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**/
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EFI_STATUS
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EFIAPI
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TimerInitialize (
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IN EFI_HANDLE ImageHandle,
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IN EFI_SYSTEM_TABLE *SystemTable
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)
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{
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EFI_HANDLE Handle = NULL;
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EFI_STATUS Status;
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UINTN TimerCtrlReg;
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if (ArmIsArchTimerImplemented () == 0) {
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DEBUG ((EFI_D_ERROR, "ARM Architectural Timer is not available in the CPU, hence cann't use this Driver \n"));
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ASSERT (0);
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}
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// Find the interrupt controller protocol. ASSERT if not found.
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Status = gBS->LocateProtocol (&gHardwareInterruptProtocolGuid, NULL, (VOID **)&gInterrupt);
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ASSERT_EFI_ERROR (Status);
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// Disable the timer
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Status = TimerDriverSetTimerPeriod (&gTimer, 0);
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ASSERT_EFI_ERROR (Status);
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// Install secure and Non-secure interrupt handlers
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// Note: Because it is not possible to determine the security state of the
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// CPU dynamically, we just install interrupt handler for both sec and non-sec
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// timer PPI
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Status = gInterrupt->RegisterInterruptSource (gInterrupt, PcdGet32 (PcdArmArchTimerSecIntrNum), TimerInterruptHandler);
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ASSERT_EFI_ERROR (Status);
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Status = gInterrupt->RegisterInterruptSource (gInterrupt, PcdGet32 (PcdArmArchTimerIntrNum), TimerInterruptHandler);
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ASSERT_EFI_ERROR (Status);
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// Unmask timer interrupts
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TimerCtrlReg = ArmArchTimerGetTimerCtrlReg ();
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TimerCtrlReg &= ~ARM_ARCH_TIMER_IMASK;
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ArmArchTimerSetTimerCtrlReg (TimerCtrlReg);
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// Set up default timer
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Status = TimerDriverSetTimerPeriod (&gTimer, FixedPcdGet32(PcdTimerPeriod)); // TIMER_DEFAULT_PERIOD
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ASSERT_EFI_ERROR (Status);
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// Install the Timer Architectural Protocol onto a new handle
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Status = gBS->InstallMultipleProtocolInterfaces(
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&Handle,
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&gEfiTimerArchProtocolGuid, &gTimer,
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NULL
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);
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ASSERT_EFI_ERROR(Status);
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// enable Secure timer interrupts
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Status = gInterrupt->EnableInterruptSource (gInterrupt, PcdGet32 (PcdArmArchTimerSecIntrNum));
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// enable NonSecure timer interrupts
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Status = gInterrupt->EnableInterruptSource (gInterrupt, PcdGet32 (PcdArmArchTimerIntrNum));
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// Register for an ExitBootServicesEvent
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Status = gBS->CreateEvent (EVT_SIGNAL_EXIT_BOOT_SERVICES, TPL_NOTIFY, ExitBootServicesEvent, NULL, &EfiExitBootServicesEvent);
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ASSERT_EFI_ERROR (Status);
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return Status;
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}
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@ -0,0 +1,59 @@
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#/** @file
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#
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# Component discription file for Timer DXE module
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#
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# Copyright (c) 2009 - 2010, Apple Inc. All rights reserved.<BR>
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# This program and the accompanying materials
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# are licensed and made available under the terms and conditions of the BSD License
|
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# which accompanies this distribution. The full text of the license may be found at
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# http://opensource.org/licenses/bsd-license.php
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#
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# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
|
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# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
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#
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#**/
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[Defines]
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INF_VERSION = 0x00010005
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BASE_NAME = ArmTimerDxe
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FILE_GUID = 49ea041e-6752-42ca-b0b1-7344fe2546b7
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MODULE_TYPE = DXE_DRIVER
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VERSION_STRING = 1.0
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ENTRY_POINT = TimerInitialize
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[Sources.common]
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TimerDxe.c
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[Packages]
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MdePkg/MdePkg.dec
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EmbeddedPkg/EmbeddedPkg.dec
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ArmPkg/ArmPkg.dec
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ArmPlatformPkg/ArmPlatformPkg.dec
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[LibraryClasses]
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ArmLib
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BaseLib
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UefiRuntimeServicesTableLib
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UefiLib
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UefiBootServicesTableLib
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BaseMemoryLib
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DebugLib
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UefiDriverEntryPoint
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IoLib
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[Guids]
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[Protocols]
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gEfiTimerArchProtocolGuid
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gHardwareInterruptProtocolGuid
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[Pcd.common]
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gEmbeddedTokenSpaceGuid.PcdTimerPeriod
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gArmTokenSpaceGuid.PcdArmArchTimerSecIntrNum
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gArmTokenSpaceGuid.PcdArmArchTimerIntrNum
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gArmTokenSpaceGuid.PcdArmArchTimerFreqInHz
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[Depex]
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gHardwareInterruptProtocolGuid
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@ -17,6 +17,7 @@
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#define __ARM_V7_H__
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#include <Chipset/ArmV7Mmu.h>
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#include <Chipset/ArmV7ArchTimer.h>
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// Domain Access Control Register
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#define DOMAIN_ACCESS_CONTROL_MASK(a) (3UL << (2 * (a)))
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@ -80,6 +81,12 @@ ArmWriteTpidrurw (
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UINTN Value
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);
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UINTN
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EFIAPI
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ArmIsArchTimerImplemented (
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VOID
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);
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UINTN
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EFIAPI
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ArmReadIdPfr1 (
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|
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@ -0,0 +1,138 @@
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/** @file
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*
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* Copyright (c) 2011, ARM Limited. All rights reserved.
|
||||
*
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* This program and the accompanying materials
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||||
* are licensed and made available under the terms and conditions of the BSD License
|
||||
* which accompanies this distribution. The full text of the license may be found at
|
||||
* http://opensource.org/licenses/bsd-license.php
|
||||
*
|
||||
* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
|
||||
*
|
||||
**/
|
||||
|
||||
#ifndef __ARMV7_ARCH_TIMER_H_
|
||||
#define __ARMV7_ARCH_TIMER_H_
|
||||
|
||||
UINTN
|
||||
EFIAPI
|
||||
ArmReadCntFrq (
|
||||
VOID
|
||||
);
|
||||
|
||||
VOID
|
||||
EFIAPI
|
||||
ArmWriteCntFrq (
|
||||
UINTN FreqInHz
|
||||
);
|
||||
|
||||
UINT64
|
||||
EFIAPI
|
||||
ArmReadCntPct (
|
||||
VOID
|
||||
);
|
||||
|
||||
UINTN
|
||||
EFIAPI
|
||||
ArmReadCntkCtl (
|
||||
VOID
|
||||
);
|
||||
|
||||
VOID
|
||||
EFIAPI
|
||||
ArmWriteCntkCtl (
|
||||
UINTN Val
|
||||
);
|
||||
|
||||
UINTN
|
||||
EFIAPI
|
||||
ArmReadCntpTval (
|
||||
VOID
|
||||
);
|
||||
|
||||
VOID
|
||||
EFIAPI
|
||||
ArmWriteCntpTval (
|
||||
UINTN Val
|
||||
);
|
||||
|
||||
UINTN
|
||||
EFIAPI
|
||||
ArmReadCntpCtl (
|
||||
VOID
|
||||
);
|
||||
|
||||
VOID
|
||||
EFIAPI
|
||||
ArmWriteCntpCtl (
|
||||
UINTN Val
|
||||
);
|
||||
|
||||
UINTN
|
||||
EFIAPI
|
||||
ArmReadCntvTval (
|
||||
VOID
|
||||
);
|
||||
|
||||
VOID
|
||||
EFIAPI
|
||||
ArmWriteCntvTval (
|
||||
UINTN Val
|
||||
);
|
||||
|
||||
UINTN
|
||||
EFIAPI
|
||||
ArmReadCntvCtl (
|
||||
VOID
|
||||
);
|
||||
|
||||
VOID
|
||||
EFIAPI
|
||||
ArmWriteCntvCtl (
|
||||
UINTN Val
|
||||
);
|
||||
|
||||
UINT64
|
||||
EFIAPI
|
||||
ArmReadCntvCt (
|
||||
VOID
|
||||
);
|
||||
|
||||
UINT64
|
||||
EFIAPI
|
||||
ArmReadCntpCval (
|
||||
VOID
|
||||
);
|
||||
|
||||
VOID
|
||||
EFIAPI
|
||||
ArmWriteCntpCval (
|
||||
UINT64 Val
|
||||
);
|
||||
|
||||
UINT64
|
||||
EFIAPI
|
||||
ArmReadCntvCval (
|
||||
VOID
|
||||
);
|
||||
|
||||
VOID
|
||||
EFIAPI
|
||||
ArmWriteCntvCval (
|
||||
UINT64 Val
|
||||
);
|
||||
|
||||
UINT64
|
||||
EFIAPI
|
||||
ArmReadCntvOff (
|
||||
VOID
|
||||
);
|
||||
|
||||
VOID
|
||||
EFIAPI
|
||||
ArmWriteCntvOff (
|
||||
UINT64 Val
|
||||
);
|
||||
|
||||
#endif
|
||||
|
|
@ -167,7 +167,7 @@ Cp15CacheInfo (
|
|||
|
||||
BOOLEAN
|
||||
EFIAPI
|
||||
ArmIsMPCore (
|
||||
ArmIsMpCore (
|
||||
VOID
|
||||
);
|
||||
|
||||
|
|
|
|||
|
|
@ -0,0 +1,115 @@
|
|||
/** @file
|
||||
|
||||
Copyright (c) 2011, ARM Ltd. All rights reserved.<BR>
|
||||
|
||||
This program and the accompanying materials
|
||||
are licensed and made available under the terms and conditions of the BSD License
|
||||
which accompanies this distribution. The full text of the license may be found at
|
||||
http://opensource.org/licenses/bsd-license.php
|
||||
|
||||
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
|
||||
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
|
||||
|
||||
**/
|
||||
|
||||
#ifndef __ARM_V7_ARCH_TIMER_LIB_H__
|
||||
#define __ARM_V7_ARCH_TIMER_LIB_H__
|
||||
|
||||
#define ARM_ARCH_TIMER_ENABLE (1 << 0)
|
||||
#define ARM_ARCH_TIMER_IMASK (1 << 1)
|
||||
#define ARM_ARCH_TIMER_ISTATUS (1 << 2)
|
||||
|
||||
typedef enum {
|
||||
CntFrq = 0,
|
||||
CntPct,
|
||||
CntkCtl,
|
||||
CntpTval,
|
||||
CntpCtl,
|
||||
CntvTval,
|
||||
CntvCtl,
|
||||
CntvCt,
|
||||
CntpCval,
|
||||
CntvCval,
|
||||
CntvOff,
|
||||
CnthCtl,
|
||||
CnthpTval,
|
||||
CnthpCtl,
|
||||
CnthpCval,
|
||||
RegMaximum
|
||||
}ARM_ARCH_TIMER_REGS;
|
||||
|
||||
VOID
|
||||
EFIAPI
|
||||
ArmArchTimerReadReg (
|
||||
IN ARM_ARCH_TIMER_REGS Reg,
|
||||
OUT VOID *DstBuf
|
||||
);
|
||||
|
||||
VOID
|
||||
EFIAPI
|
||||
ArmArchTimerWriteReg (
|
||||
IN ARM_ARCH_TIMER_REGS Reg,
|
||||
IN VOID *SrcBuf
|
||||
);
|
||||
|
||||
VOID
|
||||
EFIAPI
|
||||
ArmArchTimerEnableTimer (
|
||||
VOID
|
||||
);
|
||||
|
||||
VOID
|
||||
EFIAPI
|
||||
ArmArchTimerDisableTimer (
|
||||
VOID
|
||||
);
|
||||
|
||||
VOID
|
||||
EFIAPI
|
||||
ArmArchTimerSetTimerFreq (
|
||||
IN UINTN FreqInHz
|
||||
);
|
||||
|
||||
UINTN
|
||||
EFIAPI
|
||||
ArmArchTimerGetTimerFreq (
|
||||
VOID
|
||||
);
|
||||
|
||||
VOID
|
||||
EFIAPI
|
||||
ArmArchTimerSetTimerVal (
|
||||
IN UINTN Val
|
||||
);
|
||||
|
||||
UINTN
|
||||
EFIAPI
|
||||
ArmArchTimerGetTimerVal (
|
||||
VOID
|
||||
);
|
||||
|
||||
UINT64
|
||||
EFIAPI
|
||||
ArmArchTimerGetSystemCount (
|
||||
VOID
|
||||
);
|
||||
|
||||
UINTN
|
||||
EFIAPI
|
||||
ArmArchTimerGetTimerCtrlReg (
|
||||
VOID
|
||||
);
|
||||
|
||||
VOID
|
||||
EFIAPI
|
||||
ArmArchTimerSetTimerCtrlReg (
|
||||
UINTN Val
|
||||
);
|
||||
|
||||
VOID
|
||||
EFIAPI
|
||||
ArmArchTimerSetCompareVal (
|
||||
IN UINT64 Val
|
||||
);
|
||||
|
||||
#endif // __ARM_V7_ARCH_TIMER_LIB_H__
|
||||
|
|
@ -0,0 +1,191 @@
|
|||
/** @file
|
||||
Generic ARM implementation of TimerLib.h
|
||||
|
||||
Copyright (c) 2011, ARM Limited. All rights reserved.
|
||||
|
||||
This program and the accompanying materials
|
||||
are licensed and made available under the terms and conditions of the BSD License
|
||||
which accompanies this distribution. The full text of the license may be found at
|
||||
http://opensource.org/licenses/bsd-license.php
|
||||
|
||||
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
|
||||
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
|
||||
|
||||
**/
|
||||
|
||||
|
||||
#include <Base.h>
|
||||
#include <Library/BaseLib.h>
|
||||
#include <Library/TimerLib.h>
|
||||
#include <Library/DebugLib.h>
|
||||
#include <Library/PcdLib.h>
|
||||
#include <Library/ArmV7ArchTimerLib.h>
|
||||
#include <Chipset/ArmV7.h>
|
||||
|
||||
#define TICKS_PER_MICRO_SEC (PcdGet32 (PcdArmArchTimerFreqInHz)/1000000U)
|
||||
|
||||
RETURN_STATUS
|
||||
EFIAPI
|
||||
ArmArchTimerLibConstructor (
|
||||
VOID
|
||||
)
|
||||
{
|
||||
// Check if the ARM Generic Timer Extension is implemented
|
||||
if (ArmIsArchTimerImplemented ()) {
|
||||
|
||||
UINTN TimerFreq;
|
||||
|
||||
// Check if Architectural Timer frequency is valid number (should not be 0)
|
||||
ASSERT (PcdGet32 (PcdArmArchTimerFreqInHz));
|
||||
|
||||
// Check if ticks/uS is not 0. The Architectural timer runs at constant
|
||||
// frequency irrespective of CPU frequency. According to General Timer Ref
|
||||
// manual lower bound of the frequency is in the range of 1-10MHz
|
||||
ASSERT (TICKS_PER_MICRO_SEC);
|
||||
|
||||
// If the security extensions are not implemented set Timer Frequency
|
||||
if ((ArmReadIdPfr1 () & 0xF0)) {
|
||||
ArmArchTimerSetTimerFreq (PcdGet32 (PcdArmArchTimerFreqInHz));
|
||||
}
|
||||
|
||||
// Architectural Timer Frequency must be set in the Secure privileged(if secure extensions are supported) mode.
|
||||
// If the reset value (0) is returned just ASSERT.
|
||||
TimerFreq = ArmArchTimerGetTimerFreq ();
|
||||
ASSERT (TimerFreq);
|
||||
|
||||
} else {
|
||||
DEBUG ((EFI_D_ERROR, "ARM Architectural Timer is not available in the CPU, Hence cann't use this library \n"));
|
||||
ASSERT (0);
|
||||
}
|
||||
|
||||
return RETURN_SUCCESS;
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
Stalls the CPU for the number of microseconds specified by MicroSeconds.
|
||||
|
||||
@param MicroSeconds The minimum number of microseconds to delay.
|
||||
|
||||
@return The value of MicroSeconds inputted.
|
||||
|
||||
**/
|
||||
UINTN
|
||||
EFIAPI
|
||||
MicroSecondDelay (
|
||||
IN UINTN MicroSeconds
|
||||
)
|
||||
{
|
||||
UINT64 TimerTicks64;
|
||||
UINT64 SystemCounterVal;
|
||||
|
||||
// Calculate counter ticks that can represent requsted delay
|
||||
TimerTicks64 = MultU64x32 (MicroSeconds, TICKS_PER_MICRO_SEC);
|
||||
|
||||
// Read System Counter value
|
||||
SystemCounterVal = ArmArchTimerGetSystemCount ();
|
||||
|
||||
TimerTicks64 += SystemCounterVal;
|
||||
|
||||
// Wait until delay count is expired.
|
||||
while (SystemCounterVal < TimerTicks64) {
|
||||
SystemCounterVal = ArmArchTimerGetSystemCount ();
|
||||
}
|
||||
|
||||
return MicroSeconds;
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
Stalls the CPU for at least the given number of nanoseconds.
|
||||
|
||||
Stalls the CPU for the number of nanoseconds specified by NanoSeconds.
|
||||
|
||||
When the timer frequency is 1MHz, each tick corresponds to 1 microsecond.
|
||||
Therefore, the nanosecond delay will be rounded up to the nearest 1 microsecond.
|
||||
|
||||
@param NanoSeconds The minimum number of nanoseconds to delay.
|
||||
|
||||
@return The value of NanoSeconds inputted.
|
||||
|
||||
**/
|
||||
UINTN
|
||||
EFIAPI
|
||||
NanoSecondDelay (
|
||||
IN UINTN NanoSeconds
|
||||
)
|
||||
{
|
||||
UINTN MicroSeconds;
|
||||
|
||||
// Round up to 1us Tick Number
|
||||
MicroSeconds = NanoSeconds / 1000;
|
||||
MicroSeconds += ((NanoSeconds % 1000) == 0) ? 0 : 1;
|
||||
|
||||
MicroSecondDelay (MicroSeconds);
|
||||
|
||||
return NanoSeconds;
|
||||
}
|
||||
|
||||
/**
|
||||
Retrieves the current value of a 64-bit free running performance counter.
|
||||
|
||||
The counter can either count up by 1 or count down by 1. If the physical
|
||||
performance counter counts by a larger increment, then the counter values
|
||||
must be translated. The properties of the counter can be retrieved from
|
||||
GetPerformanceCounterProperties().
|
||||
|
||||
@return The current value of the free running performance counter.
|
||||
|
||||
**/
|
||||
UINT64
|
||||
EFIAPI
|
||||
GetPerformanceCounter (
|
||||
VOID
|
||||
)
|
||||
{
|
||||
// Just return the value of system count
|
||||
return ArmArchTimerGetSystemCount ();
|
||||
}
|
||||
|
||||
/**
|
||||
Retrieves the 64-bit frequency in Hz and the range of performance counter
|
||||
values.
|
||||
|
||||
If StartValue is not NULL, then the value that the performance counter starts
|
||||
with immediately after is it rolls over is returned in StartValue. If
|
||||
EndValue is not NULL, then the value that the performance counter end with
|
||||
immediately before it rolls over is returned in EndValue. The 64-bit
|
||||
frequency of the performance counter in Hz is always returned. If StartValue
|
||||
is less than EndValue, then the performance counter counts up. If StartValue
|
||||
is greater than EndValue, then the performance counter counts down. For
|
||||
example, a 64-bit free running counter that counts up would have a StartValue
|
||||
of 0 and an EndValue of 0xFFFFFFFFFFFFFFFF. A 24-bit free running counter
|
||||
that counts down would have a StartValue of 0xFFFFFF and an EndValue of 0.
|
||||
|
||||
@param StartValue The value the performance counter starts with when it
|
||||
rolls over.
|
||||
@param EndValue The value that the performance counter ends with before
|
||||
it rolls over.
|
||||
|
||||
@return The frequency in Hz.
|
||||
|
||||
**/
|
||||
UINT64
|
||||
EFIAPI
|
||||
GetPerformanceCounterProperties (
|
||||
OUT UINT64 *StartValue, OPTIONAL
|
||||
OUT UINT64 *EndValue OPTIONAL
|
||||
)
|
||||
{
|
||||
if (StartValue != NULL) {
|
||||
// Timer starts with the reload value
|
||||
*StartValue = (UINT64)0ULL ;
|
||||
}
|
||||
|
||||
if (EndValue != NULL) {
|
||||
// Timer counts down to 0x0
|
||||
*EndValue = 0xFFFFFFFFFFFFFFFF;;
|
||||
}
|
||||
|
||||
return (UINT64)ArmArchTimerGetTimerFreq ();
|
||||
}
|
||||
|
|
@ -0,0 +1,46 @@
|
|||
#/** @file
|
||||
#
|
||||
# Copyright (c) 2011, ARM Limited. All rights reserved.<BR>
|
||||
# This program and the accompanying materials
|
||||
# are licensed and made available under the terms and conditions of the BSD License
|
||||
# which accompanies this distribution. The full text of the license may be found at
|
||||
# http://opensource.org/licenses/bsd-license.php
|
||||
#
|
||||
# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
|
||||
# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
|
||||
#
|
||||
#**/
|
||||
|
||||
[Defines]
|
||||
INF_VERSION = 0x00010005
|
||||
BASE_NAME = ArmArchTimerLib
|
||||
FILE_GUID = 82da1b44-d2d6-4a7d-bbf0-a0cb67964034
|
||||
MODULE_TYPE = BASE
|
||||
VERSION_STRING = 1.0
|
||||
LIBRARY_CLASS = TimerLib
|
||||
CONSTRUCTOR = ArmArchTimerLibConstructor
|
||||
|
||||
[Sources.common]
|
||||
ArmArchTimerLib.c
|
||||
|
||||
[Packages]
|
||||
MdePkg/MdePkg.dec
|
||||
EmbeddedPkg/EmbeddedPkg.dec
|
||||
ArmPkg/ArmPkg.dec
|
||||
|
||||
|
||||
[LibraryClasses]
|
||||
DebugLib
|
||||
IoLib
|
||||
ArmLib
|
||||
BaseLib
|
||||
|
||||
[Protocols]
|
||||
|
||||
[Guids]
|
||||
|
||||
[Pcd]
|
||||
gArmTokenSpaceGuid.PcdArmArchTimerFreqInHz
|
||||
|
||||
[Depex]
|
||||
gEfiCpuArchProtocolGuid
|
||||
|
|
@ -0,0 +1,275 @@
|
|||
/** @file
|
||||
*
|
||||
* Copyright (c) 2011, ARM Limited. All rights reserved.
|
||||
*
|
||||
* This program and the accompanying materials
|
||||
* are licensed and made available under the terms and conditions of the BSD License
|
||||
* which accompanies this distribution. The full text of the license may be found at
|
||||
* http://opensource.org/licenses/bsd-license.php
|
||||
*
|
||||
* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
|
||||
*
|
||||
**/
|
||||
|
||||
#include <Uefi.h>
|
||||
#include <Chipset/ArmV7.h>
|
||||
#include <Library/BaseMemoryLib.h>
|
||||
#include <Library/MemoryAllocationLib.h>
|
||||
#include <Library/ArmLib.h>
|
||||
#include <Library/BaseLib.h>
|
||||
#include <Library/DebugLib.h>
|
||||
#include "ArmV7Lib.h"
|
||||
#include "ArmLibPrivate.h"
|
||||
#include <Library/ArmV7ArchTimerLib.h>
|
||||
|
||||
VOID
|
||||
EFIAPI
|
||||
ArmArchTimerReadReg (
|
||||
IN ARM_ARCH_TIMER_REGS Reg,
|
||||
OUT VOID *DstBuf
|
||||
)
|
||||
{
|
||||
// Check if the Generic/Architecture timer is implemented
|
||||
if (ArmIsArchTimerImplemented ()) {
|
||||
|
||||
switch (Reg) {
|
||||
|
||||
case CntFrq:
|
||||
*((UINTN *)DstBuf) = ArmReadCntFrq ();
|
||||
break;
|
||||
|
||||
case CntPct:
|
||||
*((UINT64 *)DstBuf) = ArmReadCntPct ();
|
||||
break;
|
||||
|
||||
case CntkCtl:
|
||||
*((UINTN *)DstBuf) = ArmReadCntkCtl();
|
||||
break;
|
||||
|
||||
case CntpTval:
|
||||
*((UINTN *)DstBuf) = ArmReadCntpTval ();
|
||||
break;
|
||||
|
||||
case CntpCtl:
|
||||
*((UINTN *)DstBuf) = ArmReadCntpCtl ();
|
||||
break;
|
||||
|
||||
case CntvTval:
|
||||
*((UINTN *)DstBuf) = ArmReadCntvTval ();
|
||||
break;
|
||||
|
||||
case CntvCtl:
|
||||
*((UINTN *)DstBuf) = ArmReadCntvCtl ();
|
||||
break;
|
||||
|
||||
case CntvCt:
|
||||
*((UINT64 *)DstBuf) = ArmReadCntvCt ();
|
||||
break;
|
||||
|
||||
case CntpCval:
|
||||
*((UINT64 *)DstBuf) = ArmReadCntpCval ();
|
||||
break;
|
||||
|
||||
case CntvCval:
|
||||
*((UINT64 *)DstBuf) = ArmReadCntvCval ();
|
||||
break;
|
||||
|
||||
case CntvOff:
|
||||
*((UINT64 *)DstBuf) = ArmReadCntvOff ();
|
||||
break;
|
||||
|
||||
case CnthCtl:
|
||||
case CnthpTval:
|
||||
case CnthpCtl:
|
||||
case CnthpCval:
|
||||
DEBUG ((EFI_D_ERROR, "The register is related to Hyperviser Mode. Can't perform requested operation\n "));
|
||||
break;
|
||||
|
||||
default:
|
||||
DEBUG ((EFI_D_ERROR, "Unknown ARM Generic Timer register %x. \n ", Reg));
|
||||
}
|
||||
} else {
|
||||
DEBUG ((EFI_D_ERROR, "Attempt to read ARM Generic Timer registers. But ARM Generic Timer extension is not implemented \n "));
|
||||
ASSERT (0);
|
||||
}
|
||||
}
|
||||
|
||||
VOID
|
||||
EFIAPI
|
||||
ArmArchTimerWriteReg (
|
||||
IN ARM_ARCH_TIMER_REGS Reg,
|
||||
IN VOID *SrcBuf
|
||||
)
|
||||
{
|
||||
// Check if the Generic/Architecture timer is implemented
|
||||
if (ArmIsArchTimerImplemented ()) {
|
||||
|
||||
switch (Reg) {
|
||||
|
||||
case CntFrq:
|
||||
ArmWriteCntFrq (*((UINTN *)SrcBuf));
|
||||
break;
|
||||
|
||||
case CntPct:
|
||||
DEBUG ((EFI_D_ERROR, "Can't write to Read Only Register: CNTPCT \n"));
|
||||
break;
|
||||
|
||||
case CntkCtl:
|
||||
ArmWriteCntkCtl (*((UINTN *)SrcBuf));
|
||||
break;
|
||||
|
||||
case CntpTval:
|
||||
ArmWriteCntpTval (*((UINTN *)SrcBuf));
|
||||
break;
|
||||
|
||||
case CntpCtl:
|
||||
ArmWriteCntpCtl (*((UINTN *)SrcBuf));
|
||||
break;
|
||||
|
||||
case CntvTval:
|
||||
ArmWriteCntvTval (*((UINTN *)SrcBuf));
|
||||
break;
|
||||
|
||||
case CntvCtl:
|
||||
ArmWriteCntvCtl (*((UINTN *)SrcBuf));
|
||||
break;
|
||||
|
||||
case CntvCt:
|
||||
DEBUG ((EFI_D_ERROR, "Can't write to Read Only Register: CNTVCT \n"));
|
||||
break;
|
||||
|
||||
case CntpCval:
|
||||
ArmWriteCntpCval (*((UINT64 *)SrcBuf) );
|
||||
break;
|
||||
|
||||
case CntvCval:
|
||||
ArmWriteCntvCval (*((UINT64 *)SrcBuf) );
|
||||
break;
|
||||
|
||||
case CntvOff:
|
||||
ArmWriteCntvOff (*((UINT64 *)SrcBuf));
|
||||
break;
|
||||
|
||||
case CnthCtl:
|
||||
case CnthpTval:
|
||||
case CnthpCtl:
|
||||
case CnthpCval:
|
||||
DEBUG ((EFI_D_ERROR, "The register is related to Hypervisor Mode. Can't perform requested operation\n "));
|
||||
break;
|
||||
|
||||
default:
|
||||
DEBUG ((EFI_D_ERROR, "Unknown ARM Generic Timer register %x. \n ", Reg));
|
||||
}
|
||||
} else {
|
||||
DEBUG ((EFI_D_ERROR, "Attempt to write to ARM Generic Timer registers. But ARM Generic Timer extension is not implemented \n "));
|
||||
ASSERT (0);
|
||||
}
|
||||
}
|
||||
|
||||
VOID
|
||||
EFIAPI
|
||||
ArmArchTimerEnableTimer (
|
||||
VOID
|
||||
)
|
||||
{
|
||||
UINTN TimerCtrlReg;
|
||||
|
||||
ArmArchTimerReadReg (CntpCtl, (VOID *)&TimerCtrlReg);
|
||||
TimerCtrlReg |= ARM_ARCH_TIMER_ENABLE;
|
||||
ArmArchTimerWriteReg (CntpCtl, (VOID *)&TimerCtrlReg);
|
||||
}
|
||||
|
||||
VOID
|
||||
EFIAPI
|
||||
ArmArchTimerDisableTimer (
|
||||
VOID
|
||||
)
|
||||
{
|
||||
UINTN TimerCtrlReg;
|
||||
|
||||
ArmArchTimerReadReg (CntpCtl, (VOID *)&TimerCtrlReg);
|
||||
TimerCtrlReg &= ~ARM_ARCH_TIMER_ENABLE;
|
||||
ArmArchTimerWriteReg (CntpCtl, (VOID *)&TimerCtrlReg);
|
||||
}
|
||||
|
||||
VOID
|
||||
EFIAPI
|
||||
ArmArchTimerSetTimerFreq (
|
||||
IN UINTN FreqInHz
|
||||
)
|
||||
{
|
||||
ArmArchTimerWriteReg (CntFrq, (VOID *)&FreqInHz);
|
||||
}
|
||||
|
||||
UINTN
|
||||
EFIAPI
|
||||
ArmArchTimerGetTimerFreq (
|
||||
VOID
|
||||
)
|
||||
{
|
||||
UINTN ArchTimerFreq = 0;
|
||||
ArmArchTimerReadReg (CntFrq, (VOID *)&ArchTimerFreq);
|
||||
return ArchTimerFreq;
|
||||
}
|
||||
|
||||
UINTN
|
||||
EFIAPI
|
||||
ArmArchTimerGetTimerVal (
|
||||
VOID
|
||||
)
|
||||
{
|
||||
UINTN ArchTimerVal;
|
||||
ArmArchTimerReadReg (CntpTval, (VOID *)&ArchTimerVal);
|
||||
return ArchTimerVal;
|
||||
}
|
||||
|
||||
|
||||
VOID
|
||||
EFIAPI
|
||||
ArmArchTimerSetTimerVal (
|
||||
IN UINTN Val
|
||||
)
|
||||
{
|
||||
ArmArchTimerWriteReg (CntpTval, (VOID *)&Val);
|
||||
}
|
||||
|
||||
UINT64
|
||||
EFIAPI
|
||||
ArmArchTimerGetSystemCount (
|
||||
VOID
|
||||
)
|
||||
{
|
||||
UINT64 SystemCount;
|
||||
ArmArchTimerReadReg (CntPct, (VOID *)&SystemCount);
|
||||
return SystemCount;
|
||||
}
|
||||
|
||||
UINTN
|
||||
EFIAPI
|
||||
ArmArchTimerGetTimerCtrlReg (
|
||||
VOID
|
||||
)
|
||||
{
|
||||
UINTN Val;
|
||||
ArmArchTimerReadReg (CntpCtl, (VOID *)&Val);
|
||||
return Val;
|
||||
}
|
||||
|
||||
VOID
|
||||
EFIAPI
|
||||
ArmArchTimerSetTimerCtrlReg (
|
||||
UINTN Val
|
||||
)
|
||||
{
|
||||
ArmArchTimerWriteReg (CntpCtl, (VOID *)&Val);
|
||||
}
|
||||
|
||||
VOID
|
||||
EFIAPI
|
||||
ArmArchTimerSetCompareVal (
|
||||
IN UINT64 Val
|
||||
)
|
||||
{
|
||||
ArmArchTimerWriteReg (CntpCval, (VOID *)&Val);
|
||||
}
|
||||
|
|
@ -0,0 +1,119 @@
|
|||
#------------------------------------------------------------------------------
|
||||
#
|
||||
# Copyright (c) 2011, ARM Limited. All rights reserved.
|
||||
#
|
||||
# This program and the accompanying materials
|
||||
# are licensed and made available under the terms and conditions of the BSD License
|
||||
# which accompanies this distribution. The full text of the license may be found at
|
||||
# http://opensource.org/licenses/bsd-license.php
|
||||
#
|
||||
# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
|
||||
# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
|
||||
#
|
||||
#------------------------------------------------------------------------------
|
||||
|
||||
.text
|
||||
.align 2
|
||||
|
||||
GCC_ASM_EXPORT (ArmReadCntFrq)
|
||||
GCC_ASM_EXPORT (ArmWriteCntFrq)
|
||||
GCC_ASM_EXPORT (ArmReadCntPct)
|
||||
GCC_ASM_EXPORT (ArmReadCntkCtl)
|
||||
GCC_ASM_EXPORT (ArmWriteCntkCtl)
|
||||
GCC_ASM_EXPORT (ArmReadCntpTval)
|
||||
GCC_ASM_EXPORT (ArmWriteCntpTval)
|
||||
GCC_ASM_EXPORT (ArmReadCntpCtl)
|
||||
GCC_ASM_EXPORT (ArmWriteCntpCtl)
|
||||
GCC_ASM_EXPORT (ArmReadCntvTval)
|
||||
GCC_ASM_EXPORT (ArmWriteCntvTval)
|
||||
GCC_ASM_EXPORT (ArmReadCntvCtl)
|
||||
GCC_ASM_EXPORT (ArmWriteCntvCtl)
|
||||
GCC_ASM_EXPORT (ArmReadCntvCt)
|
||||
GCC_ASM_EXPORT (ArmReadCntpCval)
|
||||
GCC_ASM_EXPORT (ArmWriteCntpCval)
|
||||
GCC_ASM_EXPORT (ArmReadCntvCval)
|
||||
GCC_ASM_EXPORT (ArmWriteCntvCval)
|
||||
GCC_ASM_EXPORT (ArmReadCntvOff)
|
||||
GCC_ASM_EXPORT (ArmWriteCntvOff)
|
||||
|
||||
ASM_PFX(ArmReadCntFrq):
|
||||
mrc p15, 0, r0, c14, c0, 0 @ Read CNTFRQ
|
||||
bx lr
|
||||
|
||||
ASM_PFX(ArmWriteCntFrq):
|
||||
mcr p15, 0, r0, c14, c0, 0 @ Write to CNTFRQ
|
||||
bx lr
|
||||
|
||||
ASM_PFX(ArmReadCntPct):
|
||||
mrrc p15, 0, r0, r1, c14 @ Read CNTPT (Physical counter register)
|
||||
bx lr
|
||||
|
||||
ASM_PFX(ArmReadCntkCtl):
|
||||
mrc p15, 0, r0, c14, c1, 0 @ Read CNTK_CTL (Timer PL1 Control Register)
|
||||
bx lr
|
||||
|
||||
ASM_PFX(ArmWriteCntkCtl):
|
||||
mcr p15, 0, r0, c14, c1, 0 @ Write to CNTK_CTL (Timer PL1 Control Register)
|
||||
bx lr
|
||||
|
||||
ASM_PFX(ArmReadCntpTval):
|
||||
mrc p15, 0, r0, c14, c2, 0 @ Read CNTP_TVAL (PL1 physical timer value register)
|
||||
bx lr
|
||||
|
||||
ASM_PFX(ArmWriteCntpTval):
|
||||
mcr p15, 0, r0, c14, c2, 0 @ Write to CNTP_TVAL (PL1 physical timer value register)
|
||||
bx lr
|
||||
|
||||
ASM_PFX(ArmReadCntpCtl):
|
||||
mrc p15, 0, r0, c14, c2, 1 @ Read CNTP_CTL (PL1 Physical Timer Control Register)
|
||||
bx lr
|
||||
|
||||
ASM_PFX(ArmWriteCntpCtl):
|
||||
mcr p15, 0, r0, c14, c2, 1 @ Write to CNTP_CTL (PL1 Physical Timer Control Register)
|
||||
bx lr
|
||||
|
||||
ASM_PFX(ArmReadCntvTval):
|
||||
mrc p15, 0, r0, c14, c3, 0 @ Read CNTV_TVAL (Virtual Timer Value register)
|
||||
bx lr
|
||||
|
||||
ASM_PFX(ArmWriteCntvTval):
|
||||
mcr p15, 0, r0, c14, c3, 0 @ Write to CNTV_TVAL (Virtual Timer Value register)
|
||||
bx lr
|
||||
|
||||
ASM_PFX(ArmReadCntvCtl):
|
||||
mrc p15, 0, r0, c14, c3, 1 @ Read CNTV_CTL (Virtual Timer Control Register)
|
||||
bx lr
|
||||
|
||||
ASM_PFX(ArmWriteCntvCtl):
|
||||
mcr p15, 0, r0, c14, c3, 1 @ Write to CNTV_CTL (Virtual Timer Control Register)
|
||||
bx lr
|
||||
|
||||
ASM_PFX(ArmReadCntvCt):
|
||||
mrrc p15, 1, r0, r1, c14 @ Read CNTVCT (Virtual Count Register)
|
||||
bx lr
|
||||
|
||||
ASM_PFX(ArmReadCntpCval):
|
||||
mrrc p15, 2, r0, r1, c14 @ Read CNTP_CTVAL (Physical Timer Compare Value Register)
|
||||
bx lr
|
||||
|
||||
ASM_PFX(ArmWriteCntpCval):
|
||||
mcrr p15, 2, r0, r1, c14 @ Write to CNTP_CTVAL (Physical Timer Compare Value Register)
|
||||
bx lr
|
||||
|
||||
ASM_PFX(ArmReadCntvCval):
|
||||
mrrc p15, 3, r0, r1, c14 @ Read CNTV_CTVAL (Virtual Timer Compare Value Register)
|
||||
bx lr
|
||||
|
||||
ASM_PFX(ArmWriteCntvCval):
|
||||
mcrr p15, 3, r0, r1, c14 @ write to CNTV_CTVAL (Virtual Timer Compare Value Register)
|
||||
bx lr
|
||||
|
||||
ASM_PFX(ArmReadCntvOff):
|
||||
mrrc p15, 4, r0, r1, c14 @ Read CNTVOFF (virtual Offset register)
|
||||
bx lr
|
||||
|
||||
ASM_PFX(ArmWriteCntvOff):
|
||||
mcrr p15, 4, r0, r1, c14 @ Write to CNTVOFF (Virtual Offset register)
|
||||
bx lr
|
||||
|
||||
ASM_FUNCTION_REMOVE_IF_UNREFERENCED
|
||||
|
|
@ -0,0 +1,119 @@
|
|||
//------------------------------------------------------------------------------
|
||||
//
|
||||
// Copyright (c) 2011, ARM Limited. All rights reserved.
|
||||
//
|
||||
// This program and the accompanying materials
|
||||
// are licensed and made available under the terms and conditions of the BSD License
|
||||
// which accompanies this distribution. The full text of the license may be found at
|
||||
// http://opensource.org/licenses/bsd-license.php
|
||||
//
|
||||
// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
|
||||
// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
|
||||
//
|
||||
//------------------------------------------------------------------------------
|
||||
|
||||
EXPORT ArmReadCntFrq
|
||||
EXPORT ArmWriteCntFrq
|
||||
EXPORT ArmReadCntPct
|
||||
EXPORT ArmReadCntkCtl
|
||||
EXPORT ArmWriteCntkCtl
|
||||
EXPORT ArmReadCntpTval
|
||||
EXPORT ArmWriteCntpTval
|
||||
EXPORT ArmReadCntpCtl
|
||||
EXPORT ArmWriteCntpCtl
|
||||
EXPORT ArmReadCntvTval
|
||||
EXPORT ArmWriteCntvTval
|
||||
EXPORT ArmReadCntvCtl
|
||||
EXPORT ArmWriteCntvCtl
|
||||
EXPORT ArmReadCntvCt
|
||||
EXPORT ArmReadCntpCval
|
||||
EXPORT ArmWriteCntpCval
|
||||
EXPORT ArmReadCntvCval
|
||||
EXPORT ArmWriteCntvCval
|
||||
EXPORT ArmReadCntvOff
|
||||
EXPORT ArmWriteCntvOff
|
||||
|
||||
AREA ArmV7ArchTimerSupport, CODE, READONLY
|
||||
PRESERVE8
|
||||
|
||||
ArmReadCntFrq
|
||||
mrc p15, 0, r0, c14, c0, 0 ; Read CNTFRQ
|
||||
bx lr
|
||||
|
||||
ArmWriteCntFrq
|
||||
mcr p15, 0, r0, c14, c0, 0 ; Write to CNTFRQ
|
||||
bx lr
|
||||
|
||||
ArmReadCntPct
|
||||
mrrc p15, 0, r0, r1, c14 ; Read CNTPT (Physical counter register)
|
||||
bx lr
|
||||
|
||||
ArmReadCntkCtl
|
||||
mrc p15, 0, r0, c14, c1, 0 ; Read CNTK_CTL (Timer PL1 Control Register)
|
||||
bx lr
|
||||
|
||||
ArmWriteCntkCtl
|
||||
mcr p15, 0, r0, c14, c1, 0 ; Write to CNTK_CTL (Timer PL1 Control Register)
|
||||
bx lr
|
||||
|
||||
ArmReadCntpTval
|
||||
mrc p15, 0, r0, c14, c2, 0 ; Read CNTP_TVAL (PL1 physical timer value register)
|
||||
bx lr
|
||||
|
||||
ArmWriteCntpTval
|
||||
mcr p15, 0, r0, c14, c2, 0 ; Write to CNTP_TVAL (PL1 physical timer value register)
|
||||
bx lr
|
||||
|
||||
ArmReadCntpCtl
|
||||
mrc p15, 0, r0, c14, c2, 1 ; Read CNTP_CTL (PL1 Physical Timer Control Register)
|
||||
bx lr
|
||||
|
||||
ArmWriteCntpCtl
|
||||
mcr p15, 0, r0, c14, c2, 1 ; Write to CNTP_CTL (PL1 Physical Timer Control Register)
|
||||
bx lr
|
||||
|
||||
ArmReadCntvTval
|
||||
mrc p15, 0, r0, c14, c3, 0 ; Read CNTV_TVAL (Virtual Timer Value register)
|
||||
bx lr
|
||||
|
||||
ArmWriteCntvTval
|
||||
mcr p15, 0, r0, c14, c3, 0 ; Write to CNTV_TVAL (Virtual Timer Value register)
|
||||
bx lr
|
||||
|
||||
ArmReadCntvCtl
|
||||
mrc p15, 0, r0, c14, c3, 1 ; Read CNTV_CTL (Virtual Timer Control Register)
|
||||
bx lr
|
||||
|
||||
ArmWriteCntvCtl
|
||||
mcr p15, 0, r0, c14, c3, 1 ; Write to CNTV_CTL (Virtual Timer Control Register)
|
||||
bx lr
|
||||
|
||||
ArmReadCntvCt
|
||||
mrrc p15, 1, r0, r1, c14 ; Read CNTVCT (Virtual Count Register)
|
||||
bx lr
|
||||
|
||||
ArmReadCntpCval
|
||||
mrrc p15, 2, r0, r1, c14 ; Read CNTP_CTVAL (Physical Timer Compare Value Register)
|
||||
bx lr
|
||||
|
||||
ArmWriteCntpCval
|
||||
mcrr p15, 2, r0, r1, c14 ; Write to CNTP_CTVAL (Physical Timer Compare Value Register)
|
||||
bx lr
|
||||
|
||||
ArmReadCntvCval
|
||||
mrrc p15, 3, r0, r1, c14 ; Read CNTV_CTVAL (Virtual Timer Compare Value Register)
|
||||
bx lr
|
||||
|
||||
ArmWriteCntvCval
|
||||
mcrr p15, 3, r0, r1, c14 ; write to CNTV_CTVAL (Virtual Timer Compare Value Register)
|
||||
bx lr
|
||||
|
||||
ArmReadCntvOff
|
||||
mrrc p15, 4, r0, r1, c14 ; Read CNTVOFF (virtual Offset register)
|
||||
bx lr
|
||||
|
||||
ArmWriteCntvOff
|
||||
mcrr p15, 4, r0, r1, c14 ; Write to CNTVOFF (Virtual Offset register)
|
||||
bx lr
|
||||
|
||||
END
|
||||
|
|
@ -35,6 +35,10 @@
|
|||
ArmV7Lib.c
|
||||
ArmV7Mmu.c
|
||||
|
||||
ArmV7ArchTimer.c
|
||||
ArmV7ArchTimerSupport.S | GCC
|
||||
ArmV7ArchTimerSupport.asm | RVCT
|
||||
|
||||
[Packages]
|
||||
ArmPkg/ArmPkg.dec
|
||||
MdePkg/MdePkg.dec
|
||||
|
|
|
|||
|
|
@ -35,6 +35,10 @@
|
|||
ArmV7Lib.c
|
||||
ArmV7Mmu.c
|
||||
|
||||
ArmV7ArchTimer.c
|
||||
ArmV7ArchTimerSupport.S | GCC
|
||||
ArmV7ArchTimerSupport.asm | RVCT
|
||||
|
||||
[Packages]
|
||||
ArmPkg/ArmPkg.dec
|
||||
MdePkg/MdePkg.dec
|
||||
|
|
|
|||
|
|
@ -32,6 +32,10 @@
|
|||
|
||||
ArmV7Lib.c
|
||||
|
||||
ArmV7ArchTimer.c
|
||||
ArmV7ArchTimerSupport.S | GCC
|
||||
ArmV7ArchTimerSupport.asm | RVCT
|
||||
|
||||
[Packages]
|
||||
ArmPkg/ArmPkg.dec
|
||||
MdePkg/MdePkg.dec
|
||||
|
|
|
|||
Loading…
Reference in New Issue