diff --git a/PcAtChipsetPkg/PciHostBridgeDxe/PciRootBridgeIo.c b/PcAtChipsetPkg/PciHostBridgeDxe/PciRootBridgeIo.c
index edbe4a03b2..a33836569b 100644
--- a/PcAtChipsetPkg/PciHostBridgeDxe/PciRootBridgeIo.c
+++ b/PcAtChipsetPkg/PciHostBridgeDxe/PciRootBridgeIo.c
@@ -914,6 +914,13 @@ RootBridgeIoMemRW (
         case EfiPciWidthUint64:
           MmioWrite64 ((UINTN)Address, *((UINT64 *)Uint8Buffer));
           break;
+        default:
+          //
+          // The RootBridgeIoCheckParameter call above will ensure that this
+          // path is not taken.
+          //
+          ASSERT (FALSE);
+          break;
       }
     } else {
       switch (OperationWidth) {
@@ -929,6 +936,13 @@ RootBridgeIoMemRW (
         case EfiPciWidthUint64:
           *((UINT64 *)Uint8Buffer) = MmioRead64 ((UINTN)Address);
           break;
+        default:
+          //
+          // The RootBridgeIoCheckParameter call above will ensure that this
+          // path is not taken.
+          //
+          ASSERT (FALSE);
+          break;
       }
     }
   }
@@ -989,6 +1003,13 @@ RootBridgeIoIoRW (
         case EfiPciWidthUint32:
           IoWrite32 ((UINTN)Address, *((UINT32 *)Uint8Buffer));
           break;
+        default:
+          //
+          // The RootBridgeIoCheckParameter call above will ensure that this
+          // path is not taken.
+          //
+          ASSERT (FALSE);
+          break;
       }
     } else {
       switch (OperationWidth) {
@@ -1001,6 +1022,13 @@ RootBridgeIoIoRW (
         case EfiPciWidthUint32:
           *((UINT32 *)Uint8Buffer) = IoRead32 ((UINTN)Address);
           break;
+        default:
+          //
+          // The RootBridgeIoCheckParameter call above will ensure that this
+          // path is not taken.
+          //
+          ASSERT (FALSE);
+          break;
       }
     }
   }
@@ -1074,6 +1102,13 @@ RootBridgeIoPciRW (
         case EfiPciWidthUint32:
           PciWrite32 (PcieRegAddr, *((UINT32 *)Uint8Buffer));
           break;
+        default:
+          //
+          // The RootBridgeIoCheckParameter call above will ensure that this
+          // path is not taken.
+          //
+          ASSERT (FALSE);
+          break;
       }
     } else {
       switch (OperationWidth) {
@@ -1086,6 +1121,13 @@ RootBridgeIoPciRW (
         case EfiPciWidthUint32:
           *((UINT32 *)Uint8Buffer) = PciRead32 (PcieRegAddr);
           break;
+        default:
+          //
+          // The RootBridgeIoCheckParameter call above will ensure that this
+          // path is not taken.
+          //
+          ASSERT (FALSE);
+          break;
       }
     }
   }