mirror of https://github.com/acidanthera/audk.git
OvmfPkg/LegacyRegion: Support legacy region manipulation of Q35
Current implementation only supports legacy region of 440 chip. When QEMU is launched in Q35 mode using CSM enabled OVMF image, LegacyBios driver fails to start due to the legacy region [0xC0000, 0xFFFFF] cannot be written. v2: * just updates the comments. v3: * uses PcdOvmfHostBridgePciDevId as Jordan suggested. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ruiyu Ni <ruiyu.ni@intel.com> Cc: Justen Jordan <jordan.l.justen@intel.com> Cc: Laszlo Ersek <lersek@redhat.com> Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
This commit is contained in:
Ruiyu Ni
Jordan Justen
parent
89a811538e
commit
db27e9f3d8
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@ -1,7 +1,7 @@
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/** @file
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Legacy Region Support
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Copyright (c) 2006 - 2011, Intel Corporation. All rights reserved.<BR>
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Copyright (c) 2006 - 2016, Intel Corporation. All rights reserved.<BR>
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This program and the accompanying materials are
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licensed and made available under the terms and conditions of the BSD License
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@ -16,23 +16,24 @@
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#include "LegacyRegion.h"
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//
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// 440 PAM map.
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// 440/Q35 PAM map.
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//
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// PAM Range Offset Bits Operation
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// =============== ====== ==== ===============================================================
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// 0xC0000-0xC3FFF 0x5a 1:0 00 = DRAM Disabled, 01= Read Only, 10 = Write Only, 11 = Normal
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// 0xC4000-0xC7FFF 0x5a 5:4 00 = DRAM Disabled, 01= Read Only, 10 = Write Only, 11 = Normal
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// 0xC8000-0xCBFFF 0x5b 1:0 00 = DRAM Disabled, 01= Read Only, 10 = Write Only, 11 = Normal
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// 0xCC000-0xCFFFF 0x5b 5:4 00 = DRAM Disabled, 01= Read Only, 10 = Write Only, 11 = Normal
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// 0xD0000-0xD3FFF 0x5c 1:0 00 = DRAM Disabled, 01= Read Only, 10 = Write Only, 11 = Normal
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// 0xD4000-0xD7FFF 0x5c 5:4 00 = DRAM Disabled, 01= Read Only, 10 = Write Only, 11 = Normal
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// 0xD8000-0xDBFFF 0x5d 1:0 00 = DRAM Disabled, 01= Read Only, 10 = Write Only, 11 = Normal
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// 0xDC000-0xDFFFF 0x5d 5:4 00 = DRAM Disabled, 01= Read Only, 10 = Write Only, 11 = Normal
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// 0xE0000-0xE3FFF 0x5e 1:0 00 = DRAM Disabled, 01= Read Only, 10 = Write Only, 11 = Normal
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// 0xE4000-0xE7FFF 0x5e 5:4 00 = DRAM Disabled, 01= Read Only, 10 = Write Only, 11 = Normal
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// 0xE8000-0xEBFFF 0x5f 1:0 00 = DRAM Disabled, 01= Read Only, 10 = Write Only, 11 = Normal
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// 0xEC000-0xEFFFF 0x5f 5:4 00 = DRAM Disabled, 01= Read Only, 10 = Write Only, 11 = Normal
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// 0xF0000-0xFFFFF 0x59 5:4 00 = DRAM Disabled, 01= Read Only, 10 = Write Only, 11 = Normal
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// PAM Range Offset Bits Operation
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// 440 Q35
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// =============== ==== ==== ==== ===============================================================
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// 0xC0000-0xC3FFF 0x5a 0x91 1:0 00 = DRAM Disabled, 01= Read Only, 10 = Write Only, 11 = Normal
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// 0xC4000-0xC7FFF 0x5a 0x91 5:4 00 = DRAM Disabled, 01= Read Only, 10 = Write Only, 11 = Normal
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// 0xC8000-0xCBFFF 0x5b 0x92 1:0 00 = DRAM Disabled, 01= Read Only, 10 = Write Only, 11 = Normal
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// 0xCC000-0xCFFFF 0x5b 0x92 5:4 00 = DRAM Disabled, 01= Read Only, 10 = Write Only, 11 = Normal
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// 0xD0000-0xD3FFF 0x5c 0x93 1:0 00 = DRAM Disabled, 01= Read Only, 10 = Write Only, 11 = Normal
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// 0xD4000-0xD7FFF 0x5c 0x93 5:4 00 = DRAM Disabled, 01= Read Only, 10 = Write Only, 11 = Normal
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// 0xD8000-0xDBFFF 0x5d 0x94 1:0 00 = DRAM Disabled, 01= Read Only, 10 = Write Only, 11 = Normal
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// 0xDC000-0xDFFFF 0x5d 0x94 5:4 00 = DRAM Disabled, 01= Read Only, 10 = Write Only, 11 = Normal
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// 0xE0000-0xE3FFF 0x5e 0x95 1:0 00 = DRAM Disabled, 01= Read Only, 10 = Write Only, 11 = Normal
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// 0xE4000-0xE7FFF 0x5e 0x95 5:4 00 = DRAM Disabled, 01= Read Only, 10 = Write Only, 11 = Normal
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// 0xE8000-0xEBFFF 0x5f 0x96 1:0 00 = DRAM Disabled, 01= Read Only, 10 = Write Only, 11 = Normal
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// 0xEC000-0xEFFFF 0x5f 0x96 5:4 00 = DRAM Disabled, 01= Read Only, 10 = Write Only, 11 = Normal
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// 0xF0000-0xFFFFF 0x59 0x90 5:4 00 = DRAM Disabled, 01= Read Only, 10 = Write Only, 11 = Normal
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//
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STATIC LEGACY_MEMORY_SECTION_INFO mSectionArray[] = {
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{0xC0000, SIZE_16KB, FALSE, FALSE},
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@ -50,22 +51,40 @@ STATIC LEGACY_MEMORY_SECTION_INFO mSectionArray[] = {
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{0xF0000, SIZE_64KB, FALSE, FALSE}
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};
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STATIC PAM_REGISTER_VALUE mRegisterValues[] = {
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{REG_PAM1_OFFSET, 0x01, 0x02},
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{REG_PAM1_OFFSET, 0x10, 0x20},
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{REG_PAM2_OFFSET, 0x01, 0x02},
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{REG_PAM2_OFFSET, 0x10, 0x20},
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{REG_PAM3_OFFSET, 0x01, 0x02},
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{REG_PAM3_OFFSET, 0x10, 0x20},
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{REG_PAM4_OFFSET, 0x01, 0x02},
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{REG_PAM4_OFFSET, 0x10, 0x20},
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{REG_PAM5_OFFSET, 0x01, 0x02},
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{REG_PAM5_OFFSET, 0x10, 0x20},
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{REG_PAM6_OFFSET, 0x01, 0x02},
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{REG_PAM6_OFFSET, 0x10, 0x20},
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{REG_PAM0_OFFSET, 0x10, 0x20}
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STATIC PAM_REGISTER_VALUE mRegisterValues440[] = {
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{REG_PAM1_OFFSET_440, 0x01, 0x02},
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{REG_PAM1_OFFSET_440, 0x10, 0x20},
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{REG_PAM2_OFFSET_440, 0x01, 0x02},
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{REG_PAM2_OFFSET_440, 0x10, 0x20},
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{REG_PAM3_OFFSET_440, 0x01, 0x02},
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{REG_PAM3_OFFSET_440, 0x10, 0x20},
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{REG_PAM4_OFFSET_440, 0x01, 0x02},
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{REG_PAM4_OFFSET_440, 0x10, 0x20},
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{REG_PAM5_OFFSET_440, 0x01, 0x02},
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{REG_PAM5_OFFSET_440, 0x10, 0x20},
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{REG_PAM6_OFFSET_440, 0x01, 0x02},
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{REG_PAM6_OFFSET_440, 0x10, 0x20},
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{REG_PAM0_OFFSET_440, 0x10, 0x20}
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};
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STATIC PAM_REGISTER_VALUE mRegisterValuesQ35[] = {
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{REG_PAM1_OFFSET_Q35, 0x01, 0x02},
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{REG_PAM1_OFFSET_Q35, 0x10, 0x20},
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{REG_PAM2_OFFSET_Q35, 0x01, 0x02},
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{REG_PAM2_OFFSET_Q35, 0x10, 0x20},
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{REG_PAM3_OFFSET_Q35, 0x01, 0x02},
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{REG_PAM3_OFFSET_Q35, 0x10, 0x20},
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{REG_PAM4_OFFSET_Q35, 0x01, 0x02},
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{REG_PAM4_OFFSET_Q35, 0x10, 0x20},
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{REG_PAM5_OFFSET_Q35, 0x01, 0x02},
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{REG_PAM5_OFFSET_Q35, 0x10, 0x20},
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{REG_PAM6_OFFSET_Q35, 0x01, 0x02},
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{REG_PAM6_OFFSET_Q35, 0x10, 0x20},
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{REG_PAM0_OFFSET_Q35, 0x10, 0x20}
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};
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STATIC PAM_REGISTER_VALUE *mRegisterValues;
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//
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// Handle used to install the Legacy Region Protocol
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//
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@ -450,6 +469,25 @@ LegacyRegionInit (
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)
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{
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EFI_STATUS Status;
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UINT16 HostBridgeDevId;
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//
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// Query Host Bridge DID to determine platform type
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//
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HostBridgeDevId = PcdGet16 (PcdOvmfHostBridgePciDevId);
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switch (HostBridgeDevId) {
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case INTEL_82441_DEVICE_ID:
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mRegisterValues = mRegisterValues440;
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break;
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case INTEL_Q35_MCH_DEVICE_ID:
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mRegisterValues = mRegisterValuesQ35;
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break;
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default:
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DEBUG ((EFI_D_ERROR, "%a: Unknown Host Bridge Device ID: 0x%04x\n",
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__FUNCTION__, HostBridgeDevId));
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ASSERT (FALSE);
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return RETURN_UNSUPPORTED;
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}
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//
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// Install the Legacy Region Protocol on a new handle
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@ -1,7 +1,7 @@
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/** @file
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Legacy Region Support
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Copyright (c) 2008 - 2011, Intel Corporation. All rights reserved.<BR>
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Copyright (c) 2008 - 2016, Intel Corporation. All rights reserved.<BR>
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This program and the accompanying materials are
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licensed and made available under the terms and conditions of the BSD License
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@ -21,6 +21,8 @@
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#include <Protocol/LegacyRegion2.h>
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#include <IndustryStandard/Pci.h>
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#include <IndustryStandard/Q35MchIch9.h>
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#include <IndustryStandard/I440FxPiix4.h>
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#include <Library/PciLib.h>
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#include <Library/PcdLib.h>
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@ -32,13 +34,21 @@
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#define PAM_PCI_DEV 0
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#define PAM_PCI_FUNC 0
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#define REG_PAM0_OFFSET 0x59 // Programmable Attribute Map 0
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#define REG_PAM1_OFFSET 0x5a // Programmable Attribute Map 1
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#define REG_PAM2_OFFSET 0x5b // Programmable Attribute Map 2
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#define REG_PAM3_OFFSET 0x5c // Programmable Attribute Map 3
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#define REG_PAM4_OFFSET 0x5d // Programmable Attribute Map 4
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#define REG_PAM5_OFFSET 0x5e // Programmable Attribute Map 5
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#define REG_PAM6_OFFSET 0x5f // Programmable Attribute Map 6
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#define REG_PAM0_OFFSET_440 0x59 // Programmable Attribute Map 0
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#define REG_PAM1_OFFSET_440 0x5a // Programmable Attribute Map 1
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#define REG_PAM2_OFFSET_440 0x5b // Programmable Attribute Map 2
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#define REG_PAM3_OFFSET_440 0x5c // Programmable Attribute Map 3
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#define REG_PAM4_OFFSET_440 0x5d // Programmable Attribute Map 4
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#define REG_PAM5_OFFSET_440 0x5e // Programmable Attribute Map 5
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#define REG_PAM6_OFFSET_440 0x5f // Programmable Attribute Map 6
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#define REG_PAM0_OFFSET_Q35 0x90 // Programmable Attribute Map 0
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#define REG_PAM1_OFFSET_Q35 0x91 // Programmable Attribute Map 1
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#define REG_PAM2_OFFSET_Q35 0x92 // Programmable Attribute Map 2
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#define REG_PAM3_OFFSET_Q35 0x93 // Programmable Attribute Map 3
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#define REG_PAM4_OFFSET_Q35 0x94 // Programmable Attribute Map 4
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#define REG_PAM5_OFFSET_Q35 0x95 // Programmable Attribute Map 5
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#define REG_PAM6_OFFSET_Q35 0x96 // Programmable Attribute Map 6
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#define PAM_BASE_ADDRESS 0xc0000
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#define PAM_LIMIT_ADDRESS BASE_1MB
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