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For the data region which will be touched by Pci Bus Master, we should allocate memory by PciIo.AllocateBuffer() but not AllocatePool() base library API. So the memory region can be used to map into Pci controller-specific address thru PciIo.Map(). 

git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@9323 6f19259b-4bc3-4df7-8a09-765794883524
This commit is contained in:
eric_tian 2009-09-30 03:00:36 +00:00
parent 4009f91688
commit db731882fa
2 changed files with 2 additions and 2 deletions
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2
MdeModulePkg/Bus/Pci/UhciDxe/Uhci.c
View File

@ -1001,7 +1001,7 @@ Uhci2AsyncInterruptTransfer (
//
// Allocate and map source data buffer for bus master access.
//
DataPtr = AllocatePool (DataLength);
DataPtr = UsbHcAllocateMem (Uhc->MemPool, DataLength);
if (DataPtr == NULL) {
return EFI_OUT_OF_RESOURCES;

2
MdeModulePkg/Bus/Pci/UhciDxe/UhciSched.c
View File

@ -798,7 +798,7 @@ UhciFreeAsyncReq (
}
if (AsyncReq->Data != NULL) {
gBS->FreePool (AsyncReq->Data);
UsbHcFreeMem (Uhc->MemPool, AsyncReq->Data, AsyncReq->DataLen);
}
gBS->FreePool (AsyncReq);