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MdeModulePkg/XhciDxe: fix a bug on TRB check in async int transfer 

The last TRB in transfer ring is a LINK type TRB, which shouldn't
be accounted as a valid item in IsAsyncIntTrb().

Without this fix, the original algo will bring issue on those URBs
whose TRBs crosses the transfer ring.

Cc: Star Zeng <star.zeng@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Feng Tian <feng.tian@intel.com>
Reviewed-by: Star Zeng <star.zeng@intel.com>
This commit is contained in:
Feng Tian 2016-07-11 11:17:05 +08:00
parent bf4808d644
commit db98a8bdb8
1 changed files with 5 additions and 1 deletions
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6
MdeModulePkg/Bus/Pci/XhciDxe/XhciSched.c
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@ -1009,7 +1009,11 @@ IsAsyncIntTrb (
return TRUE;
}
CheckedTrb++;
if ((UINTN)CheckedTrb >= ((UINTN) CheckedUrb->Ring->RingSeg0 + sizeof (TRB_TEMPLATE) * CheckedUrb->Ring->TrbNumber)) {
//
// If the checked TRB is the link TRB at the end of the transfer ring,
// recircle it to the head of the ring.
//
if (CheckedTrb->Type == TRB_TYPE_LINK) {
CheckedTrb = (TRB_TEMPLATE*) CheckedUrb->Ring->RingSeg0;
}
}