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ArmPlatformPkg/Documentation: Update ArmPLatformPkg documentation with PCD descriptions and explain how to port UEFI to new ARM platforms
git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@11994 6f19259b-4bc3-4df7-8a09-765794883524
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Porting UEFI to a ARM platform
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Porting UEFI to a ARM platform :
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------------------------------
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1. Create the new platform directory under ArmPlatformPkg
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1. Create the new platform directory under ArmPlatformPkg
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2. Create its DSC and FDF files into this new directory. These files can be copied from ArmVExpress-CTA9x4.dsc and ArmVExpress-CTA9x4.fdf; and adapted following the requirement of your platform.
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2. Create its DSC and FDF files into this new directory. These files can be copied from ArmVExpress-CTA9x4.dsc and ArmVExpress-CTA9x4.fdf; and adapted following the requirement of your platform.
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3. Set up the PCDs required by ArmPlatformPkg in your FDF or DSC files
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3. Set up the PCDs required by ArmPlatformPkg in your FDF or DSC files
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PCD Description
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gArmTokenSpaceGuid.PcdSecureFdBaseAddress : Base address of your Secure Firmware
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gArmTokenSpaceGuid.PcdSecureFdSize : Size in byte of your Secure Firmware gEmbeddedTokenSpaceGuid.
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gArmTokenSpaceGuid.PcdNormalFdBaseAddress : Base Address of your Non-Secure Firmware gEmbeddedTokenSpaceGuid.
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gArmTokenSpaceGuid.PcdNormalFdSize : Size in bytes of your Non-Secure Firmware
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gArmTokenSpaceGuid.PcdL2x0ControllerBase : Base Address of your L2x0 controller
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gArmTokenSpaceGuid.PcdGicDistributorBase : Base address of the Distributor of your General Interrupt Controller gArmTokenSpaceGuid.
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PcdGicInterruptInterfaceBase : Base address of the Interface of your General Interrupt Controller gArmVExpressTokenSpaceGuid.
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PcdCPUCoresSecStackBase : Top of Secure Stack for Secure World gArmVExpressTokenSpaceGuid.
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PcdCPUCoreSecStackSize : Size of the stack for each of the 4 CPU cores gArmVExpressTokenSpaceGuid.
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PcdCPUCoresSecMonStackBase : Top of Stack for Monitor World gArmVExpressTokenSpaceGuid.
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PcdCPUCoreSecMonStackSize : Size of the stack for each of the 4 CPU cores gArmVExpressTokenSpaceGuid.
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PcdCPUCoresNonSecStackBase : Top of SEC Stack for Normal World gArmVExpressTokenSpaceGuid.
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PcdCPUCoresNonSecStackSize : Size of the stack for each of the 4 CPU Cores gArmVExpressTokenSpaceGuid.
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PcdPeiServicePtrAddr : Cached value of PeiServicesTable
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4. Implement 'ArmPlatformLib' for your platform following the interface defined by ArmPlatformPkg\Include\Library\ArmPlatformLib.h.
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4. Implement 'ArmPlatformLib' for your platform following the interface defined by ArmPlatformPkg\Include\Library\ArmPlatformLib.h.
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Functions to implement:
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VOID ArmPlatformIsMemoryInitialized(VOID);
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PCDs Description :
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VOID ArmPlatformInitializeBootMemory(VOID);
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-------------------
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VOID ArmPlatformInitializeSystemMemory(VOID);
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VOID ArmPlatformBootRemapping(VOID);
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# Firmware Device / Volume
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UINTN ArmPlatformTrustzoneSupported(VOID);
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gArmTokenSpaceGuid.PcdSecureFdBaseAddress : Base address of your Secure Firmware Device
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VOID ArmPlatformTrustzoneInit(VOID);
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gArmTokenSpaceGuid.PcdSecureFdSize : Size in byte of your Secure Firmware Device.
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VOID ArmPlatformGetPeiMemory (
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gArmTokenSpaceGuid.PcdNormalFdBaseAddress : Base Address of your Non-Secure/Normal World Firmware Device.
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OUT UINTN* PeiMemoryBase,
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gArmTokenSpaceGuid.PcdNormalFdSize : Size in bytes of your Non-Secure/Normal World Firmware Device
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OUT UINTN* PeiMemorySize);
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VOID ArmPlatformGetVirtualMemoryMap (
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# Stacks
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OUT ARM_MEMORY_REGION_DESCRIPTOR** VirtualMemoryMap);
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gArmPlatformTokenSpaceGuid.PcdCPUCoresSecStackBase : Top of Secure Stack for Secure World
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VOID ArmPlatformGetEfiMemoryMap (
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gArmPlatformTokenSpaceGuid.PcdCPUCoreSecStackSize : Size of the stack for each of the 4 CPU cores
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OUT ARM_SYSTEM_MEMORY_REGION_DESCRIPTOR** EfiMemoryMap)
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gArmPlatformTokenSpaceGuid.PcdCPUCoresSecMonStackBase : Top of Stack for Monitor World
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gArmPlatformTokenSpaceGuid.PcdCPUCoreSecMonStackSize : Size of the stack for each of the 4 CPU cores
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gArmPlatformTokenSpaceGuid.PcdCPUCoresNonSecStackBase : Top of SEC Stack for Normal World
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gArmPlatformTokenSpaceGuid.PcdCPUCoresNonSecStackSize : Size of the stack for each of the 4 CPU Cores
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# CPU / Architectural controllers
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gArmTokenSpaceGuid.PcdGicDistributorBase : Base address of the Distributor of your General Interrupt Controller
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gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase : Base address of the Interface of your General Interrupt Controller
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gArmPlatformTokenSpaceGuid.PcdMPCoreSupport : Set to 1 when MP Core platforms
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gArmPlatformTokenSpaceGuid.PcdMPCoreMaxCores : Maximum number of CPU cores on the platform (used for instance to know how many stacks we need to configure)
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# Memory Regions
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gArmPlatformTokenSpaceGuid.PcdSystemMemoryUefiRegionSize : Size of the region reserve for PI & UEFI
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gArmTokenSpaceGuid.PcdSystemMemoryBase : Base Address of the System Memory (DRAM)
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gArmTokenSpaceGuid.PcdSystemMemorySize : Size of the System Memory (DRAM)
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# Features
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gArmPlatformTokenSpaceGuid.PcdSystemMemoryInitializeInSec : TRUE if System Memory initialized by the SEC phase
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gArmPlatformTokenSpaceGuid.PcdSendSgiToBringUpSecondaryCores : TRUE if the PrePi or PrePeiCore modules have to send an SGI to resume the excution of the secondary cores
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# Boot Manager
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gArmPlatformTokenSpaceGuid.PcdDefaultBootDescription : Description of the Default Boot Entry
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gArmPlatformTokenSpaceGuid.PcdDefaultBootDevicePath : DevicePath of the Default Boot Entry
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gArmPlatformTokenSpaceGuid.PcdDefaultBootArgument : Argument for the Default Boot Entry
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gArmPlatformTokenSpaceGuid.PcdDefaultBootType : Define the binary type of the Default Boot Entry (0=EFI application, 1=Linux kernel with ATAG support, 2=Linux Kernel with FDT support)
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gArmPlatformTokenSpaceGuid.PcdFdtDevicePath : DevicePath of the Platform Device Tree
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gArmPlatformTokenSpaceGuid.PcdPlatformBootTimeOut : Timeout before booting on the Device Boot entry (by default the auto boot is skipped)
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gArmPlatformTokenSpaceGuid.PcdDefaultConInPaths : List of Device Path use for the Console Input
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gArmPlatformTokenSpaceGuid.PcdDefaultConOutPaths : List of Device Path use for the Console Output
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FAQ :
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-----
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# When to use PrePi or PrePeiCore ?
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- PrePi: when the memory has already been initialized by the first stage boot loader
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Boot sequence: PlatformFirmware/PrePi/Dxe/Bds
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Example: Beagle Board
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- PrePeiCore: when the firmware is started from XIP memory and in Secure world. The PeiCore shadows the firmware itself in System Memory (DRAM)
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Boot sequence: Sec/PrePiCore/PeiCore/Dxe/Bds
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Example: ARM Versatile Express
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# What is the PcdStandalone
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gArmPlatformTokenSpaceGuid.PcdStandalone=FALSE is used on ARM Development Platforms during the development stage.
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To avoid to reflash the NOR Flash after each build, the SEC (in NOR Flash) intializes thd DRAM and wait until the Normal World firmware is copied into the DRAM.
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Copying the firmware in DRAM is much faster than reflashing the NOR Flash. It is also more convenient to debug the firmware form DRAM than NOR Flash (eg: use of software breakpoint)
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