MdePkg/Baseib: Filter/trace MSR access for IA32/X64

REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3246

Cc: Michael D Kinney <michael.d.kinney@intel.com>
Cc: Liming Gao <gaoliming@byosoft.com.cn>
Cc: Zhiguang Liu <zhiguang.liu@intel.com>
Signed-off-by: Dandan Bi <dandan.bi@intel.com>
Reviewed-by: Michael D Kinney <michael.d.kinney@intel.com>
Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn>
Acked-by: Ard Biesheuvel <ardb@kernel.org>

MdePkg/Library/BaseLib/BaseLib.inf

@@ -413,6 +413,9 @@
   DebugLib
   BaseMemoryLib
 
+[LibraryClasses.X64, LibraryClasses.IA32]
+  RegisterFilterLib
+
 [Pcd]
   gEfiMdePkgTokenSpaceGuid.PcdMaximumLinkedListLength      ## SOMETIMES_CONSUMES
   gEfiMdePkgTokenSpaceGuid.PcdMaximumAsciiStringLength     ## SOMETIMES_CONSUMES

MdePkg/Library/BaseLib/Ia32/GccInlinePriv.c

@@ -2,7 +2,7 @@
   GCC inline implementation of BaseLib processor specific functions that use
   privlidged instructions.
 
-  Copyright (c) 2006 - 2020, Intel Corporation. All rights reserved.<BR>
+  Copyright (c) 2006 - 2021, Intel Corporation. All rights reserved.<BR>
   Portions copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
   SPDX-License-Identifier: BSD-2-Clause-Patent
 
@@ -10,6 +10,7 @@
 
 
 #include "BaseLibInternals.h"
+#include <Library/RegisterFilterLib.h>
 
 /**
   Enables CPU interrupts.
@@ -63,12 +64,17 @@ AsmReadMsr64 (
   )
 {
   UINT64 Data;
+  BOOLEAN Flag;
 
-  __asm__ __volatile__ (
+  Flag = FilterBeforeMsrRead (Index, &Data);
-    "rdmsr"
+  if (Flag) {
-    : "=A" (Data)   // %0
+    __asm__ __volatile__ (
-    : "c"  (Index)  // %1
+      "rdmsr"
-    );
+      : "=A" (Data)   // %0
+      : "c"  (Index)  // %1
+      );
+  }
+  FilterAfterMsrRead (Index, &Data);
 
   return Data;
 }
@@ -97,12 +103,18 @@ AsmWriteMsr64 (
   IN      UINT64                    Value
   )
 {
-  __asm__ __volatile__ (
+  BOOLEAN  Flag;
-    "wrmsr"
+
-    :
+  Flag = FilterBeforeMsrWrite (Index, &Value);
-    : "c" (Index),
+  if (Flag) {
-      "A" (Value)
+    __asm__ __volatile__ (
-    );
+      "wrmsr"
+      :
+      : "c" (Index),
+        "A" (Value)
+      );
+  }
+  FilterAfterMsrWrite (Index, &Value);
 
   return Value;
 }

MdePkg/Library/BaseLib/Ia32/ReadMsr64.c

@@ -1,13 +1,38 @@
 /** @file
   AsmReadMsr64 function
 
-  Copyright (c) 2006 - 2008, Intel Corporation. All rights reserved.<BR>
+  Copyright (c) 2006 - 2021, Intel Corporation. All rights reserved.<BR>
   SPDX-License-Identifier: BSD-2-Clause-Patent
 
 **/
 
 
+#include <Library/RegisterFilterLib.h>
 
+/**
+  Returns a 64-bit Machine Specific Register(MSR).
+
+  Reads and returns the 64-bit MSR specified by Index. No parameter checking is
+  performed on Index, and some Index values may cause CPU exceptions. The
+  caller must either guarantee that Index is valid, or the caller must set up
+  exception handlers to catch the exceptions. This function is only available
+  on IA-32 and x64.
+
+  @param  Index The 32-bit MSR index to read.
+
+  @return The value of the MSR identified by Index.
+
+**/
+UINT64
+AsmReadMsr64Internal (
+  IN UINT32  Index
+  )
+{
+  _asm {
+    mov     ecx, Index
+    rdmsr
+  }
+}
 
 /**
   Returns a 64-bit Machine Specific Register(MSR).
@@ -29,9 +54,14 @@ AsmReadMsr64 (
   IN UINT32  Index
   )
 {
-  _asm {
+  UINT64                            Value;
-    mov     ecx, Index
+  BOOLEAN                           Flag;
-    rdmsr
-  }
-}
 
+  Flag = FilterBeforeMsrRead (Index, &Value);
+  if (Flag) {
+    Value = AsmReadMsr64Internal (Index);
+  }
+  FilterAfterMsrRead (Index, &Value);
+
+  return Value;
+}

MdePkg/Library/BaseLib/Ia32/WriteMsr64.c

@@ -1,13 +1,13 @@
 /** @file
   AsmWriteMsr64 function
 
-  Copyright (c) 2006 - 2008, Intel Corporation. All rights reserved.<BR>
+  Copyright (c) 2006 - 2021, Intel Corporation. All rights reserved.<BR>
   SPDX-License-Identifier: BSD-2-Clause-Patent
 
 **/
 
 
-
+#include <Library/RegisterFilterLib.h>
 
 /**
   Writes a 64-bit value to a Machine Specific Register(MSR), and returns the
@@ -33,11 +33,19 @@ AsmWriteMsr64 (
   IN UINT64  Value
   )
 {
-  _asm {
+  BOOLEAN                           Flag;
-    mov     edx, dword ptr [Value + 4]
+
-    mov     eax, dword ptr [Value + 0]
+  Flag = FilterBeforeMsrWrite (Index, &Value);
-    mov     ecx, Index
+  if (Flag) {
-    wrmsr
+    _asm {
+      mov     edx, dword ptr [Value + 4]
+      mov     eax, dword ptr [Value + 0]
+      mov     ecx, Index
+      wrmsr
+    }
   }
+  FilterAfterMsrWrite (Index, &Value);
+
+  return Value;
 }
 

MdePkg/Library/BaseLib/X64/GccInlinePriv.c

@@ -2,7 +2,7 @@
   GCC inline implementation of BaseLib processor specific functions that use
   privlidged instructions.
 
-  Copyright (c) 2006 - 2020, Intel Corporation. All rights reserved.<BR>
+  Copyright (c) 2006 - 2021, Intel Corporation. All rights reserved.<BR>
   Portions copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
   SPDX-License-Identifier: BSD-2-Clause-Patent
 
@@ -10,6 +10,7 @@
 
 
 #include "BaseLibInternals.h"
+#include <Library/RegisterFilterLib.h>
 
 /**
   Enables CPU interrupts.
@@ -64,13 +65,20 @@ AsmReadMsr64 (
 {
   UINT32 LowData;
   UINT32 HighData;
+  UINT64 Value;
+  BOOLEAN Flag;
 
-  __asm__ __volatile__ (
+  Flag = FilterBeforeMsrRead (Index, &Value);
-    "rdmsr"
+  if (Flag) {
-    : "=a" (LowData),   // %0
+    __asm__ __volatile__ (
-      "=d" (HighData)   // %1
+      "rdmsr"
-    : "c"  (Index)      // %2
+      : "=a" (LowData),   // %0
-    );
+        "=d" (HighData)   // %1
+      : "c"  (Index)      // %2
+      );
+    Value = (((UINT64)HighData) << 32) | LowData;
+  }
+  FilterAfterMsrRead (Index, &Value);
 
   return (((UINT64)HighData) << 32) | LowData;
 }
@@ -101,17 +109,22 @@ AsmWriteMsr64 (
 {
   UINT32 LowData;
   UINT32 HighData;
+  BOOLEAN Flag;
 
   LowData  = (UINT32)(Value);
   HighData = (UINT32)(Value >> 32);
 
-  __asm__ __volatile__ (
+  Flag = FilterBeforeMsrWrite (Index, &Value);
-    "wrmsr"
+  if (Flag) {
-    :
+    __asm__ __volatile__ (
-    : "c" (Index),
+      "wrmsr"
-      "a" (LowData),
+      :
-      "d" (HighData)
+      : "c" (Index),
-    );
+        "a" (LowData),
+        "d" (HighData)
+      );
+  }
+  FilterAfterMsrWrite (Index, &Value);
 
   return Value;
 }

MdePkg/Library/BaseLib/X64/ReadMsr64.c

@@ -1,7 +1,7 @@
 /** @file
   CpuBreakpoint function.
 
-  Copyright (c) 2006 - 2008, Intel Corporation. All rights reserved.<BR>
+  Copyright (c) 2006 - 2021, Intel Corporation. All rights reserved.<BR>
   SPDX-License-Identifier: BSD-2-Clause-Patent
 
 **/
@@ -10,6 +10,8 @@
   Microsoft Visual Studio 7.1 Function Prototypes for I/O Intrinsics.
 **/
 
+#include <Library/RegisterFilterLib.h>
+
 unsigned __int64 __readmsr (int register);
 
 #pragma intrinsic(__readmsr)
@@ -28,6 +30,15 @@ AsmReadMsr64 (
   IN UINT32  Index
   )
 {
-  return __readmsr (Index);
+  UINT64                            Value;
+  BOOLEAN                           Flag;
+
+  Flag = FilterBeforeMsrRead (Index, &Value);
+  if (Flag) {
+    Value = __readmsr (Index);
+  }
+  FilterAfterMsrRead (Index, &Value);
+
+  return Value;
 }
 

MdePkg/Library/BaseLib/X64/WriteMsr64.c

@@ -1,7 +1,7 @@
 /** @file
   CpuBreakpoint function.
 
-  Copyright (c) 2006 - 2010, Intel Corporation. All rights reserved.<BR>
+  Copyright (c) 2006 - 2021, Intel Corporation. All rights reserved.<BR>
   SPDX-License-Identifier: BSD-2-Clause-Patent
 
 **/
@@ -10,6 +10,8 @@
   Microsoft Visual Studio 7.1 Function Prototypes for I/O Intrinsics.
 **/
 
+#include <Library/RegisterFilterLib.h>
+
 void __writemsr (unsigned long Register, unsigned __int64 Value);
 
 #pragma intrinsic(__writemsr)
@@ -30,7 +32,14 @@ AsmWriteMsr64 (
   IN UINT64  Value
   )
 {
-  __writemsr (Index, Value);
+  BOOLEAN                           Flag;
+
+  Flag = FilterBeforeMsrWrite (Index, &Value);
+  if (Flag) {
+    __writemsr (Index, Value);
+  }
+  FilterAfterMsrWrite (Index, &Value);
+
   return Value;
 }