mirror of https://github.com/acidanthera/audk.git
ArmPkg: allow dynamic GIC base addresses
Allow the PCDs gArmTokenSpaceGuid.PcdGicDistributorBase and gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase to be redeclared as PcdsDynamic by the platform, so virtual machines can set these properties during boot. As the PcdGet32() calls now call into the PCD database, cache the values that are required during the handling of interrupts. Contributed-under: TianoCore Contribution Agreement 1.0 Acked-by: Laszlo Ersek <lersek@redhat.com> Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Signed-off-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@16072 6f19259b-4bc3-4df7-8a09-765794883524
This commit is contained in:
Ard Biesheuvel
oliviermartin
parent
e1e2e66cd6
commit
dc63be2495
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@ -81,13 +81,6 @@
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gArmTokenSpaceGuid.PcdCpuVectorBaseAddress|0xffff0000|UINT32|0x00000004
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gArmTokenSpaceGuid.PcdCpuResetAddress|0x00000000|UINT32|0x00000005
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#
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# ARM Generic Interrupt Controller
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#
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gArmTokenSpaceGuid.PcdGicDistributorBase|0|UINT32|0x0000000C
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gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase|0|UINT32|0x0000000D
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gArmTokenSpaceGuid.PcdGicSgiIntId|0|UINT32|0x00000025
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#
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# ARM Secure Firmware PCDs
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#
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@ -216,6 +209,10 @@
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gArmTokenSpaceGuid.PcdArmLinuxFdtAlignment|0x00200000|UINT32|0x00000026
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#
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# These PCDs are also defined as 'PcdsDynamic' to be redefined when using UEFI in a
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# context of virtual machine.
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#
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[PcdsFixedAtBuild.common, PcdsDynamic.common]
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#
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# ARM Architectural Timer
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@ -227,3 +224,10 @@
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gArmTokenSpaceGuid.PcdArmArchTimerIntrNum|30|UINT32|0x00000036
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gArmTokenSpaceGuid.PcdArmArchTimerHypIntrNum|26|UINT32|0x00000040
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gArmTokenSpaceGuid.PcdArmArchTimerVirtIntrNum|27|UINT32|0x00000041
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#
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# ARM Generic Interrupt Controller
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#
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gArmTokenSpaceGuid.PcdGicDistributorBase|0|UINT32|0x0000000C
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gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase|0|UINT32|0x0000000D
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gArmTokenSpaceGuid.PcdGicSgiIntId|0|UINT32|0x00000025
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@ -43,12 +43,13 @@
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MemoryAllocationLib
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UefiDriverEntryPoint
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IoLib
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PcdLib
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[Protocols]
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gHardwareInterruptProtocolGuid
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gEfiCpuArchProtocolGuid
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[FixedPcd.common]
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[Pcd.common]
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gArmTokenSpaceGuid.PcdGicDistributorBase
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gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase
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@ -29,6 +29,9 @@ Abstract:
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extern EFI_HARDWARE_INTERRUPT_PROTOCOL gHardwareInterruptV2Protocol;
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UINT32 mGicInterruptInterfaceBase;
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UINT32 mGicDistributorBase;
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/**
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Enable interrupt source Source.
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@ -51,7 +54,7 @@ GicV2EnableInterruptSource (
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return EFI_UNSUPPORTED;
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}
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ArmGicEnableInterrupt (FixedPcdGet32 (PcdGicDistributorBase), Source);
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ArmGicEnableInterrupt (mGicDistributorBase, Source);
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return EFI_SUCCESS;
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}
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@ -78,7 +81,7 @@ GicV2DisableInterruptSource (
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return EFI_UNSUPPORTED;
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}
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ArmGicDisableInterrupt (FixedPcdGet32 (PcdGicDistributorBase), Source);
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ArmGicDisableInterrupt (mGicDistributorBase, Source);
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return EFI_SUCCESS;
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}
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@ -107,7 +110,7 @@ GicV2GetInterruptSourceState (
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return EFI_UNSUPPORTED;
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}
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*InterruptState = ArmGicIsInterruptEnabled (FixedPcdGet32 (PcdGicDistributorBase), Source);
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*InterruptState = ArmGicIsInterruptEnabled (mGicDistributorBase, Source);
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return EFI_SUCCESS;
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}
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@ -135,7 +138,7 @@ GicV2EndOfInterrupt (
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return EFI_UNSUPPORTED;
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}
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ArmGicV2EndOfInterrupt (FixedPcdGet32 (PcdGicInterruptInterfaceBase), Source);
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ArmGicV2EndOfInterrupt (mGicInterruptInterfaceBase, Source);
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return EFI_SUCCESS;
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}
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@ -160,7 +163,7 @@ GicV2IrqInterruptHandler (
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UINT32 GicInterrupt;
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HARDWARE_INTERRUPT_HANDLER InterruptHandler;
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GicInterrupt = ArmGicV2AcknowledgeInterrupt (FixedPcdGet32 (PcdGicInterruptInterfaceBase));
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GicInterrupt = ArmGicV2AcknowledgeInterrupt (mGicInterruptInterfaceBase);
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// Special Interrupts (ID1020-ID1023) have an Interrupt ID greater than the number of interrupt (ie: Spurious interrupt).
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if ((GicInterrupt & ARM_GIC_ICCIAR_ACKINTID) >= mGicNumInterrupts) {
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@ -216,7 +219,7 @@ GicV2ExitBootServicesEvent (
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// Acknowledge all pending interrupts
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do {
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GicInterrupt = ArmGicV2AcknowledgeInterrupt (FixedPcdGet32 (PcdGicInterruptInterfaceBase));
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GicInterrupt = ArmGicV2AcknowledgeInterrupt (mGicInterruptInterfaceBase);
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if ((GicInterrupt & ARM_GIC_ICCIAR_ACKINTID) < mGicNumInterrupts) {
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GicV2EndOfInterrupt (&gHardwareInterruptV2Protocol, GicInterrupt);
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@ -224,10 +227,10 @@ GicV2ExitBootServicesEvent (
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} while (!ARM_GIC_IS_SPECIAL_INTERRUPTS (GicInterrupt));
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// Disable Gic Interface
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ArmGicV2DisableInterruptInterface (FixedPcdGet32 (PcdGicInterruptInterfaceBase));
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ArmGicV2DisableInterruptInterface (mGicInterruptInterfaceBase);
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// Disable Gic Distributor
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ArmGicDisableDistributor (FixedPcdGet32 (PcdGicDistributorBase));
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ArmGicDisableDistributor (mGicDistributorBase);
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}
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/**
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@ -256,7 +259,9 @@ GicV2DxeInitialize (
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// Make sure the Interrupt Controller Protocol is not already installed in the system.
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ASSERT_PROTOCOL_ALREADY_INSTALLED (NULL, &gHardwareInterruptProtocolGuid);
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mGicNumInterrupts = ArmGicGetMaxNumInterrupts (FixedPcdGet32 (PcdGicDistributorBase));
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mGicInterruptInterfaceBase = PcdGet32 (PcdGicInterruptInterfaceBase);
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mGicDistributorBase = PcdGet32 (PcdGicDistributorBase);
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mGicNumInterrupts = ArmGicGetMaxNumInterrupts (mGicDistributorBase);
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for (Index = 0; Index < mGicNumInterrupts; Index++) {
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GicV2DisableInterruptSource (&gHardwareInterruptV2Protocol, Index);
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@ -265,7 +270,7 @@ GicV2DxeInitialize (
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RegOffset = Index / 4;
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RegShift = (Index % 4) * 8;
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MmioAndThenOr32 (
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FixedPcdGet32 (PcdGicDistributorBase) + ARM_GIC_ICDIPR + (4 * RegOffset),
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mGicDistributorBase + ARM_GIC_ICDIPR + (4 * RegOffset),
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~(0xff << RegShift),
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ARM_GIC_DEFAULT_PRIORITY << RegShift
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);
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@ -282,28 +287,28 @@ GicV2DxeInitialize (
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//
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// Read the first Interrupt Processor Targets Register (that corresponds to the 4
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// first SGIs)
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CpuTarget = MmioRead32 (FixedPcdGet32 (PcdGicDistributorBase) + ARM_GIC_ICDIPTR);
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CpuTarget = MmioRead32 (mGicDistributorBase + ARM_GIC_ICDIPTR);
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// The CPU target is a bit field mapping each CPU to a GIC CPU Interface. This value
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// is 0 when we run on a uniprocessor platform.
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if (CpuTarget != 0) {
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// The 8 first Interrupt Processor Targets Registers are read-only
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for (Index = 8; Index < (mGicNumInterrupts / 4); Index++) {
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MmioWrite32 (FixedPcdGet32 (PcdGicDistributorBase) + ARM_GIC_ICDIPTR + (Index * 4), CpuTarget);
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MmioWrite32 (mGicDistributorBase + ARM_GIC_ICDIPTR + (Index * 4), CpuTarget);
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}
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}
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// Set binary point reg to 0x7 (no preemption)
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MmioWrite32 (FixedPcdGet32 (PcdGicInterruptInterfaceBase) + ARM_GIC_ICCBPR, 0x7);
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MmioWrite32 (mGicInterruptInterfaceBase + ARM_GIC_ICCBPR, 0x7);
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// Set priority mask reg to 0xff to allow all priorities through
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MmioWrite32 (FixedPcdGet32 (PcdGicInterruptInterfaceBase) + ARM_GIC_ICCPMR, 0xff);
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MmioWrite32 (mGicInterruptInterfaceBase + ARM_GIC_ICCPMR, 0xff);
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// Enable gic cpu interface
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ArmGicEnableInterruptInterface (FixedPcdGet32 (PcdGicInterruptInterfaceBase));
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ArmGicEnableInterruptInterface (mGicInterruptInterfaceBase);
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// Enable gic distributor
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ArmGicEnableDistributor (FixedPcdGet32 (PcdGicDistributorBase));
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ArmGicEnableDistributor (mGicDistributorBase);
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Status = InstallAndRegisterInterruptService (
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&gHardwareInterruptV2Protocol, GicV2IrqInterruptHandler, GicV2ExitBootServicesEvent);
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@ -48,6 +48,7 @@
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DebugLib
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DevicePathLib
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HobLib
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PcdLib
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PerformanceLib
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SerialPortLib
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FdtLib
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@ -91,7 +92,7 @@
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[FixedPcd.ARM]
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gArmTokenSpaceGuid.PcdArmLinuxAtagMaxOffset
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[FixedPcd.AARCH64]
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[Pcd.AARCH64]
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gArmTokenSpaceGuid.PcdGicDistributorBase
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gArmTokenSpaceGuid.PcdGicSgiIntId
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