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ArmPkg/GenericWatchdogDxe: Split 64bit register write to 2x32bit 

According to the SBSA specification the Watchdog Compare
Register is split into two separate 32bit registers.
EDK2 code uses a single 64bit transaction to update
them, which can be problematic, depending on the SoC
implementation and could result in unpredictable behavior.

Fix this by modifying WatchdogWriteCompareRegister routine to
use two consecutive 32bit writes to the Watchdog Compare Register
Low and High, using new dedicated macros.

Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Marcin Wojtas <mw@semihalf.com>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
This commit is contained in:
Marcin Wojtas 2018-08-02 22:50:54 +02:00 committed by Ard Biesheuvel
parent 1d802e234e
commit dd4cae4d82
2 changed files with 4 additions and 2 deletions
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3
ArmPkg/Drivers/GenericWatchdogDxe/GenericWatchdog.h
View File

@ -20,7 +20,8 @@
// Control Frame:
#define GENERIC_WDOG_CONTROL_STATUS_REG ((UINTN)FixedPcdGet64 (PcdGenericWatchdogControlBase) + 0x000)
#define GENERIC_WDOG_OFFSET_REG ((UINTN)FixedPcdGet64 (PcdGenericWatchdogControlBase) + 0x008)
#define GENERIC_WDOG_COMPARE_VALUE_REG ((UINTN)FixedPcdGet64 (PcdGenericWatchdogControlBase) + 0x010)
#define GENERIC_WDOG_COMPARE_VALUE_REG_LOW ((UINTN)FixedPcdGet64 (PcdGenericWatchdogControlBase) + 0x010)
#define GENERIC_WDOG_COMPARE_VALUE_REG_HIGH ((UINTN)FixedPcdGet64 (PcdGenericWatchdogControlBase) + 0x014)
// Values of bit 0 of the Control/Status Register
#define GENERIC_WDOG_ENABLED 1

3
ArmPkg/Drivers/GenericWatchdogDxe/GenericWatchdogDxe.c
View File

@ -56,7 +56,8 @@ WatchdogWriteCompareRegister (
UINT64 Value
)
{
MmioWrite64 (GENERIC_WDOG_COMPARE_VALUE_REG, Value);
MmioWrite32 (GENERIC_WDOG_COMPARE_VALUE_REG_LOW, Value & MAX_UINT32);
MmioWrite32 (GENERIC_WDOG_COMPARE_VALUE_REG_HIGH, (Value >> 32) & MAX_UINT32);
}
VOID