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Check in implementation in GNU assembly for Thunk16.S in BaseLib.
git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@4614 6f19259b-4bc3-4df7-8a09-765794883524
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#------------------------------------------------------------------------------
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#
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# Copyright (c) 2006 - 2008, Intel Corporation
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# All rights reserved. This program and the accompanying materials
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# are licensed and made available under the terms and conditions of the BSD License
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# which accompanies this distribution. The full text of the license may be found at
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# http://opensource.org/licenses/bsd-license.php
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#
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# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
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# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
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#
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# Module Name:
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#
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# Thunk16.S
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#
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# Abstract:
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#
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# Real mode thunk
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#
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#------------------------------------------------------------------------------
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#include <Library/BaseLib.h>
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# define the structure of IA32_REGS
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.equ _EDI, 0 #size 4
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.equ _ESI, 4 #size 4
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.equ _EBP, 8 #size 4
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.equ _ESP, 12 #size 4
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.equ _EBX, 16 #size 4
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.equ _EDX, 20 #size 4
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.equ _ECX, 24 #size 4
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.equ _EAX, 28 #size 4
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.equ _DS, 32 #size 2
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.equ _ES, 34 #size 2
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.equ _FS, 36 #size 2
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.equ _GS, 38 #size 2
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.equ _EFLAGS, 40 #size 8
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.equ _EIP, 48 #size 4
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.equ _CS, 52 #size 2
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.equ _SS, 54 #size 2
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.equ IA32_REGS_SIZE, 56
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.data
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m16Size: .word _InternalAsmThunk16 - m16Start
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mThunk16Attr: .word _ThunkAttr - m16Start
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m16Gdt: .word _NullSeg - m16Start
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m16GdtrBase: .word _16GdtrBase - m16Start
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mTransition: .word _EntryPoint - m16Start
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.text
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m16Start:
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SavedGdt: .space 10
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#------------------------------------------------------------------------------
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# _BackFromUserCode() takes control in real mode after 'retf' has been executed
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# by user code. It will be shadowed to somewhere in memory below 1MB.
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#------------------------------------------------------------------------------
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.globl ASM_PFX(BackFromUserCode)
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ASM_PFX(BackFromUserCode):
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#
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# The order of saved registers on the stack matches the order they appears
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# in IA32_REGS structure. This facilitates wrapper function to extract them
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# into that structure.
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#
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# Some instructions for manipulation of segment registers have to be written
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# in opcode since 64-bit MASM prevents accesses to those registers.
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#
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.byte 0x16 # push ss
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.byte 0xe # push cs
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.byte 0x66
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call @Base # push eip
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@Base:
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.byte 0x66
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pushq $0 # reserved high order 32 bits of EFlags
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.byte 0x66, 0x9c # pushfd actually
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cli # disable interrupts
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push %gs
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push %fs
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.byte 6 # push es
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.byte 0x1e # push ds
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.byte 0x66,0x60 # pushad
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.byte 0x66,0xba # mov edx, imm32
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_ThunkAttr: .space 4
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testb $THUNK_ATTRIBUTE_DISABLE_A20_MASK_INT_15, %dl
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jz @1
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movl $0x15cd2401,%eax # mov ax, 2401h & int 15h
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cli # disable interrupts
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jnc @2
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@1:
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testb $THUNK_ATTRIBUTE_DISABLE_A20_MASK_KBD_CTRL, %dl
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jz @2
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inb $0x92,%al
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orb $2,%al
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outb %al, $0x92 # deactivate A20M#
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@2:
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movl %ss,%eax
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lea IA32_REGS_SIZE(%esp), %bp
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#
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# rsi in the following 2 instructions is indeed bp in 16-bit code
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#
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movw %bp, (_ESP - IA32_REGS_SIZE)(%rsi)
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.byte 0x66
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movl (_EIP - IA32_REGS_SIZE)(%rsi), %ebx
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shlw $4,%ax # shl eax, 4
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addw %ax,%bp # add ebp, eax
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movw %cs,%ax
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shlw $4,%ax
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lea (@64BitCode - @Base)(%ebx, %eax), %ax
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.byte 0x66,0x2e,0x89,0x87 # mov cs:[bx + (@64Eip - @Base)], eax
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.word @64Eip - @Base
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.byte 0x66,0xb8 # mov eax, imm32
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SavedCr4: .space 4
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movq %rax, %cr4
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#
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# rdi in the instruction below is indeed bx in 16-bit code
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#
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.byte 0x66,0x2e # 2eh is "cs:" segment override
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lgdt (SavedGdt - @Base)(%rdi)
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.byte 0x66
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movl $0xc0000080,%ecx
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rdmsr
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orb $1,%ah
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wrmsr
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.byte 0x66,0xb8 # mov eax, imm32
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SavedCr0: .space 4
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movq %rax, %cr0
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.byte 0x66,0xea # jmp far cs:@64Bit
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@64Eip: .space 4
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SavedCs: .space 2
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@64BitCode:
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movq %r8, %rsp
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ret
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_EntryPoint: .long ASM_PFX(ToUserCode) - m16Start
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.word CODE16
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_16Gdtr: .word GDT_SIZE - 1
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_16GdtrBase: .quad $_NullSeg
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_16Idtr: .word 0x3ff
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.long 0
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#------------------------------------------------------------------------------
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# _ToUserCode() takes control in real mode before passing control to user code.
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# It will be shadowed to somewhere in memory below 1MB.
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#------------------------------------------------------------------------------
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.globl ASM_PFX(ToUserCode)
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ASM_PFX(ToUserCode):
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movl %edx,%ss # set new segment selectors
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movl %edx,%ds
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movl %edx,%es
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movl %edx,%fs
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movl %edx,%gs
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.byte 0x66
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movl $0xc0000080,%ecx
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movq %rax, %cr0
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rdmsr
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andb $0b11111110, %ah
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wrmsr
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movq %rbp, %cr4
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movl %esi,%ss # set up 16-bit stack segment
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movw %bx,%sp # set up 16-bit stack pointer
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.byte 0x66 # make the following call 32-bit
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call @Base1 # push eip
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@Base1:
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popw %bp # ebp <- address of @Base1
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pushq (IA32_REGS_SIZE + 2)(%esp)
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lea 0x0c(%rsi), %eax
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pushq %rax
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lret # execution begins at next instruction
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@RealMode:
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.byte 0x66,0x2e # CS and operand size override
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lidt (_16Idtr - @Base1)(%rsi)
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.byte 0x66,0x61 # popad
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.byte 0x1f # pop ds
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.byte 0x7 # pop es
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.byte 0x0f, 0xa1 # pop fs
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.byte 0x0f, 0xa9 # pop gs
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.byte 0x66, 0x9d # popfd
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leaw 4(%esp),%sp # skip high order 32 bits of EFlags
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.byte 0x66 # make the following retf 32-bit
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lret # transfer control to user code
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.equ CODE16, ASM_PFX(16Code) - .
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.equ DATA16, ASM_PFX(16Data) - .
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.equ DATA32, ASM_PFX(32Data) - .
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_NullSeg: .quad 0
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ASM_PFX(16Code):
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.word -1
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.word 0
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.byte 0
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.byte 0x9b
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.byte 0x8f # 16-bit segment, 4GB limit
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.byte 0
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ASM_PFX(16Data):
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.word -1
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.word 0
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.byte 0
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.byte 0x93
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.byte 0x8f # 16-bit segment, 4GB limit
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.byte 0
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ASM_PFX(32Data):
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.word -1
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.word 0
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.byte 0
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.byte 0x93
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.byte 0xcf # 16-bit segment, 4GB limit
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.byte 0
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.equ GDT_SIZE, . - ASM_PFX(NullSeg)
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#------------------------------------------------------------------------------
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# IA32_REGISTER_SET *
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# EFIAPI
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# InternalAsmThunk16 (
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# IN IA32_REGISTER_SET *RegisterSet,
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# IN OUT VOID *Transition
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# );
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#------------------------------------------------------------------------------
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# MISMATCH: "InternalAsmThunk16 PROC USES rbp rbx rsi rdi"
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.globl ASM_PFX(InternalAsmThunk16)
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ASM_PFX(InternalAsmThunk16):
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pushq %rbp
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pushq %rbx
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pushq %rsi
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pushq %rdi
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movl %ds, %r10d # r9 ~ r11 are not accessible in 16-bit
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movl %es, %r11d # so use them for saving seg registers
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movl %ss, %r9d
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.byte 0x0f, 0xa0 #push fs
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.byte 0x0f, 0xa8 #push gs
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movq %rcx, %rsi
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movzwl _SS(%rsi), %r8d
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movl _ESP(%rsi), %edi
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lea -(IA32_REGS_SIZE + 4)(%edi), %rdi
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imul $16, %r8d, %eax
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movl %edi,%ebx # ebx <- stack for 16-bit code
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pushq $(IA32_REGS_SIZE / 4)
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addl %eax,%edi # edi <- linear address of 16-bit stack
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popq %rcx
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rep
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movsl # copy RegSet
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lea (SavedCr4 - m16Start)(%rdx), %ecx
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movl %edx,%eax # eax <- transition code address
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andl $0xf,%edx
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shll $12,%eax # segment address in high order 16 bits
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lea (_BackFromUserCode - m16Start)(%rdx), %ax
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stosl # [edi] <- return address of user code
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sgdt (SavedGdt - SavedCr4)(%rcx)
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sidt 0x38(%rsp)
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movq %cr0, %rax
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movl %eax, (SavedCr0 - SavedCr4)(%rcx)
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andl $0x7ffffffe,%eax # clear PE, PG bits
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movq %cr4, %rbp
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movl %ebp, (%rcx) # save CR4 in SavedCr4
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andl $0x300,%ebp # clear all but PCE and OSFXSR bits
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movl %r8d, %esi # esi <- 16-bit stack segment
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.byte 0x6a, DATA32
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popq %rdx
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lgdt (_16Gdtr - SavedCr4)(%rcx)
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movl %edx,%ss
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pushfq
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lea -8(%rdx), %edx
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lea @RetFromRealMode, %r8
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pushq %r8
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movl %cs, %r8d
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movw %r8w, (SavedCs - SavedCr4)(%rcx)
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movq %rsp, %r8
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.byte 0xff, 0x69 # jmp (_EntryPoint - SavedCr4)(%rcx)
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.byte _EntryPoint - SavedCr4
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@RetFromRealMode:
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popfq
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lidt 0x38(%rsp)
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lea -IA32_REGS_SIZE(%rbp), %eax
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.byte 0x0f, 0xa9 # pop gs
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.byte 0x0f, 0xa1 # pop fs
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movl %r9d, %ss
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movl %r11d, %es
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movl %r10d, %ds
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popq %rdi
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popq %rsi
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popq %rbx
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popq %rbp
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ret
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